| /hal_nxp-3.6.0/s32/drivers/s32k3/Pwm/src/ |
| D | Emios_Pwm_Ip.c | 236 uint8 Channel, in Emios_Pwm_Ip_ValidateMode() argument
242 …Ret = (((Emios_Pwm_Ip_aChannelModes[Instance][(uint8)Mode] >> Channel) & 0x01UL) == 1UL) ? TRUE : … in Emios_Pwm_Ip_ValidateMode()
248 (void) Channel; in Emios_Pwm_Ip_ValidateMode()
264 uint8 Channel, in Emios_Pwm_Ip_GetCounterBusPeriod() argument
269 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > Channel); in Emios_Pwm_Ip_GetCounterBusPeriod()
273 uint8 MasterBusCh = Emios_Pwm_Ip_GetTimebaseChannel(Channel, CounterBus); in Emios_Pwm_Ip_GetCounterBusPeriod()
293 uint8 Channel, in Emios_Pwm_Ip_GetCounterBusMode() argument
305 … = (Emios_Pwm_Ip_MasterBusModeType)Emios_Pwm_Ip_GetChannelPwmMode(Base, (Channel & (uint8)EMIOS_PW… in Emios_Pwm_Ip_GetCounterBusMode()
469 uint8 Channel, in Emios_Pwm_Ip_SetDutyCycleOpwfmb() argument
474 DevAssert(EMIOS_PWM_IP_CHANNEL_COUNT > Channel); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
[all …]
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| D | Emios_Pwm_Ip_Irq.c | 207 static void Emios_Pwm_Ip_IrqDaocHandler(uint8 Instance, uint8 Channel) in Emios_Pwm_Ip_IrqDaocHandler() argument
212 …Ip_GetUCRegA(Emios_Pwm_Ip_aBasePtr[Instance], Emios_Pwm_Ip_GetMasterBusChannel(Instance, Channel)); in Emios_Pwm_Ip_IrqDaocHandler()
214 …_Ip_PolarityType Polarity = Emios_Pwm_Ip_GetEdgePolarity(Emios_Pwm_Ip_aBasePtr[Instance], Channel); in Emios_Pwm_Ip_IrqDaocHandler()
215 boolean OutputPin = Emios_Pwm_Ip_GetOutputPinState(Emios_Pwm_Ip_aBasePtr[Instance], Channel); in Emios_Pwm_Ip_IrqDaocHandler()
217 …WM_IP_MODE_DAOC_FLAG == Emios_Pwm_Ip_aCurrentModes[eMios_Pwm_Ip_IndexInChState[Instance][Channel]]) in Emios_Pwm_Ip_IrqDaocHandler()
219 …ios_Pwm_Ip_IndexInChState[Instance][Channel]] - Emios_Pwm_Ip_aDutyCycle[eMios_Pwm_Ip_IndexInChStat… in Emios_Pwm_Ip_IrqDaocHandler()
220 …DaocRegA = ((DaocDuty + Emios_Pwm_Ip_GetUCRegB(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) % Counte… in Emios_Pwm_Ip_IrqDaocHandler()
222 …Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_aBasePtr[Instance], Channel, (DaocRegA == 0U)? CounterMax : Da… in Emios_Pwm_Ip_IrqDaocHandler()
224 …[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] + Emios_Pwm_Ip_GetUCRegB(Emios_Pwm_Ip_aBasePtr[In… in Emios_Pwm_Ip_IrqDaocHandler()
225 …Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_aBasePtr[Instance], Channel, (DaocRegB == 0U)? CounterMax : Da… in Emios_Pwm_Ip_IrqDaocHandler()
[all …]
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Pwm/include/ |
| D | Emios_Pwm_Ip_HwAccess.h | 152 uint8 Channel, in Emios_Pwm_Ip_SetOutputUpdate() argument
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
164 uint8 Channel) in Emios_Pwm_Ip_GetOutputUpdate() argument
166 …return (((Base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == … in Emios_Pwm_Ip_GetOutputUpdate()
186 uint8 Channel, in Emios_Pwm_Ip_SetChannelEnable() argument
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetChannelEnable()
199 uint8 Channel) in Emios_Pwm_Ip_GetChannelEnable() argument
201 …Base->UCDIS & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)Channel)) >> Channel) == 0U) ? T… in Emios_Pwm_Ip_GetChannelEnable()
212 uint8 Channel, in Emios_Pwm_Ip_SetUCRegA() argument
215 Base->CH.UC[Channel].A = eMIOS_A_A(Value); in Emios_Pwm_Ip_SetUCRegA()
[all …]
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| D | Emios_Pwm_Ip.h | 137 uint8 Channel);
149 uint8 Channel,
162 uint8 Channel,
174 uint8 Channel);
185 uint8 Channel,
196 uint8 Channel);
209 uint8 Channel,
220 uint8 Channel);
231 uint8 Channel,
242 uint8 Channel);
[all …]
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| D | Emios_Pwm_Ip_Irq.h | 86 void Emios_Pwm_Ip_IrqHandler(uint8 Instance, uint8 Channel);
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX9352/iar/ |
| D | startup_MIMX9352_cm33.s | 169 DCD DMA3_0_IRQHandler ;eDMA1 Channel 0 interrupt
170 DCD DMA3_1_IRQHandler ;eDMA1 Channel 1 interrupt
171 DCD DMA3_2_IRQHandler ;eDMA1 Channel 2 interrupt
172 DCD DMA3_3_IRQHandler ;eDMA1 Channel 3 interrupt
173 DCD DMA3_4_IRQHandler ;eDMA1 Channel 4 interrupt
174 DCD DMA3_5_IRQHandler ;eDMA1 Channel 5 interrupt
175 DCD DMA3_6_IRQHandler ;eDMA1 Channel 6 interrupt
176 DCD DMA3_7_IRQHandler ;eDMA1 Channel 7 interrupt
177 DCD DMA3_8_IRQHandler ;eDMA1 Channel 8 interrupt
178 DCD DMA3_9_IRQHandler ;eDMA1 Channel 9 interrupt
[all …]
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip_Hw_Access.c | 472 uint8 Channel) in GMAC_RxIRQHandler() argument
474 Gmac_Ip_ChannelType *ChBase = Gmac_apxChBases[Instance][Channel]; in GMAC_RxIRQHandler()
489 if (Gmac_apxState[Instance]->RxChCallback[Channel] != NULL_PTR) in GMAC_RxIRQHandler()
491 Gmac_apxState[Instance]->RxChCallback[Channel](Instance, Channel); in GMAC_RxIRQHandler()
512 uint8 Channel) in GMAC_TxIRQHandler() argument
514 Gmac_Ip_ChannelType *ChBase = Gmac_apxChBases[Instance][Channel]; in GMAC_TxIRQHandler()
529 if (Gmac_apxState[Instance]->TxChCallback[Channel] != NULL_PTR) in GMAC_TxIRQHandler()
531 Gmac_apxState[Instance]->TxChCallback[Channel](Instance, Channel); in GMAC_TxIRQHandler()
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| D | Gmac_Ip.c | 2336 uint8 Channel) in Gmac_Ip_GetChInterruptFlags() argument
2342 Base = Gmac_apxChBases[Instance][Channel]; in Gmac_Ip_GetChInterruptFlags()
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Mcl/src/ |
| D | Emios_Mcl_Ip.c | 437 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel) in Emios_Mcl_Ip_GetCounterBusPeriod() argument
439 uint16 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel) in Emios_Mcl_Ip_GetCounterBusPeriod()
444 DevAssert(Channel < eMIOS_CH_UC_UC_COUNT); in Emios_Mcl_Ip_GetCounterBusPeriod()
448 uint32 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel]; in Emios_Mcl_Ip_GetCounterBusPeriod()
450 uint16 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel]; in Emios_Mcl_Ip_GetCounterBusPeriod()
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Mcl/include/ |
| D | Emios_Mcl_Ip.h | 234 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel);
236 uint16 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel);
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/include/ |
| D | Gmac_Ip_Hw_Access.h | 252 uint8 Channel);
264 uint8 Channel);
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| D | Gmac_Ip.h | 520 uint8 Channel);
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| D | Gmac_Ip_Types.h | 502 typedef void (*Gmac_Ip_ChCallbackType)(const uint8 Instance, const uint8 Channel);
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| /hal_nxp-3.6.0/mcux/mcux-sdk/components/rtt/ |
| D | README.txt | 10 - Main_RTT_InputEchoApp.c - Sample application which echoes input on Channel 0.
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| /hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/ |
| D | Clock_Ip_Frequency.c | 170 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin);
4220 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin) in DFS_OUTPUT() argument
4230 …Mfi = ((Base->DVPORT[Channel] & DFS_DVPORT_MFI_MASK) >> DFS_DVPORT_MFI_SHIFT); /* Mfi… in DFS_OUTPUT()
4231 …Mfn = ((Base->DVPORT[Channel] & DFS_DVPORT_MFN_MASK) >> DFS_DVPORT_MFN_SHIFT); /* Mfn… in DFS_OUTPUT()
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| /hal_nxp-3.6.0/s32/drivers/s32ze/EthSwt_NETC/include/ |
| D | Netc_EthSwt_Ip_Types.h | 140 typedef void (*Netc_EthSwt_Ip_ChCallbackType)(uint8 Instance, uint8 Channel);
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