Searched refs:CSSELR (Results 1 – 10 of 10) sorted by relevance
150 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()188 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()244 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()279 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()314 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
485 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member2334 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()2372 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()2410 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()2445 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()2480 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
522 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
109 …__IO uint32_t CSSELR; /**< Cache Size Selection Register, offset: 0xD84… member
108 …__IO uint32_t CSSELR; /**< Cache Size Selection Register, offset: 0xD84… member
