CLOCK_IP_PLL_OUT (reference) in projects: hal_nxp-3.6.0

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Searched refs:CLOCK_IP_PLL_OUT (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Data.c	107 #define CLOCK_IP_PLL_OUT 3U macro 705 /* PERIPHPLL_PHI0 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 706 / PERIPHPLL_PHI1 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 707 / PERIPHPLL_PHI2 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 708 / PERIPHPLL_PHI3 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 709 / PERIPHPLL_PHI4 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 710 / PERIPHPLL_PHI5 clock / {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, … 711 / PERIPHPLL_PHI6 clock */ {CLOCK_IP_PERIPHPLL_INSTANCE, CLOCK_IP_PLL_OUT, …
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Data.c	`110 #define CLOCK_IP_PLL_OUT 5U macro 1035 /* PLL_PHI1_CLK clock / {CLOCK_IP_PLL_INSTANCE, CLOCK_IP_PLL_OUT, 0U, … 1037 / PLLAUX_PHI0_CLK clock / {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, … 1040 / PLLAUX_PHI1_CLK clock / {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, … 1043 / PLLAUX_PHI2_CLK clock */ {CLOCK_IP_PLLAUX_INSTANCE, CLOCK_IP_PLL_OUT, 0U, …`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
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babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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