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Searched refs:CH3STAT_TOG (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8332 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h9050 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10614 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10630 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11656 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12898 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12900 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12441 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13267 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h14053 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h14127 …__IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC… member