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Searched refs:CH3OPTS_CLR (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8335 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h9053 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10617 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10633 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11659 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12901 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12903 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12444 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h13270 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h14056 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h14130 …__IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F… member