Searched refs:CH2STAT_CLR (Results 1 – 12 of 12) sorted by relevance
| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/dcp/ |
| D | fsl_dcp.c | 191 chStatClrPtr = &base->CH2STAT_CLR; in dcp_clear_channel_status()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 8319 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 9037 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 10601 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 10617 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 11643 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 12885 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 12887 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 12428 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 13254 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 14040 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 14114 …__IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8… member
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