| /hal_nxp-3.6.0/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/ |
| D | xcvr_test_fsk.c | 140 t3 = XCVR_PHY->CFG1; in XcvrFskGetInstantRssi()
166 uint32_t temp = XCVR_PHY->CFG1; in XcvrFskGetInstantRssi()
169 XCVR_PHY->CFG1 = temp; in XcvrFskGetInstantRssi()
183 XCVR_PHY->CFG1 = t3; in XcvrFskGetInstantRssi()
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/adc12/ |
| D | fsl_adc12.c | 145 tmp32 = (base->CFG1 & ~(ADC_CFG1_ADICLK_MASK | ADC_CFG1_ADIV_MASK | ADC_CFG1_MODE_MASK)); in ADC12_Init()
148 base->CFG1 = tmp32; in ADC12_Init()
298 saveCFG1 = base->CFG1; in ADC12_DoAutoCalibration()
300 base->CFG1 |= ADC_CFG1_ADIV(1); in ADC12_DoAutoCalibration()
350 base->CFG1 = saveCFG1; in ADC12_DoAutoCalibration()
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/flexcomm/i2s/ |
| D | fsl_i2s.h | 398 base->CFG1 |= I2S_CFG1_MAINENABLE(1U); in I2S_Enable()
434 base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); in I2S_Disable()
|
| D | fsl_i2s.c | 358 base->CFG1 = cfg1; in I2S_Config()
563 …handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U … in I2S_TxTransferCreateHandle()
564 …handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1… in I2S_TxTransferCreateHandle()
667 …handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL… in I2S_RxTransferCreateHandle()
668 …handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1… in I2S_RxTransferCreateHandle()
|
| D | fsl_i2s_dma.c | 207 …handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT… in I2S_TxTransferCreateHandleDMA()
211 if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) in I2S_TxTransferCreateHandleDMA()
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/components/silicon_id/socs/rt10xx/ |
| D | fsl_silicon_id_soc.c | 15 *((uint32_t *)(uintptr_t)&uid[4]) = OCOTP->CFG1; in SILICONID_ReadUniqueID()
|
| /hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_CANXL_MSG_DESCRIPTORS.h | 83 } CFG1; member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/adc16/ |
| D | fsl_adc16.c | 86 base->CFG1 = tmp32; in ADC16_Init()
|
| /hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K144W_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K144_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K116_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K118_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K142W_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K142_ADC.h | 79 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K146_ADC.h | 94 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| D | S32K148_ADC.h | 94 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
|
| /hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/src/ |
| D | CanEXCEL_Ip_HwAccess.c | 263 base_Msg_Desc->MSGDSC[idx].CFG1.MDFLT1FD = 0U; in CanXL_ClearRAM()
|
| D | CanEXCEL_Ip.c | 376 CANEXCEL.EXL_MSGD[instance]->MSGDSC[descNo].CFG1.MDFLT1XL = mask; in Canexcel_Ip_SetRxIndividualMask()
380 CANEXCEL.EXL_MSGD[instance]->MSGDSC[descNo].CFG1.MDFLT1FD = mask; in Canexcel_Ip_SetRxIndividualMask()
|
| /hal_nxp-3.6.0/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ |
| D | fsl_xcvr.c | 617 XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; in XCVR_Configure()
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14F16/ |
| D | MKE14F16.h | 527 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
12508 …__I uint32_t CFG1; /**< Processor 0 Configuration Register, array of… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A31A/ |
| D | K32L2A31A.h | 425 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ member
10823 …__I uint32_t CFG1; /**< Processor 0 Configuration Register, array offset: 0x34, array step: 0x20… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A41A/ |
| D | K32L2A41A.h | 425 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ member
10823 …__I uint32_t CFG1; /**< Processor 0 Configuration Register, array offset: 0x34, array step: 0x20… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16F16/ |
| D | MKE16F16.h | 527 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
13507 …__I uint32_t CFG1; /**< Processor 0 Configuration Register, array of… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE18F16/ |
| D | MKE18F16.h | 527 …__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ member
13512 …__I uint32_t CFG1; /**< Processor 0 Configuration Register, array of… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL25Z4/ |
| D | MKL25Z4.h | 342 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ member
|
