1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CANXL_DSC_CONTROL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_CANXL_DSC_CONTROL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CANXL_DSC_CONTROL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CANXL_DSC_CONTROL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CANXL_DSC_CONTROL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CANXL_DSC_CONTROL_Peripheral_Access_Layer CANXL_DSC_CONTROL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CANXL_DSC_CONTROL - Size of Registers Arrays */ 72 #define CANXL_DSC_CONTROL_DSCMBCTRLAR_COUNT 128u 73 74 /** CANXL_DSC_CONTROL - Register Layout Typedef */ 75 typedef struct { 76 struct { /* offset: 0x0, array step: 0x20 */ 77 union { /* offset: 0x0, array step: 0x20 */ 78 __I uint32_t DCSTA; /**< Descriptor Control Status, array offset: 0x0, array step: 0x20 */ 79 } STA; 80 union { /* offset: 0x4, array step: 0x20 */ 81 __IO uint32_t DCSYSPUSH; /**< Descriptor Control System Push, array offset: 0x4, array step: 0x20 */ 82 } PUSHPOP; 83 union { /* offset: 0x8, array step: 0x20 */ 84 __IO uint32_t DCSYSLOCK; /**< Descriptor Control System Lock, array offset: 0x8, array step: 0x20 */ 85 } SYSLOCK; 86 uint8_t RESERVED_0[8]; 87 union { /* offset: 0x14, array step: 0x20 */ 88 __IO uint32_t DCACT; /**< Descriptor Control Activation, array offset: 0x14, array step: 0x20 */ 89 } ACT; 90 uint8_t RESERVED_1[8]; 91 } DSCMBCTRLAR[CANXL_DSC_CONTROL_DSCMBCTRLAR_COUNT]; 92 } CANXL_DSC_CONTROL_Type, *CANXL_DSC_CONTROL_MemMapPtr; 93 94 /** Number of instances of the CANXL_DSC_CONTROL module. */ 95 #define CANXL_DSC_CONTROL_INSTANCE_COUNT (2u) 96 97 /* CANXL_DSC_CONTROL - Peripheral instance base addresses */ 98 /** Peripheral CANXL_0__DSC_CONTROL base address */ 99 #define IP_CANXL_0__DSC_CONTROL_BASE (0x47424000u) 100 /** Peripheral CANXL_0__DSC_CONTROL base pointer */ 101 #define IP_CANXL_0__DSC_CONTROL ((CANXL_DSC_CONTROL_Type *)IP_CANXL_0__DSC_CONTROL_BASE) 102 /** Peripheral CANXL_1__DSC_CONTROL base address */ 103 #define IP_CANXL_1__DSC_CONTROL_BASE (0x47524000u) 104 /** Peripheral CANXL_1__DSC_CONTROL base pointer */ 105 #define IP_CANXL_1__DSC_CONTROL ((CANXL_DSC_CONTROL_Type *)IP_CANXL_1__DSC_CONTROL_BASE) 106 /** Array initializer of CANXL_DSC_CONTROL peripheral base addresses */ 107 #define IP_CANXL_DSC_CONTROL_BASE_ADDRS { IP_CANXL_0__DSC_CONTROL_BASE, IP_CANXL_1__DSC_CONTROL_BASE } 108 /** Array initializer of CANXL_DSC_CONTROL peripheral base pointers */ 109 #define IP_CANXL_DSC_CONTROL_BASE_PTRS { IP_CANXL_0__DSC_CONTROL, IP_CANXL_1__DSC_CONTROL } 110 111 /* ---------------------------------------------------------------------------- 112 -- CANXL_DSC_CONTROL Register Masks 113 ---------------------------------------------------------------------------- */ 114 115 /*! 116 * @addtogroup CANXL_DSC_CONTROL_Register_Masks CANXL_DSC_CONTROL Register Masks 117 * @{ 118 */ 119 120 /*! @name DCSTA - Descriptor Control Status */ 121 /*! @{ */ 122 123 #define CANXL_DSC_CONTROL_DCSTA_STATE_MASK (0x7U) 124 #define CANXL_DSC_CONTROL_DCSTA_STATE_SHIFT (0U) 125 #define CANXL_DSC_CONTROL_DCSTA_STATE_WIDTH (3U) 126 #define CANXL_DSC_CONTROL_DCSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_STATE_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_STATE_MASK) 127 128 #define CANXL_DSC_CONTROL_DCSTA_HWLOCK_MASK (0x40U) 129 #define CANXL_DSC_CONTROL_DCSTA_HWLOCK_SHIFT (6U) 130 #define CANXL_DSC_CONTROL_DCSTA_HWLOCK_WIDTH (1U) 131 #define CANXL_DSC_CONTROL_DCSTA_HWLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_HWLOCK_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_HWLOCK_MASK) 132 133 #define CANXL_DSC_CONTROL_DCSTA_SYSLOCK_MASK (0x80U) 134 #define CANXL_DSC_CONTROL_DCSTA_SYSLOCK_SHIFT (7U) 135 #define CANXL_DSC_CONTROL_DCSTA_SYSLOCK_WIDTH (1U) 136 #define CANXL_DSC_CONTROL_DCSTA_SYSLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_SYSLOCK_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_SYSLOCK_MASK) 137 138 #define CANXL_DSC_CONTROL_DCSTA_HWPOINTER_MASK (0x1F00U) 139 #define CANXL_DSC_CONTROL_DCSTA_HWPOINTER_SHIFT (8U) 140 #define CANXL_DSC_CONTROL_DCSTA_HWPOINTER_WIDTH (5U) 141 #define CANXL_DSC_CONTROL_DCSTA_HWPOINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_HWPOINTER_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_HWPOINTER_MASK) 142 143 #define CANXL_DSC_CONTROL_DCSTA_SYSPOINTER_MASK (0x1F0000U) 144 #define CANXL_DSC_CONTROL_DCSTA_SYSPOINTER_SHIFT (16U) 145 #define CANXL_DSC_CONTROL_DCSTA_SYSPOINTER_WIDTH (5U) 146 #define CANXL_DSC_CONTROL_DCSTA_SYSPOINTER(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_SYSPOINTER_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_SYSPOINTER_MASK) 147 148 #define CANXL_DSC_CONTROL_DCSTA_WTMARK_MASK (0xF000000U) 149 #define CANXL_DSC_CONTROL_DCSTA_WTMARK_SHIFT (24U) 150 #define CANXL_DSC_CONTROL_DCSTA_WTMARK_WIDTH (4U) 151 #define CANXL_DSC_CONTROL_DCSTA_WTMARK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSTA_WTMARK_SHIFT)) & CANXL_DSC_CONTROL_DCSTA_WTMARK_MASK) 152 /*! @} */ 153 154 /*! @name DCSYSPUSH - Descriptor Control System Push */ 155 /*! @{ */ 156 157 #define CANXL_DSC_CONTROL_DCSYSPUSH_PUSH_MASK (0xFU) 158 #define CANXL_DSC_CONTROL_DCSYSPUSH_PUSH_SHIFT (0U) 159 #define CANXL_DSC_CONTROL_DCSYSPUSH_PUSH_WIDTH (4U) 160 #define CANXL_DSC_CONTROL_DCSYSPUSH_PUSH(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSYSPUSH_PUSH_SHIFT)) & CANXL_DSC_CONTROL_DCSYSPUSH_PUSH_MASK) 161 /*! @} */ 162 163 /*! @name DCSYSLOCK - Descriptor Control System Lock */ 164 /*! @{ */ 165 166 #define CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK_MASK (0x1U) 167 #define CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK_SHIFT (0U) 168 #define CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK_WIDTH (1U) 169 #define CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK_SHIFT)) & CANXL_DSC_CONTROL_DCSYSLOCK_SYSLOCK_MASK) 170 /*! @} */ 171 172 /*! @name DCACT - Descriptor Control Activation */ 173 /*! @{ */ 174 175 #define CANXL_DSC_CONTROL_DCACT_ACT_MASK (0x1U) 176 #define CANXL_DSC_CONTROL_DCACT_ACT_SHIFT (0U) 177 #define CANXL_DSC_CONTROL_DCACT_ACT_WIDTH (1U) 178 #define CANXL_DSC_CONTROL_DCACT_ACT(x) (((uint32_t)(((uint32_t)(x)) << CANXL_DSC_CONTROL_DCACT_ACT_SHIFT)) & CANXL_DSC_CONTROL_DCACT_ACT_MASK) 179 /*! @} */ 180 181 /*! 182 * @} 183 */ /* end of group CANXL_DSC_CONTROL_Register_Masks */ 184 185 /*! 186 * @} 187 */ /* end of group CANXL_DSC_CONTROL_Peripheral_Access_Layer */ 188 189 #endif /* #if !defined(S32Z2_CANXL_DSC_CONTROL_H_) */ 190
