Home
last modified time | relevance | path

Searched refs:CACHE64_CTRL0_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2273 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2277 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2281 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }
2290 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
2292 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2294 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2273 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2277 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2281 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }
2290 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
2292 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2294 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7613 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7617 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7629 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
7638 #define CACHE64_CTRL0_BASE (0x40033000u) macro
7640 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7646 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7616 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7620 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7632 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
7641 #define CACHE64_CTRL0_BASE (0x40033000u) macro
7643 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7649 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7617 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7621 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7633 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
7642 #define CACHE64_CTRL0_BASE (0x40033000u) macro
7644 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
7650 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
DMIMXRT595S_dsp.h1468 #define CACHE64_CTRL0_BASE (0x40033000u) macro
1470 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
1476 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2272 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2276 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2280 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }
2289 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
2291 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
2293 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE }