1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_ADC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_ADC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_ADC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_ADC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ADC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ADC - Size of Registers Arrays */ 72 #define ADC_THRHLR_COUNT 4u 73 #define ADC_CDR1_COUNT 8u 74 #define ADC_CDR2_COUNT 24u 75 #define ADC_CDR3_COUNT 32u 76 #define ADC_CWSELRPI_COUNT 2u 77 #define ADC_CWSELRSI_COUNT 3u 78 #define ADC_CWSELREI_COUNT 4u 79 80 /** ADC - Register Layout Typedef */ 81 typedef struct { 82 __IO uint32_t MCR; /**< Main Configuration, offset: 0x0 */ 83 __I uint32_t MSR; /**< Main Status, offset: 0x4 */ 84 uint8_t RESERVED_0[8]; 85 __IO uint32_t ISR; /**< Interrupt Status, offset: 0x10 */ 86 __IO uint32_t CEOCFR0; /**< Channel End Of Conversion Flag For Precision Inputs, offset: 0x14 */ 87 __IO uint32_t CEOCFR1; /**< Channel End Of Conversion Flag For Standard Inputs, offset: 0x18 */ 88 __IO uint32_t CEOCFR2; /**< Channel End Of Conversion Flag For External Inputs, offset: 0x1C */ 89 __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ 90 __IO uint32_t CIMR0; /**< EOC Interrupt Enable For Precision Inputs, offset: 0x24 */ 91 __IO uint32_t CIMR1; /**< EOC Interrupt Enable For Standard Inputs, offset: 0x28 */ 92 __IO uint32_t CIMR2; /**< EOC Interrupt Enable For External Inputs, offset: 0x2C */ 93 __IO uint32_t WTISR; /**< Analog Watchdog Threshold Interrupt Status, offset: 0x30 */ 94 __IO uint32_t WTIMR; /**< Analog Watchdog Threshold Interrupt Enable, offset: 0x34 */ 95 uint8_t RESERVED_1[8]; 96 __IO uint32_t DMAE; /**< Direct Memory Access Configuration, offset: 0x40 */ 97 __IO uint32_t DMAR0; /**< DMA Request Enable For Precision Inputs, offset: 0x44 */ 98 __IO uint32_t DMAR1; /**< DMA Request Enable For Standard Inputs, offset: 0x48 */ 99 __IO uint32_t DMAR2; /**< DMA Request Enable For External Inputs, offset: 0x4C */ 100 uint8_t RESERVED_2[16]; 101 __IO uint32_t THRHLR[ADC_THRHLR_COUNT]; /**< Analog Watchdog Threshold Values, array offset: 0x60, array step: 0x4 */ 102 uint8_t RESERVED_3[16]; 103 __IO uint32_t PSCR; /**< Presampling Control, offset: 0x80 */ 104 __IO uint32_t PSR0; /**< Presampling Enable For Precision Inputs, offset: 0x84 */ 105 __IO uint32_t PSR1; /**< Presampling Enable For Standard Inputs, offset: 0x88 */ 106 __IO uint32_t PSR2; /**< Presampling Enable For External Inputs, offset: 0x8C */ 107 uint8_t RESERVED_4[4]; 108 __IO uint32_t CTR0; /**< Conversion Timing For Precision Inputs, offset: 0x94 */ 109 __IO uint32_t CTR1; /**< Conversion Timing For Standard Inputs, offset: 0x98 */ 110 __IO uint32_t CTR2; /**< Conversion Timing For External Inputs, offset: 0x9C */ 111 uint8_t RESERVED_5[4]; 112 __IO uint32_t NCMR0; /**< Normal Conversion Enable For Precision Inputs, offset: 0xA4 */ 113 __IO uint32_t NCMR1; /**< Normal Conversion Enable For Standard Inputs, offset: 0xA8 */ 114 __IO uint32_t NCMR2; /**< Normal Conversion Enable For External Inputs, offset: 0xAC */ 115 uint8_t RESERVED_6[4]; 116 __IO uint32_t JCMR0; /**< Injected Conversion Enable For Precision Inputs, offset: 0xB4 */ 117 __IO uint32_t JCMR1; /**< Injected Conversion Enable For Standard Inputs, offset: 0xB8 */ 118 __IO uint32_t JCMR2; /**< Injected Conversion Enable For External Inputs, offset: 0xBC */ 119 uint8_t RESERVED_7[4]; 120 __IO uint32_t DSDR; /**< Delay Start Of Data Conversion, offset: 0xC4 */ 121 __IO uint32_t PDEDR; /**< Power Down Exit Delay, offset: 0xC8 */ 122 uint8_t RESERVED_8[52]; 123 __I uint32_t PCDR[ADC_CDR1_COUNT]; /**< Precision Input n Conversion Data, array offset: 0x100, array step: 0x4 */ 124 uint8_t RESERVED_9[96]; 125 __I uint32_t ICDR[ADC_CDR2_COUNT]; /**< Standard Input n Conversion Data, array offset: 0x180, array step: 0x4 */ 126 uint8_t RESERVED_10[32]; 127 __I uint32_t ECDR[ADC_CDR3_COUNT]; /**< External Input n Conversion Data, array offset: 0x200, array step: 0x4 */ 128 uint8_t RESERVED_11[48]; 129 __IO uint32_t CWSELRPI[ADC_CWSELRPI_COUNT]; /**< Channel Analog Watchdog Select For Precision Inputs, array offset: 0x2B0, array step: 0x4 */ 130 uint8_t RESERVED_12[8]; 131 __IO uint32_t CWSELRSI[ADC_CWSELRSI_COUNT]; /**< Channel Analog Watchdog Select For Standard Inputs, array offset: 0x2C0, array step: 0x4 */ 132 uint8_t RESERVED_13[4]; 133 __IO uint32_t CWSELREI[ADC_CWSELREI_COUNT]; /**< Channel Analog Watchdog Select For External inputs, array offset: 0x2D0, array step: 0x4 */ 134 __IO uint32_t CWENR0; /**< Channel Watchdog Enable For Precision Inputs, offset: 0x2E0 */ 135 __IO uint32_t CWENR1; /**< Channel Watchdog Enable For Standard Inputs, offset: 0x2E4 */ 136 __IO uint32_t CWENR2; /**< Channel Watchdog Enable For External Inputs, offset: 0x2E8 */ 137 uint8_t RESERVED_14[4]; 138 __IO uint32_t AWORR0; /**< Analog Watchdog Out Of Range For Precision Inputs, offset: 0x2F0 */ 139 __IO uint32_t AWORR1; /**< Analog Watchdog Out Of Range For Standard Inputs, offset: 0x2F4 */ 140 __IO uint32_t AWORR2; /**< Analog Watchdog Out Of Range For External Inputs, offset: 0x2F8 */ 141 uint8_t RESERVED_15[68]; 142 __IO uint32_t STCR1; /**< Self-Test Configuration 1, offset: 0x340 */ 143 __IO uint32_t STCR2; /**< Self-Test Configuration 2, offset: 0x344 */ 144 __IO uint32_t STCR3; /**< Self-Test Configuration 3, offset: 0x348 */ 145 __IO uint32_t STBRR; /**< Self-Test Baud Rate, offset: 0x34C */ 146 __IO uint32_t STSR1; /**< Self-Test Status 1, offset: 0x350 */ 147 __I uint32_t STSR2; /**< Self-Test Status 2, offset: 0x354 */ 148 __I uint32_t STSR3; /**< Self-Test Status 3, offset: 0x358 */ 149 __I uint32_t STSR4; /**< Self-Test Status 4, offset: 0x35C */ 150 uint8_t RESERVED_16[16]; 151 __I uint32_t STDR1; /**< Self-Test Conversion Data 1, offset: 0x370 */ 152 uint8_t RESERVED_17[12]; 153 __IO uint32_t STAW0R; /**< Self-Test Analog Watchdog S0, offset: 0x380 */ 154 uint8_t RESERVED_18[4]; 155 __IO uint32_t STAW1R; /**< Self-Test Analog Watchdog S1, offset: 0x388 */ 156 __IO uint32_t STAW2R; /**< Self-Test Analog Watchdog S2, offset: 0x38C */ 157 uint8_t RESERVED_19[4]; 158 __IO uint32_t STAW4R; /**< Self-Test Analog Watchdog C0, offset: 0x394 */ 159 __IO uint32_t STAW5R; /**< Self-Test Analog Watchdog C, offset: 0x398 */ 160 __IO uint32_t AMSIO; /**< Analog Miscellaneous In/Out register, offset: 0x39C */ 161 __IO uint32_t CALBISTREG; /**< Control And Calibration Status, offset: 0x3A0 */ 162 uint8_t RESERVED_20[4]; 163 __IO uint32_t OFSGNUSR; /**< Offset And Gain User, offset: 0x3A8 */ 164 uint8_t RESERVED_21[8]; 165 __IO uint32_t CAL2; /**< Calibration Value 2, offset: 0x3B4 */ 166 } ADC_Type, *ADC_MemMapPtr; 167 168 /** Number of instances of the ADC module. */ 169 #define ADC_INSTANCE_COUNT (3) 170 171 /* ADC - Peripheral instance base addresses */ 172 /** Peripheral ADC_0 base address */ 173 #define IP_ADC_0_BASE (0x400A0000u) 174 /** Peripheral ADC_0 base pointer */ 175 #define IP_ADC_0 ((ADC_Type *)IP_ADC_0_BASE) 176 /** Peripheral ADC_1 base address */ 177 #define IP_ADC_1_BASE (0x400A4000u) 178 /** Peripheral ADC_1 base pointer */ 179 #define IP_ADC_1 ((ADC_Type *)IP_ADC_1_BASE) 180 /** Peripheral ADC_2 base address */ 181 #define IP_ADC_2_BASE (0x400A8000u) 182 /** Peripheral ADC_2 base pointer */ 183 #define IP_ADC_2 ((ADC_Type *)IP_ADC_2_BASE) 184 /** Array initializer of ADC peripheral base addresses */ 185 #define IP_ADC_BASE_ADDRS { IP_ADC_0_BASE, IP_ADC_1_BASE, IP_ADC_2_BASE } 186 /** Array initializer of ADC peripheral base pointers */ 187 #define IP_ADC_BASE_PTRS { IP_ADC_0, IP_ADC_1, IP_ADC_2 } 188 189 /* ---------------------------------------------------------------------------- 190 -- ADC Register Masks 191 ---------------------------------------------------------------------------- */ 192 193 /*! 194 * @addtogroup ADC_Register_Masks ADC Register Masks 195 * @{ 196 */ 197 198 /*! @name MCR - Main Configuration */ 199 /*! @{ */ 200 201 #define ADC_MCR_PWDN_MASK (0x1U) 202 #define ADC_MCR_PWDN_SHIFT (0U) 203 #define ADC_MCR_PWDN_WIDTH (1U) 204 #define ADC_MCR_PWDN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_PWDN_SHIFT)) & ADC_MCR_PWDN_MASK) 205 206 #define ADC_MCR_ADCLKSEL_MASK (0x6U) 207 #define ADC_MCR_ADCLKSEL_SHIFT (1U) 208 #define ADC_MCR_ADCLKSEL_WIDTH (2U) 209 #define ADC_MCR_ADCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSEL_SHIFT)) & ADC_MCR_ADCLKSEL_MASK) 210 211 #define ADC_MCR_ACKO_MASK (0x20U) 212 #define ADC_MCR_ACKO_SHIFT (5U) 213 #define ADC_MCR_ACKO_WIDTH (1U) 214 #define ADC_MCR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ACKO_SHIFT)) & ADC_MCR_ACKO_MASK) 215 216 #define ADC_MCR_ABORT_MASK (0x40U) 217 #define ADC_MCR_ABORT_SHIFT (6U) 218 #define ADC_MCR_ABORT_WIDTH (1U) 219 #define ADC_MCR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORT_SHIFT)) & ADC_MCR_ABORT_MASK) 220 221 #define ADC_MCR_ABORTCHAIN_MASK (0x80U) 222 #define ADC_MCR_ABORTCHAIN_SHIFT (7U) 223 #define ADC_MCR_ABORTCHAIN_WIDTH (1U) 224 #define ADC_MCR_ABORTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORTCHAIN_SHIFT)) & ADC_MCR_ABORTCHAIN_MASK) 225 226 #define ADC_MCR_AVGS_MASK (0x600U) 227 #define ADC_MCR_AVGS_SHIFT (9U) 228 #define ADC_MCR_AVGS_WIDTH (2U) 229 #define ADC_MCR_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGS_SHIFT)) & ADC_MCR_AVGS_MASK) 230 231 #define ADC_MCR_AVGEN_MASK (0x800U) 232 #define ADC_MCR_AVGEN_SHIFT (11U) 233 #define ADC_MCR_AVGEN_WIDTH (1U) 234 #define ADC_MCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGEN_SHIFT)) & ADC_MCR_AVGEN_MASK) 235 236 #define ADC_MCR_STCL_MASK (0x8000U) 237 #define ADC_MCR_STCL_SHIFT (15U) 238 #define ADC_MCR_STCL_WIDTH (1U) 239 #define ADC_MCR_STCL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_STCL_SHIFT)) & ADC_MCR_STCL_MASK) 240 241 #define ADC_MCR_BCTU_MODE_MASK (0x10000U) 242 #define ADC_MCR_BCTU_MODE_SHIFT (16U) 243 #define ADC_MCR_BCTU_MODE_WIDTH (1U) 244 #define ADC_MCR_BCTU_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_BCTU_MODE_SHIFT)) & ADC_MCR_BCTU_MODE_MASK) 245 246 #define ADC_MCR_BCTUEN_MASK (0x20000U) 247 #define ADC_MCR_BCTUEN_SHIFT (17U) 248 #define ADC_MCR_BCTUEN_WIDTH (1U) 249 #define ADC_MCR_BCTUEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_BCTUEN_SHIFT)) & ADC_MCR_BCTUEN_MASK) 250 251 #define ADC_MCR_JSTART_MASK (0x100000U) 252 #define ADC_MCR_JSTART_SHIFT (20U) 253 #define ADC_MCR_JSTART_WIDTH (1U) 254 #define ADC_MCR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JSTART_SHIFT)) & ADC_MCR_JSTART_MASK) 255 256 #define ADC_MCR_JEDGE_MASK (0x200000U) 257 #define ADC_MCR_JEDGE_SHIFT (21U) 258 #define ADC_MCR_JEDGE_WIDTH (1U) 259 #define ADC_MCR_JEDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JEDGE_SHIFT)) & ADC_MCR_JEDGE_MASK) 260 261 #define ADC_MCR_JTRGEN_MASK (0x400000U) 262 #define ADC_MCR_JTRGEN_SHIFT (22U) 263 #define ADC_MCR_JTRGEN_WIDTH (1U) 264 #define ADC_MCR_JTRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JTRGEN_SHIFT)) & ADC_MCR_JTRGEN_MASK) 265 266 #define ADC_MCR_NSTART_MASK (0x1000000U) 267 #define ADC_MCR_NSTART_SHIFT (24U) 268 #define ADC_MCR_NSTART_WIDTH (1U) 269 #define ADC_MCR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NSTART_SHIFT)) & ADC_MCR_NSTART_MASK) 270 271 #define ADC_MCR_XSTRTEN_MASK (0x2000000U) 272 #define ADC_MCR_XSTRTEN_SHIFT (25U) 273 #define ADC_MCR_XSTRTEN_WIDTH (1U) 274 #define ADC_MCR_XSTRTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_XSTRTEN_SHIFT)) & ADC_MCR_XSTRTEN_MASK) 275 276 #define ADC_MCR_EDGE_MASK (0x4000000U) 277 #define ADC_MCR_EDGE_SHIFT (26U) 278 #define ADC_MCR_EDGE_WIDTH (1U) 279 #define ADC_MCR_EDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_EDGE_SHIFT)) & ADC_MCR_EDGE_MASK) 280 281 #define ADC_MCR_TRGEN_MASK (0x8000000U) 282 #define ADC_MCR_TRGEN_SHIFT (27U) 283 #define ADC_MCR_TRGEN_WIDTH (1U) 284 #define ADC_MCR_TRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TRGEN_SHIFT)) & ADC_MCR_TRGEN_MASK) 285 286 #define ADC_MCR_MODE_MASK (0x20000000U) 287 #define ADC_MCR_MODE_SHIFT (29U) 288 #define ADC_MCR_MODE_WIDTH (1U) 289 #define ADC_MCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_MODE_SHIFT)) & ADC_MCR_MODE_MASK) 290 291 #define ADC_MCR_WLSIDE_MASK (0x40000000U) 292 #define ADC_MCR_WLSIDE_SHIFT (30U) 293 #define ADC_MCR_WLSIDE_WIDTH (1U) 294 #define ADC_MCR_WLSIDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_WLSIDE_SHIFT)) & ADC_MCR_WLSIDE_MASK) 295 296 #define ADC_MCR_OWREN_MASK (0x80000000U) 297 #define ADC_MCR_OWREN_SHIFT (31U) 298 #define ADC_MCR_OWREN_WIDTH (1U) 299 #define ADC_MCR_OWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_OWREN_SHIFT)) & ADC_MCR_OWREN_MASK) 300 /*! @} */ 301 302 /*! @name MSR - Main Status */ 303 /*! @{ */ 304 305 #define ADC_MSR_ADCSTATUS_MASK (0x7U) 306 #define ADC_MSR_ADCSTATUS_SHIFT (0U) 307 #define ADC_MSR_ADCSTATUS_WIDTH (3U) 308 #define ADC_MSR_ADCSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK) 309 310 #define ADC_MSR_ACKO_MASK (0x20U) 311 #define ADC_MSR_ACKO_SHIFT (5U) 312 #define ADC_MSR_ACKO_WIDTH (1U) 313 #define ADC_MSR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ACKO_SHIFT)) & ADC_MSR_ACKO_MASK) 314 315 #define ADC_MSR_CHADDR_MASK (0xFE00U) 316 #define ADC_MSR_CHADDR_SHIFT (9U) 317 #define ADC_MSR_CHADDR_WIDTH (7U) 318 #define ADC_MSR_CHADDR(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CHADDR_SHIFT)) & ADC_MSR_CHADDR_MASK) 319 320 #define ADC_MSR_BCTUSTART_MASK (0x10000U) 321 #define ADC_MSR_BCTUSTART_SHIFT (16U) 322 #define ADC_MSR_BCTUSTART_WIDTH (1U) 323 #define ADC_MSR_BCTUSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_BCTUSTART_SHIFT)) & ADC_MSR_BCTUSTART_MASK) 324 325 #define ADC_MSR_SELF_TEST_S_MASK (0x40000U) 326 #define ADC_MSR_SELF_TEST_S_SHIFT (18U) 327 #define ADC_MSR_SELF_TEST_S_WIDTH (1U) 328 #define ADC_MSR_SELF_TEST_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_SELF_TEST_S_SHIFT)) & ADC_MSR_SELF_TEST_S_MASK) 329 330 #define ADC_MSR_JSTART_MASK (0x100000U) 331 #define ADC_MSR_JSTART_SHIFT (20U) 332 #define ADC_MSR_JSTART_WIDTH (1U) 333 #define ADC_MSR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JSTART_SHIFT)) & ADC_MSR_JSTART_MASK) 334 335 #define ADC_MSR_JABORT_MASK (0x800000U) 336 #define ADC_MSR_JABORT_SHIFT (23U) 337 #define ADC_MSR_JABORT_WIDTH (1U) 338 #define ADC_MSR_JABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JABORT_SHIFT)) & ADC_MSR_JABORT_MASK) 339 340 #define ADC_MSR_NSTART_MASK (0x1000000U) 341 #define ADC_MSR_NSTART_SHIFT (24U) 342 #define ADC_MSR_NSTART_WIDTH (1U) 343 #define ADC_MSR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_NSTART_SHIFT)) & ADC_MSR_NSTART_MASK) 344 345 #define ADC_MSR_CALIBRTD_MASK (0x80000000U) 346 #define ADC_MSR_CALIBRTD_SHIFT (31U) 347 #define ADC_MSR_CALIBRTD_WIDTH (1U) 348 #define ADC_MSR_CALIBRTD(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALIBRTD_SHIFT)) & ADC_MSR_CALIBRTD_MASK) 349 /*! @} */ 350 351 /*! @name ISR - Interrupt Status */ 352 /*! @{ */ 353 354 #define ADC_ISR_ECH_MASK (0x1U) 355 #define ADC_ISR_ECH_SHIFT (0U) 356 #define ADC_ISR_ECH_WIDTH (1U) 357 #define ADC_ISR_ECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK) 358 359 #define ADC_ISR_EOC_MASK (0x2U) 360 #define ADC_ISR_EOC_SHIFT (1U) 361 #define ADC_ISR_EOC_WIDTH (1U) 362 #define ADC_ISR_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK) 363 364 #define ADC_ISR_JECH_MASK (0x4U) 365 #define ADC_ISR_JECH_SHIFT (2U) 366 #define ADC_ISR_JECH_WIDTH (1U) 367 #define ADC_ISR_JECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK) 368 369 #define ADC_ISR_JEOC_MASK (0x8U) 370 #define ADC_ISR_JEOC_SHIFT (3U) 371 #define ADC_ISR_JEOC_WIDTH (1U) 372 #define ADC_ISR_JEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK) 373 374 #define ADC_ISR_EOBCTU_MASK (0x10U) 375 #define ADC_ISR_EOBCTU_SHIFT (4U) 376 #define ADC_ISR_EOBCTU_WIDTH (1U) 377 #define ADC_ISR_EOBCTU(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOBCTU_SHIFT)) & ADC_ISR_EOBCTU_MASK) 378 /*! @} */ 379 380 /*! @name CEOCFR0 - Channel End Of Conversion Flag For Precision Inputs */ 381 /*! @{ */ 382 383 #define ADC_CEOCFR0_PIEOCF0_MASK (0x1U) 384 #define ADC_CEOCFR0_PIEOCF0_SHIFT (0U) 385 #define ADC_CEOCFR0_PIEOCF0_WIDTH (1U) 386 #define ADC_CEOCFR0_PIEOCF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF0_SHIFT)) & ADC_CEOCFR0_PIEOCF0_MASK) 387 388 #define ADC_CEOCFR0_PIEOCF1_MASK (0x2U) 389 #define ADC_CEOCFR0_PIEOCF1_SHIFT (1U) 390 #define ADC_CEOCFR0_PIEOCF1_WIDTH (1U) 391 #define ADC_CEOCFR0_PIEOCF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF1_SHIFT)) & ADC_CEOCFR0_PIEOCF1_MASK) 392 393 #define ADC_CEOCFR0_PIEOCF2_MASK (0x4U) 394 #define ADC_CEOCFR0_PIEOCF2_SHIFT (2U) 395 #define ADC_CEOCFR0_PIEOCF2_WIDTH (1U) 396 #define ADC_CEOCFR0_PIEOCF2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF2_SHIFT)) & ADC_CEOCFR0_PIEOCF2_MASK) 397 398 #define ADC_CEOCFR0_PIEOCF3_MASK (0x8U) 399 #define ADC_CEOCFR0_PIEOCF3_SHIFT (3U) 400 #define ADC_CEOCFR0_PIEOCF3_WIDTH (1U) 401 #define ADC_CEOCFR0_PIEOCF3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF3_SHIFT)) & ADC_CEOCFR0_PIEOCF3_MASK) 402 403 #define ADC_CEOCFR0_PIEOCF4_MASK (0x10U) 404 #define ADC_CEOCFR0_PIEOCF4_SHIFT (4U) 405 #define ADC_CEOCFR0_PIEOCF4_WIDTH (1U) 406 #define ADC_CEOCFR0_PIEOCF4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF4_SHIFT)) & ADC_CEOCFR0_PIEOCF4_MASK) 407 408 #define ADC_CEOCFR0_PIEOCF5_MASK (0x20U) 409 #define ADC_CEOCFR0_PIEOCF5_SHIFT (5U) 410 #define ADC_CEOCFR0_PIEOCF5_WIDTH (1U) 411 #define ADC_CEOCFR0_PIEOCF5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF5_SHIFT)) & ADC_CEOCFR0_PIEOCF5_MASK) 412 413 #define ADC_CEOCFR0_PIEOCF6_MASK (0x40U) 414 #define ADC_CEOCFR0_PIEOCF6_SHIFT (6U) 415 #define ADC_CEOCFR0_PIEOCF6_WIDTH (1U) 416 #define ADC_CEOCFR0_PIEOCF6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF6_SHIFT)) & ADC_CEOCFR0_PIEOCF6_MASK) 417 418 #define ADC_CEOCFR0_PIEOCF7_MASK (0x80U) 419 #define ADC_CEOCFR0_PIEOCF7_SHIFT (7U) 420 #define ADC_CEOCFR0_PIEOCF7_WIDTH (1U) 421 #define ADC_CEOCFR0_PIEOCF7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_PIEOCF7_SHIFT)) & ADC_CEOCFR0_PIEOCF7_MASK) 422 /*! @} */ 423 424 /*! @name CEOCFR1 - Channel End Of Conversion Flag For Standard Inputs */ 425 /*! @{ */ 426 427 #define ADC_CEOCFR1_SIEOCF0_MASK (0x1U) 428 #define ADC_CEOCFR1_SIEOCF0_SHIFT (0U) 429 #define ADC_CEOCFR1_SIEOCF0_WIDTH (1U) 430 #define ADC_CEOCFR1_SIEOCF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF0_SHIFT)) & ADC_CEOCFR1_SIEOCF0_MASK) 431 432 #define ADC_CEOCFR1_SIEOCF1_MASK (0x2U) 433 #define ADC_CEOCFR1_SIEOCF1_SHIFT (1U) 434 #define ADC_CEOCFR1_SIEOCF1_WIDTH (1U) 435 #define ADC_CEOCFR1_SIEOCF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF1_SHIFT)) & ADC_CEOCFR1_SIEOCF1_MASK) 436 437 #define ADC_CEOCFR1_SIEOCF2_MASK (0x4U) 438 #define ADC_CEOCFR1_SIEOCF2_SHIFT (2U) 439 #define ADC_CEOCFR1_SIEOCF2_WIDTH (1U) 440 #define ADC_CEOCFR1_SIEOCF2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF2_SHIFT)) & ADC_CEOCFR1_SIEOCF2_MASK) 441 442 #define ADC_CEOCFR1_SIEOCF3_MASK (0x8U) 443 #define ADC_CEOCFR1_SIEOCF3_SHIFT (3U) 444 #define ADC_CEOCFR1_SIEOCF3_WIDTH (1U) 445 #define ADC_CEOCFR1_SIEOCF3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF3_SHIFT)) & ADC_CEOCFR1_SIEOCF3_MASK) 446 447 #define ADC_CEOCFR1_SIEOCF4_MASK (0x10U) 448 #define ADC_CEOCFR1_SIEOCF4_SHIFT (4U) 449 #define ADC_CEOCFR1_SIEOCF4_WIDTH (1U) 450 #define ADC_CEOCFR1_SIEOCF4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF4_SHIFT)) & ADC_CEOCFR1_SIEOCF4_MASK) 451 452 #define ADC_CEOCFR1_SIEOCF5_MASK (0x20U) 453 #define ADC_CEOCFR1_SIEOCF5_SHIFT (5U) 454 #define ADC_CEOCFR1_SIEOCF5_WIDTH (1U) 455 #define ADC_CEOCFR1_SIEOCF5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF5_SHIFT)) & ADC_CEOCFR1_SIEOCF5_MASK) 456 457 #define ADC_CEOCFR1_SIEOCF6_MASK (0x40U) 458 #define ADC_CEOCFR1_SIEOCF6_SHIFT (6U) 459 #define ADC_CEOCFR1_SIEOCF6_WIDTH (1U) 460 #define ADC_CEOCFR1_SIEOCF6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF6_SHIFT)) & ADC_CEOCFR1_SIEOCF6_MASK) 461 462 #define ADC_CEOCFR1_SIEOCF7_MASK (0x80U) 463 #define ADC_CEOCFR1_SIEOCF7_SHIFT (7U) 464 #define ADC_CEOCFR1_SIEOCF7_WIDTH (1U) 465 #define ADC_CEOCFR1_SIEOCF7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF7_SHIFT)) & ADC_CEOCFR1_SIEOCF7_MASK) 466 467 #define ADC_CEOCFR1_SIEOCF8_MASK (0x100U) 468 #define ADC_CEOCFR1_SIEOCF8_SHIFT (8U) 469 #define ADC_CEOCFR1_SIEOCF8_WIDTH (1U) 470 #define ADC_CEOCFR1_SIEOCF8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF8_SHIFT)) & ADC_CEOCFR1_SIEOCF8_MASK) 471 472 #define ADC_CEOCFR1_SIEOCF9_MASK (0x200U) 473 #define ADC_CEOCFR1_SIEOCF9_SHIFT (9U) 474 #define ADC_CEOCFR1_SIEOCF9_WIDTH (1U) 475 #define ADC_CEOCFR1_SIEOCF9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF9_SHIFT)) & ADC_CEOCFR1_SIEOCF9_MASK) 476 477 #define ADC_CEOCFR1_SIEOCF10_MASK (0x400U) 478 #define ADC_CEOCFR1_SIEOCF10_SHIFT (10U) 479 #define ADC_CEOCFR1_SIEOCF10_WIDTH (1U) 480 #define ADC_CEOCFR1_SIEOCF10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF10_SHIFT)) & ADC_CEOCFR1_SIEOCF10_MASK) 481 482 #define ADC_CEOCFR1_SIEOCF11_MASK (0x800U) 483 #define ADC_CEOCFR1_SIEOCF11_SHIFT (11U) 484 #define ADC_CEOCFR1_SIEOCF11_WIDTH (1U) 485 #define ADC_CEOCFR1_SIEOCF11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF11_SHIFT)) & ADC_CEOCFR1_SIEOCF11_MASK) 486 487 #define ADC_CEOCFR1_SIEOCF12_MASK (0x1000U) 488 #define ADC_CEOCFR1_SIEOCF12_SHIFT (12U) 489 #define ADC_CEOCFR1_SIEOCF12_WIDTH (1U) 490 #define ADC_CEOCFR1_SIEOCF12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF12_SHIFT)) & ADC_CEOCFR1_SIEOCF12_MASK) 491 492 #define ADC_CEOCFR1_SIEOCF13_MASK (0x2000U) 493 #define ADC_CEOCFR1_SIEOCF13_SHIFT (13U) 494 #define ADC_CEOCFR1_SIEOCF13_WIDTH (1U) 495 #define ADC_CEOCFR1_SIEOCF13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF13_SHIFT)) & ADC_CEOCFR1_SIEOCF13_MASK) 496 497 #define ADC_CEOCFR1_SIEOCF14_MASK (0x4000U) 498 #define ADC_CEOCFR1_SIEOCF14_SHIFT (14U) 499 #define ADC_CEOCFR1_SIEOCF14_WIDTH (1U) 500 #define ADC_CEOCFR1_SIEOCF14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF14_SHIFT)) & ADC_CEOCFR1_SIEOCF14_MASK) 501 502 #define ADC_CEOCFR1_SIEOCF15_MASK (0x8000U) 503 #define ADC_CEOCFR1_SIEOCF15_SHIFT (15U) 504 #define ADC_CEOCFR1_SIEOCF15_WIDTH (1U) 505 #define ADC_CEOCFR1_SIEOCF15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF15_SHIFT)) & ADC_CEOCFR1_SIEOCF15_MASK) 506 507 #define ADC_CEOCFR1_SIEOCF16_MASK (0x10000U) 508 #define ADC_CEOCFR1_SIEOCF16_SHIFT (16U) 509 #define ADC_CEOCFR1_SIEOCF16_WIDTH (1U) 510 #define ADC_CEOCFR1_SIEOCF16(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF16_SHIFT)) & ADC_CEOCFR1_SIEOCF16_MASK) 511 512 #define ADC_CEOCFR1_SIEOCF17_MASK (0x20000U) 513 #define ADC_CEOCFR1_SIEOCF17_SHIFT (17U) 514 #define ADC_CEOCFR1_SIEOCF17_WIDTH (1U) 515 #define ADC_CEOCFR1_SIEOCF17(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF17_SHIFT)) & ADC_CEOCFR1_SIEOCF17_MASK) 516 517 #define ADC_CEOCFR1_SIEOCF18_MASK (0x40000U) 518 #define ADC_CEOCFR1_SIEOCF18_SHIFT (18U) 519 #define ADC_CEOCFR1_SIEOCF18_WIDTH (1U) 520 #define ADC_CEOCFR1_SIEOCF18(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF18_SHIFT)) & ADC_CEOCFR1_SIEOCF18_MASK) 521 522 #define ADC_CEOCFR1_SIEOCF19_MASK (0x80000U) 523 #define ADC_CEOCFR1_SIEOCF19_SHIFT (19U) 524 #define ADC_CEOCFR1_SIEOCF19_WIDTH (1U) 525 #define ADC_CEOCFR1_SIEOCF19(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF19_SHIFT)) & ADC_CEOCFR1_SIEOCF19_MASK) 526 527 #define ADC_CEOCFR1_SIEOCF20_MASK (0x100000U) 528 #define ADC_CEOCFR1_SIEOCF20_SHIFT (20U) 529 #define ADC_CEOCFR1_SIEOCF20_WIDTH (1U) 530 #define ADC_CEOCFR1_SIEOCF20(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF20_SHIFT)) & ADC_CEOCFR1_SIEOCF20_MASK) 531 532 #define ADC_CEOCFR1_SIEOCF21_MASK (0x200000U) 533 #define ADC_CEOCFR1_SIEOCF21_SHIFT (21U) 534 #define ADC_CEOCFR1_SIEOCF21_WIDTH (1U) 535 #define ADC_CEOCFR1_SIEOCF21(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF21_SHIFT)) & ADC_CEOCFR1_SIEOCF21_MASK) 536 537 #define ADC_CEOCFR1_SIEOCF22_MASK (0x400000U) 538 #define ADC_CEOCFR1_SIEOCF22_SHIFT (22U) 539 #define ADC_CEOCFR1_SIEOCF22_WIDTH (1U) 540 #define ADC_CEOCFR1_SIEOCF22(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF22_SHIFT)) & ADC_CEOCFR1_SIEOCF22_MASK) 541 542 #define ADC_CEOCFR1_SIEOCF23_MASK (0x800000U) 543 #define ADC_CEOCFR1_SIEOCF23_SHIFT (23U) 544 #define ADC_CEOCFR1_SIEOCF23_WIDTH (1U) 545 #define ADC_CEOCFR1_SIEOCF23(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_SIEOCF23_SHIFT)) & ADC_CEOCFR1_SIEOCF23_MASK) 546 /*! @} */ 547 548 /*! @name CEOCFR2 - Channel End Of Conversion Flag For External Inputs */ 549 /*! @{ */ 550 551 #define ADC_CEOCFR2_EIEOCF0_MASK (0x1U) 552 #define ADC_CEOCFR2_EIEOCF0_SHIFT (0U) 553 #define ADC_CEOCFR2_EIEOCF0_WIDTH (1U) 554 #define ADC_CEOCFR2_EIEOCF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF0_SHIFT)) & ADC_CEOCFR2_EIEOCF0_MASK) 555 556 #define ADC_CEOCFR2_EIEOCF1_MASK (0x2U) 557 #define ADC_CEOCFR2_EIEOCF1_SHIFT (1U) 558 #define ADC_CEOCFR2_EIEOCF1_WIDTH (1U) 559 #define ADC_CEOCFR2_EIEOCF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF1_SHIFT)) & ADC_CEOCFR2_EIEOCF1_MASK) 560 561 #define ADC_CEOCFR2_EIEOCF2_MASK (0x4U) 562 #define ADC_CEOCFR2_EIEOCF2_SHIFT (2U) 563 #define ADC_CEOCFR2_EIEOCF2_WIDTH (1U) 564 #define ADC_CEOCFR2_EIEOCF2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF2_SHIFT)) & ADC_CEOCFR2_EIEOCF2_MASK) 565 566 #define ADC_CEOCFR2_EIEOCF3_MASK (0x8U) 567 #define ADC_CEOCFR2_EIEOCF3_SHIFT (3U) 568 #define ADC_CEOCFR2_EIEOCF3_WIDTH (1U) 569 #define ADC_CEOCFR2_EIEOCF3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF3_SHIFT)) & ADC_CEOCFR2_EIEOCF3_MASK) 570 571 #define ADC_CEOCFR2_EIEOCF4_MASK (0x10U) 572 #define ADC_CEOCFR2_EIEOCF4_SHIFT (4U) 573 #define ADC_CEOCFR2_EIEOCF4_WIDTH (1U) 574 #define ADC_CEOCFR2_EIEOCF4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF4_SHIFT)) & ADC_CEOCFR2_EIEOCF4_MASK) 575 576 #define ADC_CEOCFR2_EIEOCF5_MASK (0x20U) 577 #define ADC_CEOCFR2_EIEOCF5_SHIFT (5U) 578 #define ADC_CEOCFR2_EIEOCF5_WIDTH (1U) 579 #define ADC_CEOCFR2_EIEOCF5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF5_SHIFT)) & ADC_CEOCFR2_EIEOCF5_MASK) 580 581 #define ADC_CEOCFR2_EIEOCF6_MASK (0x40U) 582 #define ADC_CEOCFR2_EIEOCF6_SHIFT (6U) 583 #define ADC_CEOCFR2_EIEOCF6_WIDTH (1U) 584 #define ADC_CEOCFR2_EIEOCF6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF6_SHIFT)) & ADC_CEOCFR2_EIEOCF6_MASK) 585 586 #define ADC_CEOCFR2_EIEOCF7_MASK (0x80U) 587 #define ADC_CEOCFR2_EIEOCF7_SHIFT (7U) 588 #define ADC_CEOCFR2_EIEOCF7_WIDTH (1U) 589 #define ADC_CEOCFR2_EIEOCF7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF7_SHIFT)) & ADC_CEOCFR2_EIEOCF7_MASK) 590 591 #define ADC_CEOCFR2_EIEOCF8_MASK (0x100U) 592 #define ADC_CEOCFR2_EIEOCF8_SHIFT (8U) 593 #define ADC_CEOCFR2_EIEOCF8_WIDTH (1U) 594 #define ADC_CEOCFR2_EIEOCF8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF8_SHIFT)) & ADC_CEOCFR2_EIEOCF8_MASK) 595 596 #define ADC_CEOCFR2_EIEOCF9_MASK (0x200U) 597 #define ADC_CEOCFR2_EIEOCF9_SHIFT (9U) 598 #define ADC_CEOCFR2_EIEOCF9_WIDTH (1U) 599 #define ADC_CEOCFR2_EIEOCF9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF9_SHIFT)) & ADC_CEOCFR2_EIEOCF9_MASK) 600 601 #define ADC_CEOCFR2_EIEOCF10_MASK (0x400U) 602 #define ADC_CEOCFR2_EIEOCF10_SHIFT (10U) 603 #define ADC_CEOCFR2_EIEOCF10_WIDTH (1U) 604 #define ADC_CEOCFR2_EIEOCF10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF10_SHIFT)) & ADC_CEOCFR2_EIEOCF10_MASK) 605 606 #define ADC_CEOCFR2_EIEOCF11_MASK (0x800U) 607 #define ADC_CEOCFR2_EIEOCF11_SHIFT (11U) 608 #define ADC_CEOCFR2_EIEOCF11_WIDTH (1U) 609 #define ADC_CEOCFR2_EIEOCF11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF11_SHIFT)) & ADC_CEOCFR2_EIEOCF11_MASK) 610 611 #define ADC_CEOCFR2_EIEOCF12_MASK (0x1000U) 612 #define ADC_CEOCFR2_EIEOCF12_SHIFT (12U) 613 #define ADC_CEOCFR2_EIEOCF12_WIDTH (1U) 614 #define ADC_CEOCFR2_EIEOCF12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF12_SHIFT)) & ADC_CEOCFR2_EIEOCF12_MASK) 615 616 #define ADC_CEOCFR2_EIEOCF13_MASK (0x2000U) 617 #define ADC_CEOCFR2_EIEOCF13_SHIFT (13U) 618 #define ADC_CEOCFR2_EIEOCF13_WIDTH (1U) 619 #define ADC_CEOCFR2_EIEOCF13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF13_SHIFT)) & ADC_CEOCFR2_EIEOCF13_MASK) 620 621 #define ADC_CEOCFR2_EIEOCF14_MASK (0x4000U) 622 #define ADC_CEOCFR2_EIEOCF14_SHIFT (14U) 623 #define ADC_CEOCFR2_EIEOCF14_WIDTH (1U) 624 #define ADC_CEOCFR2_EIEOCF14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF14_SHIFT)) & ADC_CEOCFR2_EIEOCF14_MASK) 625 626 #define ADC_CEOCFR2_EIEOCF15_MASK (0x8000U) 627 #define ADC_CEOCFR2_EIEOCF15_SHIFT (15U) 628 #define ADC_CEOCFR2_EIEOCF15_WIDTH (1U) 629 #define ADC_CEOCFR2_EIEOCF15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF15_SHIFT)) & ADC_CEOCFR2_EIEOCF15_MASK) 630 631 #define ADC_CEOCFR2_EIEOCF16_MASK (0x10000U) 632 #define ADC_CEOCFR2_EIEOCF16_SHIFT (16U) 633 #define ADC_CEOCFR2_EIEOCF16_WIDTH (1U) 634 #define ADC_CEOCFR2_EIEOCF16(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF16_SHIFT)) & ADC_CEOCFR2_EIEOCF16_MASK) 635 636 #define ADC_CEOCFR2_EIEOCF17_MASK (0x20000U) 637 #define ADC_CEOCFR2_EIEOCF17_SHIFT (17U) 638 #define ADC_CEOCFR2_EIEOCF17_WIDTH (1U) 639 #define ADC_CEOCFR2_EIEOCF17(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF17_SHIFT)) & ADC_CEOCFR2_EIEOCF17_MASK) 640 641 #define ADC_CEOCFR2_EIEOCF18_MASK (0x40000U) 642 #define ADC_CEOCFR2_EIEOCF18_SHIFT (18U) 643 #define ADC_CEOCFR2_EIEOCF18_WIDTH (1U) 644 #define ADC_CEOCFR2_EIEOCF18(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF18_SHIFT)) & ADC_CEOCFR2_EIEOCF18_MASK) 645 646 #define ADC_CEOCFR2_EIEOCF19_MASK (0x80000U) 647 #define ADC_CEOCFR2_EIEOCF19_SHIFT (19U) 648 #define ADC_CEOCFR2_EIEOCF19_WIDTH (1U) 649 #define ADC_CEOCFR2_EIEOCF19(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF19_SHIFT)) & ADC_CEOCFR2_EIEOCF19_MASK) 650 651 #define ADC_CEOCFR2_EIEOCF20_MASK (0x100000U) 652 #define ADC_CEOCFR2_EIEOCF20_SHIFT (20U) 653 #define ADC_CEOCFR2_EIEOCF20_WIDTH (1U) 654 #define ADC_CEOCFR2_EIEOCF20(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF20_SHIFT)) & ADC_CEOCFR2_EIEOCF20_MASK) 655 656 #define ADC_CEOCFR2_EIEOCF21_MASK (0x200000U) 657 #define ADC_CEOCFR2_EIEOCF21_SHIFT (21U) 658 #define ADC_CEOCFR2_EIEOCF21_WIDTH (1U) 659 #define ADC_CEOCFR2_EIEOCF21(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF21_SHIFT)) & ADC_CEOCFR2_EIEOCF21_MASK) 660 661 #define ADC_CEOCFR2_EIEOCF22_MASK (0x400000U) 662 #define ADC_CEOCFR2_EIEOCF22_SHIFT (22U) 663 #define ADC_CEOCFR2_EIEOCF22_WIDTH (1U) 664 #define ADC_CEOCFR2_EIEOCF22(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF22_SHIFT)) & ADC_CEOCFR2_EIEOCF22_MASK) 665 666 #define ADC_CEOCFR2_EIEOCF23_MASK (0x800000U) 667 #define ADC_CEOCFR2_EIEOCF23_SHIFT (23U) 668 #define ADC_CEOCFR2_EIEOCF23_WIDTH (1U) 669 #define ADC_CEOCFR2_EIEOCF23(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF23_SHIFT)) & ADC_CEOCFR2_EIEOCF23_MASK) 670 671 #define ADC_CEOCFR2_EIEOCF24_MASK (0x1000000U) 672 #define ADC_CEOCFR2_EIEOCF24_SHIFT (24U) 673 #define ADC_CEOCFR2_EIEOCF24_WIDTH (1U) 674 #define ADC_CEOCFR2_EIEOCF24(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF24_SHIFT)) & ADC_CEOCFR2_EIEOCF24_MASK) 675 676 #define ADC_CEOCFR2_EIEOCF25_MASK (0x2000000U) 677 #define ADC_CEOCFR2_EIEOCF25_SHIFT (25U) 678 #define ADC_CEOCFR2_EIEOCF25_WIDTH (1U) 679 #define ADC_CEOCFR2_EIEOCF25(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF25_SHIFT)) & ADC_CEOCFR2_EIEOCF25_MASK) 680 681 #define ADC_CEOCFR2_EIEOCF26_MASK (0x4000000U) 682 #define ADC_CEOCFR2_EIEOCF26_SHIFT (26U) 683 #define ADC_CEOCFR2_EIEOCF26_WIDTH (1U) 684 #define ADC_CEOCFR2_EIEOCF26(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF26_SHIFT)) & ADC_CEOCFR2_EIEOCF26_MASK) 685 686 #define ADC_CEOCFR2_EIEOCF27_MASK (0x8000000U) 687 #define ADC_CEOCFR2_EIEOCF27_SHIFT (27U) 688 #define ADC_CEOCFR2_EIEOCF27_WIDTH (1U) 689 #define ADC_CEOCFR2_EIEOCF27(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF27_SHIFT)) & ADC_CEOCFR2_EIEOCF27_MASK) 690 691 #define ADC_CEOCFR2_EIEOCF28_MASK (0x10000000U) 692 #define ADC_CEOCFR2_EIEOCF28_SHIFT (28U) 693 #define ADC_CEOCFR2_EIEOCF28_WIDTH (1U) 694 #define ADC_CEOCFR2_EIEOCF28(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF28_SHIFT)) & ADC_CEOCFR2_EIEOCF28_MASK) 695 696 #define ADC_CEOCFR2_EIEOCF29_MASK (0x20000000U) 697 #define ADC_CEOCFR2_EIEOCF29_SHIFT (29U) 698 #define ADC_CEOCFR2_EIEOCF29_WIDTH (1U) 699 #define ADC_CEOCFR2_EIEOCF29(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF29_SHIFT)) & ADC_CEOCFR2_EIEOCF29_MASK) 700 701 #define ADC_CEOCFR2_EIEOCF30_MASK (0x40000000U) 702 #define ADC_CEOCFR2_EIEOCF30_SHIFT (30U) 703 #define ADC_CEOCFR2_EIEOCF30_WIDTH (1U) 704 #define ADC_CEOCFR2_EIEOCF30(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF30_SHIFT)) & ADC_CEOCFR2_EIEOCF30_MASK) 705 706 #define ADC_CEOCFR2_EIEOCF31_MASK (0x80000000U) 707 #define ADC_CEOCFR2_EIEOCF31_SHIFT (31U) 708 #define ADC_CEOCFR2_EIEOCF31_WIDTH (1U) 709 #define ADC_CEOCFR2_EIEOCF31(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR2_EIEOCF31_SHIFT)) & ADC_CEOCFR2_EIEOCF31_MASK) 710 /*! @} */ 711 712 /*! @name IMR - Interrupt Mask */ 713 /*! @{ */ 714 715 #define ADC_IMR_MSKECH_MASK (0x1U) 716 #define ADC_IMR_MSKECH_SHIFT (0U) 717 #define ADC_IMR_MSKECH_WIDTH (1U) 718 #define ADC_IMR_MSKECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKECH_SHIFT)) & ADC_IMR_MSKECH_MASK) 719 720 #define ADC_IMR_MSKEOC_MASK (0x2U) 721 #define ADC_IMR_MSKEOC_SHIFT (1U) 722 #define ADC_IMR_MSKEOC_WIDTH (1U) 723 #define ADC_IMR_MSKEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOC_SHIFT)) & ADC_IMR_MSKEOC_MASK) 724 725 #define ADC_IMR_MSKJECH_MASK (0x4U) 726 #define ADC_IMR_MSKJECH_SHIFT (2U) 727 #define ADC_IMR_MSKJECH_WIDTH (1U) 728 #define ADC_IMR_MSKJECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJECH_SHIFT)) & ADC_IMR_MSKJECH_MASK) 729 730 #define ADC_IMR_MSKJEOC_MASK (0x8U) 731 #define ADC_IMR_MSKJEOC_SHIFT (3U) 732 #define ADC_IMR_MSKJEOC_WIDTH (1U) 733 #define ADC_IMR_MSKJEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJEOC_SHIFT)) & ADC_IMR_MSKJEOC_MASK) 734 735 #define ADC_IMR_MSKEOBCTU_MASK (0x10U) 736 #define ADC_IMR_MSKEOBCTU_SHIFT (4U) 737 #define ADC_IMR_MSKEOBCTU_WIDTH (1U) 738 #define ADC_IMR_MSKEOBCTU(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOBCTU_SHIFT)) & ADC_IMR_MSKEOBCTU_MASK) 739 /*! @} */ 740 741 /*! @name CIMR0 - EOC Interrupt Enable For Precision Inputs */ 742 /*! @{ */ 743 744 #define ADC_CIMR0_PIEOCIEN0_MASK (0x1U) 745 #define ADC_CIMR0_PIEOCIEN0_SHIFT (0U) 746 #define ADC_CIMR0_PIEOCIEN0_WIDTH (1U) 747 #define ADC_CIMR0_PIEOCIEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN0_SHIFT)) & ADC_CIMR0_PIEOCIEN0_MASK) 748 749 #define ADC_CIMR0_PIEOCIEN1_MASK (0x2U) 750 #define ADC_CIMR0_PIEOCIEN1_SHIFT (1U) 751 #define ADC_CIMR0_PIEOCIEN1_WIDTH (1U) 752 #define ADC_CIMR0_PIEOCIEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN1_SHIFT)) & ADC_CIMR0_PIEOCIEN1_MASK) 753 754 #define ADC_CIMR0_PIEOCIEN2_MASK (0x4U) 755 #define ADC_CIMR0_PIEOCIEN2_SHIFT (2U) 756 #define ADC_CIMR0_PIEOCIEN2_WIDTH (1U) 757 #define ADC_CIMR0_PIEOCIEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN2_SHIFT)) & ADC_CIMR0_PIEOCIEN2_MASK) 758 759 #define ADC_CIMR0_PIEOCIEN3_MASK (0x8U) 760 #define ADC_CIMR0_PIEOCIEN3_SHIFT (3U) 761 #define ADC_CIMR0_PIEOCIEN3_WIDTH (1U) 762 #define ADC_CIMR0_PIEOCIEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN3_SHIFT)) & ADC_CIMR0_PIEOCIEN3_MASK) 763 764 #define ADC_CIMR0_PIEOCIEN4_MASK (0x10U) 765 #define ADC_CIMR0_PIEOCIEN4_SHIFT (4U) 766 #define ADC_CIMR0_PIEOCIEN4_WIDTH (1U) 767 #define ADC_CIMR0_PIEOCIEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN4_SHIFT)) & ADC_CIMR0_PIEOCIEN4_MASK) 768 769 #define ADC_CIMR0_PIEOCIEN5_MASK (0x20U) 770 #define ADC_CIMR0_PIEOCIEN5_SHIFT (5U) 771 #define ADC_CIMR0_PIEOCIEN5_WIDTH (1U) 772 #define ADC_CIMR0_PIEOCIEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN5_SHIFT)) & ADC_CIMR0_PIEOCIEN5_MASK) 773 774 #define ADC_CIMR0_PIEOCIEN6_MASK (0x40U) 775 #define ADC_CIMR0_PIEOCIEN6_SHIFT (6U) 776 #define ADC_CIMR0_PIEOCIEN6_WIDTH (1U) 777 #define ADC_CIMR0_PIEOCIEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN6_SHIFT)) & ADC_CIMR0_PIEOCIEN6_MASK) 778 779 #define ADC_CIMR0_PIEOCIEN7_MASK (0x80U) 780 #define ADC_CIMR0_PIEOCIEN7_SHIFT (7U) 781 #define ADC_CIMR0_PIEOCIEN7_WIDTH (1U) 782 #define ADC_CIMR0_PIEOCIEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_PIEOCIEN7_SHIFT)) & ADC_CIMR0_PIEOCIEN7_MASK) 783 /*! @} */ 784 785 /*! @name CIMR1 - EOC Interrupt Enable For Standard Inputs */ 786 /*! @{ */ 787 788 #define ADC_CIMR1_SIEOCIEN0_MASK (0x1U) 789 #define ADC_CIMR1_SIEOCIEN0_SHIFT (0U) 790 #define ADC_CIMR1_SIEOCIEN0_WIDTH (1U) 791 #define ADC_CIMR1_SIEOCIEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN0_SHIFT)) & ADC_CIMR1_SIEOCIEN0_MASK) 792 793 #define ADC_CIMR1_SIEOCIEN1_MASK (0x2U) 794 #define ADC_CIMR1_SIEOCIEN1_SHIFT (1U) 795 #define ADC_CIMR1_SIEOCIEN1_WIDTH (1U) 796 #define ADC_CIMR1_SIEOCIEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN1_SHIFT)) & ADC_CIMR1_SIEOCIEN1_MASK) 797 798 #define ADC_CIMR1_SIEOCIEN2_MASK (0x4U) 799 #define ADC_CIMR1_SIEOCIEN2_SHIFT (2U) 800 #define ADC_CIMR1_SIEOCIEN2_WIDTH (1U) 801 #define ADC_CIMR1_SIEOCIEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN2_SHIFT)) & ADC_CIMR1_SIEOCIEN2_MASK) 802 803 #define ADC_CIMR1_SIEOCIEN3_MASK (0x8U) 804 #define ADC_CIMR1_SIEOCIEN3_SHIFT (3U) 805 #define ADC_CIMR1_SIEOCIEN3_WIDTH (1U) 806 #define ADC_CIMR1_SIEOCIEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN3_SHIFT)) & ADC_CIMR1_SIEOCIEN3_MASK) 807 808 #define ADC_CIMR1_SIEOCIEN4_MASK (0x10U) 809 #define ADC_CIMR1_SIEOCIEN4_SHIFT (4U) 810 #define ADC_CIMR1_SIEOCIEN4_WIDTH (1U) 811 #define ADC_CIMR1_SIEOCIEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN4_SHIFT)) & ADC_CIMR1_SIEOCIEN4_MASK) 812 813 #define ADC_CIMR1_SIEOCIEN5_MASK (0x20U) 814 #define ADC_CIMR1_SIEOCIEN5_SHIFT (5U) 815 #define ADC_CIMR1_SIEOCIEN5_WIDTH (1U) 816 #define ADC_CIMR1_SIEOCIEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN5_SHIFT)) & ADC_CIMR1_SIEOCIEN5_MASK) 817 818 #define ADC_CIMR1_SIEOCIEN6_MASK (0x40U) 819 #define ADC_CIMR1_SIEOCIEN6_SHIFT (6U) 820 #define ADC_CIMR1_SIEOCIEN6_WIDTH (1U) 821 #define ADC_CIMR1_SIEOCIEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN6_SHIFT)) & ADC_CIMR1_SIEOCIEN6_MASK) 822 823 #define ADC_CIMR1_SIEOCIEN7_MASK (0x80U) 824 #define ADC_CIMR1_SIEOCIEN7_SHIFT (7U) 825 #define ADC_CIMR1_SIEOCIEN7_WIDTH (1U) 826 #define ADC_CIMR1_SIEOCIEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN7_SHIFT)) & ADC_CIMR1_SIEOCIEN7_MASK) 827 828 #define ADC_CIMR1_SIEOCIEN8_MASK (0x100U) 829 #define ADC_CIMR1_SIEOCIEN8_SHIFT (8U) 830 #define ADC_CIMR1_SIEOCIEN8_WIDTH (1U) 831 #define ADC_CIMR1_SIEOCIEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN8_SHIFT)) & ADC_CIMR1_SIEOCIEN8_MASK) 832 833 #define ADC_CIMR1_SIEOCIEN9_MASK (0x200U) 834 #define ADC_CIMR1_SIEOCIEN9_SHIFT (9U) 835 #define ADC_CIMR1_SIEOCIEN9_WIDTH (1U) 836 #define ADC_CIMR1_SIEOCIEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN9_SHIFT)) & ADC_CIMR1_SIEOCIEN9_MASK) 837 838 #define ADC_CIMR1_SIEOCIEN10_MASK (0x400U) 839 #define ADC_CIMR1_SIEOCIEN10_SHIFT (10U) 840 #define ADC_CIMR1_SIEOCIEN10_WIDTH (1U) 841 #define ADC_CIMR1_SIEOCIEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN10_SHIFT)) & ADC_CIMR1_SIEOCIEN10_MASK) 842 843 #define ADC_CIMR1_SIEOCIEN11_MASK (0x800U) 844 #define ADC_CIMR1_SIEOCIEN11_SHIFT (11U) 845 #define ADC_CIMR1_SIEOCIEN11_WIDTH (1U) 846 #define ADC_CIMR1_SIEOCIEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN11_SHIFT)) & ADC_CIMR1_SIEOCIEN11_MASK) 847 848 #define ADC_CIMR1_SIEOCIEN12_MASK (0x1000U) 849 #define ADC_CIMR1_SIEOCIEN12_SHIFT (12U) 850 #define ADC_CIMR1_SIEOCIEN12_WIDTH (1U) 851 #define ADC_CIMR1_SIEOCIEN12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN12_SHIFT)) & ADC_CIMR1_SIEOCIEN12_MASK) 852 853 #define ADC_CIMR1_SIEOCIEN13_MASK (0x2000U) 854 #define ADC_CIMR1_SIEOCIEN13_SHIFT (13U) 855 #define ADC_CIMR1_SIEOCIEN13_WIDTH (1U) 856 #define ADC_CIMR1_SIEOCIEN13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN13_SHIFT)) & ADC_CIMR1_SIEOCIEN13_MASK) 857 858 #define ADC_CIMR1_SIEOCIEN14_MASK (0x4000U) 859 #define ADC_CIMR1_SIEOCIEN14_SHIFT (14U) 860 #define ADC_CIMR1_SIEOCIEN14_WIDTH (1U) 861 #define ADC_CIMR1_SIEOCIEN14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN14_SHIFT)) & ADC_CIMR1_SIEOCIEN14_MASK) 862 863 #define ADC_CIMR1_SIEOCIEN15_MASK (0x8000U) 864 #define ADC_CIMR1_SIEOCIEN15_SHIFT (15U) 865 #define ADC_CIMR1_SIEOCIEN15_WIDTH (1U) 866 #define ADC_CIMR1_SIEOCIEN15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN15_SHIFT)) & ADC_CIMR1_SIEOCIEN15_MASK) 867 868 #define ADC_CIMR1_SIEOCIEN16_MASK (0x10000U) 869 #define ADC_CIMR1_SIEOCIEN16_SHIFT (16U) 870 #define ADC_CIMR1_SIEOCIEN16_WIDTH (1U) 871 #define ADC_CIMR1_SIEOCIEN16(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN16_SHIFT)) & ADC_CIMR1_SIEOCIEN16_MASK) 872 873 #define ADC_CIMR1_SIEOCIEN17_MASK (0x20000U) 874 #define ADC_CIMR1_SIEOCIEN17_SHIFT (17U) 875 #define ADC_CIMR1_SIEOCIEN17_WIDTH (1U) 876 #define ADC_CIMR1_SIEOCIEN17(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN17_SHIFT)) & ADC_CIMR1_SIEOCIEN17_MASK) 877 878 #define ADC_CIMR1_SIEOCIEN18_MASK (0x40000U) 879 #define ADC_CIMR1_SIEOCIEN18_SHIFT (18U) 880 #define ADC_CIMR1_SIEOCIEN18_WIDTH (1U) 881 #define ADC_CIMR1_SIEOCIEN18(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN18_SHIFT)) & ADC_CIMR1_SIEOCIEN18_MASK) 882 883 #define ADC_CIMR1_SIEOCIEN19_MASK (0x80000U) 884 #define ADC_CIMR1_SIEOCIEN19_SHIFT (19U) 885 #define ADC_CIMR1_SIEOCIEN19_WIDTH (1U) 886 #define ADC_CIMR1_SIEOCIEN19(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN19_SHIFT)) & ADC_CIMR1_SIEOCIEN19_MASK) 887 888 #define ADC_CIMR1_SIEOCIEN20_MASK (0x100000U) 889 #define ADC_CIMR1_SIEOCIEN20_SHIFT (20U) 890 #define ADC_CIMR1_SIEOCIEN20_WIDTH (1U) 891 #define ADC_CIMR1_SIEOCIEN20(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN20_SHIFT)) & ADC_CIMR1_SIEOCIEN20_MASK) 892 893 #define ADC_CIMR1_SIEOCIEN21_MASK (0x200000U) 894 #define ADC_CIMR1_SIEOCIEN21_SHIFT (21U) 895 #define ADC_CIMR1_SIEOCIEN21_WIDTH (1U) 896 #define ADC_CIMR1_SIEOCIEN21(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN21_SHIFT)) & ADC_CIMR1_SIEOCIEN21_MASK) 897 898 #define ADC_CIMR1_SIEOCIEN22_MASK (0x400000U) 899 #define ADC_CIMR1_SIEOCIEN22_SHIFT (22U) 900 #define ADC_CIMR1_SIEOCIEN22_WIDTH (1U) 901 #define ADC_CIMR1_SIEOCIEN22(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN22_SHIFT)) & ADC_CIMR1_SIEOCIEN22_MASK) 902 903 #define ADC_CIMR1_SIEOCIEN23_MASK (0x800000U) 904 #define ADC_CIMR1_SIEOCIEN23_SHIFT (23U) 905 #define ADC_CIMR1_SIEOCIEN23_WIDTH (1U) 906 #define ADC_CIMR1_SIEOCIEN23(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_SIEOCIEN23_SHIFT)) & ADC_CIMR1_SIEOCIEN23_MASK) 907 /*! @} */ 908 909 /*! @name CIMR2 - EOC Interrupt Enable For External Inputs */ 910 /*! @{ */ 911 912 #define ADC_CIMR2_EIEOCIEN0_MASK (0x1U) 913 #define ADC_CIMR2_EIEOCIEN0_SHIFT (0U) 914 #define ADC_CIMR2_EIEOCIEN0_WIDTH (1U) 915 #define ADC_CIMR2_EIEOCIEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN0_SHIFT)) & ADC_CIMR2_EIEOCIEN0_MASK) 916 917 #define ADC_CIMR2_EIEOCIEN1_MASK (0x2U) 918 #define ADC_CIMR2_EIEOCIEN1_SHIFT (1U) 919 #define ADC_CIMR2_EIEOCIEN1_WIDTH (1U) 920 #define ADC_CIMR2_EIEOCIEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN1_SHIFT)) & ADC_CIMR2_EIEOCIEN1_MASK) 921 922 #define ADC_CIMR2_EIEOCIEN2_MASK (0x4U) 923 #define ADC_CIMR2_EIEOCIEN2_SHIFT (2U) 924 #define ADC_CIMR2_EIEOCIEN2_WIDTH (1U) 925 #define ADC_CIMR2_EIEOCIEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN2_SHIFT)) & ADC_CIMR2_EIEOCIEN2_MASK) 926 927 #define ADC_CIMR2_EIEOCIEN3_MASK (0x8U) 928 #define ADC_CIMR2_EIEOCIEN3_SHIFT (3U) 929 #define ADC_CIMR2_EIEOCIEN3_WIDTH (1U) 930 #define ADC_CIMR2_EIEOCIEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN3_SHIFT)) & ADC_CIMR2_EIEOCIEN3_MASK) 931 932 #define ADC_CIMR2_EIEOCIEN4_MASK (0x10U) 933 #define ADC_CIMR2_EIEOCIEN4_SHIFT (4U) 934 #define ADC_CIMR2_EIEOCIEN4_WIDTH (1U) 935 #define ADC_CIMR2_EIEOCIEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN4_SHIFT)) & ADC_CIMR2_EIEOCIEN4_MASK) 936 937 #define ADC_CIMR2_EIEOCIEN5_MASK (0x20U) 938 #define ADC_CIMR2_EIEOCIEN5_SHIFT (5U) 939 #define ADC_CIMR2_EIEOCIEN5_WIDTH (1U) 940 #define ADC_CIMR2_EIEOCIEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN5_SHIFT)) & ADC_CIMR2_EIEOCIEN5_MASK) 941 942 #define ADC_CIMR2_EIEOCIEN6_MASK (0x40U) 943 #define ADC_CIMR2_EIEOCIEN6_SHIFT (6U) 944 #define ADC_CIMR2_EIEOCIEN6_WIDTH (1U) 945 #define ADC_CIMR2_EIEOCIEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN6_SHIFT)) & ADC_CIMR2_EIEOCIEN6_MASK) 946 947 #define ADC_CIMR2_EIEOCIEN7_MASK (0x80U) 948 #define ADC_CIMR2_EIEOCIEN7_SHIFT (7U) 949 #define ADC_CIMR2_EIEOCIEN7_WIDTH (1U) 950 #define ADC_CIMR2_EIEOCIEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN7_SHIFT)) & ADC_CIMR2_EIEOCIEN7_MASK) 951 952 #define ADC_CIMR2_EIEOCIEN8_MASK (0x100U) 953 #define ADC_CIMR2_EIEOCIEN8_SHIFT (8U) 954 #define ADC_CIMR2_EIEOCIEN8_WIDTH (1U) 955 #define ADC_CIMR2_EIEOCIEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN8_SHIFT)) & ADC_CIMR2_EIEOCIEN8_MASK) 956 957 #define ADC_CIMR2_EIEOCIEN9_MASK (0x200U) 958 #define ADC_CIMR2_EIEOCIEN9_SHIFT (9U) 959 #define ADC_CIMR2_EIEOCIEN9_WIDTH (1U) 960 #define ADC_CIMR2_EIEOCIEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN9_SHIFT)) & ADC_CIMR2_EIEOCIEN9_MASK) 961 962 #define ADC_CIMR2_EIEOCIEN10_MASK (0x400U) 963 #define ADC_CIMR2_EIEOCIEN10_SHIFT (10U) 964 #define ADC_CIMR2_EIEOCIEN10_WIDTH (1U) 965 #define ADC_CIMR2_EIEOCIEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN10_SHIFT)) & ADC_CIMR2_EIEOCIEN10_MASK) 966 967 #define ADC_CIMR2_EIEOCIEN11_MASK (0x800U) 968 #define ADC_CIMR2_EIEOCIEN11_SHIFT (11U) 969 #define ADC_CIMR2_EIEOCIEN11_WIDTH (1U) 970 #define ADC_CIMR2_EIEOCIEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN11_SHIFT)) & ADC_CIMR2_EIEOCIEN11_MASK) 971 972 #define ADC_CIMR2_EIEOCIEN12_MASK (0x1000U) 973 #define ADC_CIMR2_EIEOCIEN12_SHIFT (12U) 974 #define ADC_CIMR2_EIEOCIEN12_WIDTH (1U) 975 #define ADC_CIMR2_EIEOCIEN12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN12_SHIFT)) & ADC_CIMR2_EIEOCIEN12_MASK) 976 977 #define ADC_CIMR2_EIEOCIEN13_MASK (0x2000U) 978 #define ADC_CIMR2_EIEOCIEN13_SHIFT (13U) 979 #define ADC_CIMR2_EIEOCIEN13_WIDTH (1U) 980 #define ADC_CIMR2_EIEOCIEN13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN13_SHIFT)) & ADC_CIMR2_EIEOCIEN13_MASK) 981 982 #define ADC_CIMR2_EIEOCIEN14_MASK (0x4000U) 983 #define ADC_CIMR2_EIEOCIEN14_SHIFT (14U) 984 #define ADC_CIMR2_EIEOCIEN14_WIDTH (1U) 985 #define ADC_CIMR2_EIEOCIEN14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN14_SHIFT)) & ADC_CIMR2_EIEOCIEN14_MASK) 986 987 #define ADC_CIMR2_EIEOCIEN15_MASK (0x8000U) 988 #define ADC_CIMR2_EIEOCIEN15_SHIFT (15U) 989 #define ADC_CIMR2_EIEOCIEN15_WIDTH (1U) 990 #define ADC_CIMR2_EIEOCIEN15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN15_SHIFT)) & ADC_CIMR2_EIEOCIEN15_MASK) 991 992 #define ADC_CIMR2_EIEOCIEN16_MASK (0x10000U) 993 #define ADC_CIMR2_EIEOCIEN16_SHIFT (16U) 994 #define ADC_CIMR2_EIEOCIEN16_WIDTH (1U) 995 #define ADC_CIMR2_EIEOCIEN16(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN16_SHIFT)) & ADC_CIMR2_EIEOCIEN16_MASK) 996 997 #define ADC_CIMR2_EIEOCIEN17_MASK (0x20000U) 998 #define ADC_CIMR2_EIEOCIEN17_SHIFT (17U) 999 #define ADC_CIMR2_EIEOCIEN17_WIDTH (1U) 1000 #define ADC_CIMR2_EIEOCIEN17(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN17_SHIFT)) & ADC_CIMR2_EIEOCIEN17_MASK) 1001 1002 #define ADC_CIMR2_EIEOCIEN18_MASK (0x40000U) 1003 #define ADC_CIMR2_EIEOCIEN18_SHIFT (18U) 1004 #define ADC_CIMR2_EIEOCIEN18_WIDTH (1U) 1005 #define ADC_CIMR2_EIEOCIEN18(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN18_SHIFT)) & ADC_CIMR2_EIEOCIEN18_MASK) 1006 1007 #define ADC_CIMR2_EIEOCIEN19_MASK (0x80000U) 1008 #define ADC_CIMR2_EIEOCIEN19_SHIFT (19U) 1009 #define ADC_CIMR2_EIEOCIEN19_WIDTH (1U) 1010 #define ADC_CIMR2_EIEOCIEN19(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN19_SHIFT)) & ADC_CIMR2_EIEOCIEN19_MASK) 1011 1012 #define ADC_CIMR2_EIEOCIEN20_MASK (0x100000U) 1013 #define ADC_CIMR2_EIEOCIEN20_SHIFT (20U) 1014 #define ADC_CIMR2_EIEOCIEN20_WIDTH (1U) 1015 #define ADC_CIMR2_EIEOCIEN20(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN20_SHIFT)) & ADC_CIMR2_EIEOCIEN20_MASK) 1016 1017 #define ADC_CIMR2_EIEOCIEN21_MASK (0x200000U) 1018 #define ADC_CIMR2_EIEOCIEN21_SHIFT (21U) 1019 #define ADC_CIMR2_EIEOCIEN21_WIDTH (1U) 1020 #define ADC_CIMR2_EIEOCIEN21(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN21_SHIFT)) & ADC_CIMR2_EIEOCIEN21_MASK) 1021 1022 #define ADC_CIMR2_EIEOCIEN22_MASK (0x400000U) 1023 #define ADC_CIMR2_EIEOCIEN22_SHIFT (22U) 1024 #define ADC_CIMR2_EIEOCIEN22_WIDTH (1U) 1025 #define ADC_CIMR2_EIEOCIEN22(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN22_SHIFT)) & ADC_CIMR2_EIEOCIEN22_MASK) 1026 1027 #define ADC_CIMR2_EIEOCIEN23_MASK (0x800000U) 1028 #define ADC_CIMR2_EIEOCIEN23_SHIFT (23U) 1029 #define ADC_CIMR2_EIEOCIEN23_WIDTH (1U) 1030 #define ADC_CIMR2_EIEOCIEN23(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN23_SHIFT)) & ADC_CIMR2_EIEOCIEN23_MASK) 1031 1032 #define ADC_CIMR2_EIEOCIEN24_MASK (0x1000000U) 1033 #define ADC_CIMR2_EIEOCIEN24_SHIFT (24U) 1034 #define ADC_CIMR2_EIEOCIEN24_WIDTH (1U) 1035 #define ADC_CIMR2_EIEOCIEN24(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN24_SHIFT)) & ADC_CIMR2_EIEOCIEN24_MASK) 1036 1037 #define ADC_CIMR2_EIEOCIEN25_MASK (0x2000000U) 1038 #define ADC_CIMR2_EIEOCIEN25_SHIFT (25U) 1039 #define ADC_CIMR2_EIEOCIEN25_WIDTH (1U) 1040 #define ADC_CIMR2_EIEOCIEN25(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN25_SHIFT)) & ADC_CIMR2_EIEOCIEN25_MASK) 1041 1042 #define ADC_CIMR2_EIEOCIEN26_MASK (0x4000000U) 1043 #define ADC_CIMR2_EIEOCIEN26_SHIFT (26U) 1044 #define ADC_CIMR2_EIEOCIEN26_WIDTH (1U) 1045 #define ADC_CIMR2_EIEOCIEN26(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN26_SHIFT)) & ADC_CIMR2_EIEOCIEN26_MASK) 1046 1047 #define ADC_CIMR2_EIEOCIEN27_MASK (0x8000000U) 1048 #define ADC_CIMR2_EIEOCIEN27_SHIFT (27U) 1049 #define ADC_CIMR2_EIEOCIEN27_WIDTH (1U) 1050 #define ADC_CIMR2_EIEOCIEN27(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN27_SHIFT)) & ADC_CIMR2_EIEOCIEN27_MASK) 1051 1052 #define ADC_CIMR2_EIEOCIEN28_MASK (0x10000000U) 1053 #define ADC_CIMR2_EIEOCIEN28_SHIFT (28U) 1054 #define ADC_CIMR2_EIEOCIEN28_WIDTH (1U) 1055 #define ADC_CIMR2_EIEOCIEN28(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN28_SHIFT)) & ADC_CIMR2_EIEOCIEN28_MASK) 1056 1057 #define ADC_CIMR2_EIEOCIEN29_MASK (0x20000000U) 1058 #define ADC_CIMR2_EIEOCIEN29_SHIFT (29U) 1059 #define ADC_CIMR2_EIEOCIEN29_WIDTH (1U) 1060 #define ADC_CIMR2_EIEOCIEN29(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN29_SHIFT)) & ADC_CIMR2_EIEOCIEN29_MASK) 1061 1062 #define ADC_CIMR2_EIEOCIEN30_MASK (0x40000000U) 1063 #define ADC_CIMR2_EIEOCIEN30_SHIFT (30U) 1064 #define ADC_CIMR2_EIEOCIEN30_WIDTH (1U) 1065 #define ADC_CIMR2_EIEOCIEN30(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN30_SHIFT)) & ADC_CIMR2_EIEOCIEN30_MASK) 1066 1067 #define ADC_CIMR2_EIEOCIEN31_MASK (0x80000000U) 1068 #define ADC_CIMR2_EIEOCIEN31_SHIFT (31U) 1069 #define ADC_CIMR2_EIEOCIEN31_WIDTH (1U) 1070 #define ADC_CIMR2_EIEOCIEN31(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR2_EIEOCIEN31_SHIFT)) & ADC_CIMR2_EIEOCIEN31_MASK) 1071 /*! @} */ 1072 1073 /*! @name WTISR - Analog Watchdog Threshold Interrupt Status */ 1074 /*! @{ */ 1075 1076 #define ADC_WTISR_LAWIF1_MASK (0x1U) 1077 #define ADC_WTISR_LAWIF1_SHIFT (0U) 1078 #define ADC_WTISR_LAWIF1_WIDTH (1U) 1079 #define ADC_WTISR_LAWIF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF1_SHIFT)) & ADC_WTISR_LAWIF1_MASK) 1080 1081 #define ADC_WTISR_HAWIF1_MASK (0x2U) 1082 #define ADC_WTISR_HAWIF1_SHIFT (1U) 1083 #define ADC_WTISR_HAWIF1_WIDTH (1U) 1084 #define ADC_WTISR_HAWIF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF1_SHIFT)) & ADC_WTISR_HAWIF1_MASK) 1085 1086 #define ADC_WTISR_LAWIF2_MASK (0x4U) 1087 #define ADC_WTISR_LAWIF2_SHIFT (2U) 1088 #define ADC_WTISR_LAWIF2_WIDTH (1U) 1089 #define ADC_WTISR_LAWIF2(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF2_SHIFT)) & ADC_WTISR_LAWIF2_MASK) 1090 1091 #define ADC_WTISR_HAWIF2_MASK (0x8U) 1092 #define ADC_WTISR_HAWIF2_SHIFT (3U) 1093 #define ADC_WTISR_HAWIF2_WIDTH (1U) 1094 #define ADC_WTISR_HAWIF2(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF2_SHIFT)) & ADC_WTISR_HAWIF2_MASK) 1095 1096 #define ADC_WTISR_LAWIF3_MASK (0x10U) 1097 #define ADC_WTISR_LAWIF3_SHIFT (4U) 1098 #define ADC_WTISR_LAWIF3_WIDTH (1U) 1099 #define ADC_WTISR_LAWIF3(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF3_SHIFT)) & ADC_WTISR_LAWIF3_MASK) 1100 1101 #define ADC_WTISR_HAWIF3_MASK (0x20U) 1102 #define ADC_WTISR_HAWIF3_SHIFT (5U) 1103 #define ADC_WTISR_HAWIF3_WIDTH (1U) 1104 #define ADC_WTISR_HAWIF3(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF3_SHIFT)) & ADC_WTISR_HAWIF3_MASK) 1105 1106 #define ADC_WTISR_LAWIF4_MASK (0x40U) 1107 #define ADC_WTISR_LAWIF4_SHIFT (6U) 1108 #define ADC_WTISR_LAWIF4_WIDTH (1U) 1109 #define ADC_WTISR_LAWIF4(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF4_SHIFT)) & ADC_WTISR_LAWIF4_MASK) 1110 1111 #define ADC_WTISR_HAWIF4_MASK (0x80U) 1112 #define ADC_WTISR_HAWIF4_SHIFT (7U) 1113 #define ADC_WTISR_HAWIF4_WIDTH (1U) 1114 #define ADC_WTISR_HAWIF4(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF4_SHIFT)) & ADC_WTISR_HAWIF4_MASK) 1115 1116 #define ADC_WTISR_LAWIF5_MASK (0x100U) 1117 #define ADC_WTISR_LAWIF5_SHIFT (8U) 1118 #define ADC_WTISR_LAWIF5_WIDTH (1U) 1119 #define ADC_WTISR_LAWIF5(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF5_SHIFT)) & ADC_WTISR_LAWIF5_MASK) 1120 1121 #define ADC_WTISR_HAWIF5_MASK (0x200U) 1122 #define ADC_WTISR_HAWIF5_SHIFT (9U) 1123 #define ADC_WTISR_HAWIF5_WIDTH (1U) 1124 #define ADC_WTISR_HAWIF5(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF5_SHIFT)) & ADC_WTISR_HAWIF5_MASK) 1125 1126 #define ADC_WTISR_LAWIF6_MASK (0x400U) 1127 #define ADC_WTISR_LAWIF6_SHIFT (10U) 1128 #define ADC_WTISR_LAWIF6_WIDTH (1U) 1129 #define ADC_WTISR_LAWIF6(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF6_SHIFT)) & ADC_WTISR_LAWIF6_MASK) 1130 1131 #define ADC_WTISR_HAWIF6_MASK (0x800U) 1132 #define ADC_WTISR_HAWIF6_SHIFT (11U) 1133 #define ADC_WTISR_HAWIF6_WIDTH (1U) 1134 #define ADC_WTISR_HAWIF6(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF6_SHIFT)) & ADC_WTISR_HAWIF6_MASK) 1135 1136 #define ADC_WTISR_LAWIF7_MASK (0x1000U) 1137 #define ADC_WTISR_LAWIF7_SHIFT (12U) 1138 #define ADC_WTISR_LAWIF7_WIDTH (1U) 1139 #define ADC_WTISR_LAWIF7(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF7_SHIFT)) & ADC_WTISR_LAWIF7_MASK) 1140 1141 #define ADC_WTISR_HAWIF7_MASK (0x2000U) 1142 #define ADC_WTISR_HAWIF7_SHIFT (13U) 1143 #define ADC_WTISR_HAWIF7_WIDTH (1U) 1144 #define ADC_WTISR_HAWIF7(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF7_SHIFT)) & ADC_WTISR_HAWIF7_MASK) 1145 1146 #define ADC_WTISR_LAWIF8_MASK (0x4000U) 1147 #define ADC_WTISR_LAWIF8_SHIFT (14U) 1148 #define ADC_WTISR_LAWIF8_WIDTH (1U) 1149 #define ADC_WTISR_LAWIF8(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF8_SHIFT)) & ADC_WTISR_LAWIF8_MASK) 1150 1151 #define ADC_WTISR_HAWIF8_MASK (0x8000U) 1152 #define ADC_WTISR_HAWIF8_SHIFT (15U) 1153 #define ADC_WTISR_HAWIF8_WIDTH (1U) 1154 #define ADC_WTISR_HAWIF8(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF8_SHIFT)) & ADC_WTISR_HAWIF8_MASK) 1155 1156 #define ADC_WTISR_LAWIF9_MASK (0x10000U) 1157 #define ADC_WTISR_LAWIF9_SHIFT (16U) 1158 #define ADC_WTISR_LAWIF9_WIDTH (1U) 1159 #define ADC_WTISR_LAWIF9(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF9_SHIFT)) & ADC_WTISR_LAWIF9_MASK) 1160 1161 #define ADC_WTISR_HAWIF9_MASK (0x20000U) 1162 #define ADC_WTISR_HAWIF9_SHIFT (17U) 1163 #define ADC_WTISR_HAWIF9_WIDTH (1U) 1164 #define ADC_WTISR_HAWIF9(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF9_SHIFT)) & ADC_WTISR_HAWIF9_MASK) 1165 1166 #define ADC_WTISR_LAWIF10_MASK (0x40000U) 1167 #define ADC_WTISR_LAWIF10_SHIFT (18U) 1168 #define ADC_WTISR_LAWIF10_WIDTH (1U) 1169 #define ADC_WTISR_LAWIF10(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF10_SHIFT)) & ADC_WTISR_LAWIF10_MASK) 1170 1171 #define ADC_WTISR_HAWIF10_MASK (0x80000U) 1172 #define ADC_WTISR_HAWIF10_SHIFT (19U) 1173 #define ADC_WTISR_HAWIF10_WIDTH (1U) 1174 #define ADC_WTISR_HAWIF10(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF10_SHIFT)) & ADC_WTISR_HAWIF10_MASK) 1175 1176 #define ADC_WTISR_LAWIF11_MASK (0x100000U) 1177 #define ADC_WTISR_LAWIF11_SHIFT (20U) 1178 #define ADC_WTISR_LAWIF11_WIDTH (1U) 1179 #define ADC_WTISR_LAWIF11(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF11_SHIFT)) & ADC_WTISR_LAWIF11_MASK) 1180 1181 #define ADC_WTISR_HAWIF11_MASK (0x200000U) 1182 #define ADC_WTISR_HAWIF11_SHIFT (21U) 1183 #define ADC_WTISR_HAWIF11_WIDTH (1U) 1184 #define ADC_WTISR_HAWIF11(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF11_SHIFT)) & ADC_WTISR_HAWIF11_MASK) 1185 1186 #define ADC_WTISR_LAWIF12_MASK (0x400000U) 1187 #define ADC_WTISR_LAWIF12_SHIFT (22U) 1188 #define ADC_WTISR_LAWIF12_WIDTH (1U) 1189 #define ADC_WTISR_LAWIF12(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF12_SHIFT)) & ADC_WTISR_LAWIF12_MASK) 1190 1191 #define ADC_WTISR_HAWIF12_MASK (0x800000U) 1192 #define ADC_WTISR_HAWIF12_SHIFT (23U) 1193 #define ADC_WTISR_HAWIF12_WIDTH (1U) 1194 #define ADC_WTISR_HAWIF12(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF12_SHIFT)) & ADC_WTISR_HAWIF12_MASK) 1195 1196 #define ADC_WTISR_LAWIF13_MASK (0x1000000U) 1197 #define ADC_WTISR_LAWIF13_SHIFT (24U) 1198 #define ADC_WTISR_LAWIF13_WIDTH (1U) 1199 #define ADC_WTISR_LAWIF13(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF13_SHIFT)) & ADC_WTISR_LAWIF13_MASK) 1200 1201 #define ADC_WTISR_HAWIF13_MASK (0x2000000U) 1202 #define ADC_WTISR_HAWIF13_SHIFT (25U) 1203 #define ADC_WTISR_HAWIF13_WIDTH (1U) 1204 #define ADC_WTISR_HAWIF13(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF13_SHIFT)) & ADC_WTISR_HAWIF13_MASK) 1205 1206 #define ADC_WTISR_LAWIF14_MASK (0x4000000U) 1207 #define ADC_WTISR_LAWIF14_SHIFT (26U) 1208 #define ADC_WTISR_LAWIF14_WIDTH (1U) 1209 #define ADC_WTISR_LAWIF14(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF14_SHIFT)) & ADC_WTISR_LAWIF14_MASK) 1210 1211 #define ADC_WTISR_HAWIF14_MASK (0x8000000U) 1212 #define ADC_WTISR_HAWIF14_SHIFT (27U) 1213 #define ADC_WTISR_HAWIF14_WIDTH (1U) 1214 #define ADC_WTISR_HAWIF14(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF14_SHIFT)) & ADC_WTISR_HAWIF14_MASK) 1215 1216 #define ADC_WTISR_LAWIF15_MASK (0x10000000U) 1217 #define ADC_WTISR_LAWIF15_SHIFT (28U) 1218 #define ADC_WTISR_LAWIF15_WIDTH (1U) 1219 #define ADC_WTISR_LAWIF15(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF15_SHIFT)) & ADC_WTISR_LAWIF15_MASK) 1220 1221 #define ADC_WTISR_HAWIF15_MASK (0x20000000U) 1222 #define ADC_WTISR_HAWIF15_SHIFT (29U) 1223 #define ADC_WTISR_HAWIF15_WIDTH (1U) 1224 #define ADC_WTISR_HAWIF15(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF15_SHIFT)) & ADC_WTISR_HAWIF15_MASK) 1225 1226 #define ADC_WTISR_LAWIF16_MASK (0x40000000U) 1227 #define ADC_WTISR_LAWIF16_SHIFT (30U) 1228 #define ADC_WTISR_LAWIF16_WIDTH (1U) 1229 #define ADC_WTISR_LAWIF16(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_LAWIF16_SHIFT)) & ADC_WTISR_LAWIF16_MASK) 1230 1231 #define ADC_WTISR_HAWIF16_MASK (0x80000000U) 1232 #define ADC_WTISR_HAWIF16_SHIFT (31U) 1233 #define ADC_WTISR_HAWIF16_WIDTH (1U) 1234 #define ADC_WTISR_HAWIF16(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_HAWIF16_SHIFT)) & ADC_WTISR_HAWIF16_MASK) 1235 /*! @} */ 1236 1237 /*! @name WTIMR - Analog Watchdog Threshold Interrupt Enable */ 1238 /*! @{ */ 1239 1240 #define ADC_WTIMR_LAWIFEN1_MASK (0x1U) 1241 #define ADC_WTIMR_LAWIFEN1_SHIFT (0U) 1242 #define ADC_WTIMR_LAWIFEN1_WIDTH (1U) 1243 #define ADC_WTIMR_LAWIFEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_LAWIFEN1_SHIFT)) & ADC_WTIMR_LAWIFEN1_MASK) 1244 1245 #define ADC_WTIMR_HDWIFEN1_MASK (0x2U) 1246 #define ADC_WTIMR_HDWIFEN1_SHIFT (1U) 1247 #define ADC_WTIMR_HDWIFEN1_WIDTH (1U) 1248 #define ADC_WTIMR_HDWIFEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_HDWIFEN1_SHIFT)) & ADC_WTIMR_HDWIFEN1_MASK) 1249 1250 #define ADC_WTIMR_LAWIFEN2_MASK (0x4U) 1251 #define ADC_WTIMR_LAWIFEN2_SHIFT (2U) 1252 #define ADC_WTIMR_LAWIFEN2_WIDTH (1U) 1253 #define ADC_WTIMR_LAWIFEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_LAWIFEN2_SHIFT)) & ADC_WTIMR_LAWIFEN2_MASK) 1254 1255 #define ADC_WTIMR_HDWIFEN2_MASK (0x8U) 1256 #define ADC_WTIMR_HDWIFEN2_SHIFT (3U) 1257 #define ADC_WTIMR_HDWIFEN2_WIDTH (1U) 1258 #define ADC_WTIMR_HDWIFEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_HDWIFEN2_SHIFT)) & ADC_WTIMR_HDWIFEN2_MASK) 1259 1260 #define ADC_WTIMR_LAWIFEN3_MASK (0x10U) 1261 #define ADC_WTIMR_LAWIFEN3_SHIFT (4U) 1262 #define ADC_WTIMR_LAWIFEN3_WIDTH (1U) 1263 #define ADC_WTIMR_LAWIFEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_LAWIFEN3_SHIFT)) & ADC_WTIMR_LAWIFEN3_MASK) 1264 1265 #define ADC_WTIMR_HDWIFEN3_MASK (0x20U) 1266 #define ADC_WTIMR_HDWIFEN3_SHIFT (5U) 1267 #define ADC_WTIMR_HDWIFEN3_WIDTH (1U) 1268 #define ADC_WTIMR_HDWIFEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_HDWIFEN3_SHIFT)) & ADC_WTIMR_HDWIFEN3_MASK) 1269 1270 #define ADC_WTIMR_LAWIFEN4_MASK (0x40U) 1271 #define ADC_WTIMR_LAWIFEN4_SHIFT (6U) 1272 #define ADC_WTIMR_LAWIFEN4_WIDTH (1U) 1273 #define ADC_WTIMR_LAWIFEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_LAWIFEN4_SHIFT)) & ADC_WTIMR_LAWIFEN4_MASK) 1274 1275 #define ADC_WTIMR_HDWIFEN4_MASK (0x80U) 1276 #define ADC_WTIMR_HDWIFEN4_SHIFT (7U) 1277 #define ADC_WTIMR_HDWIFEN4_WIDTH (1U) 1278 #define ADC_WTIMR_HDWIFEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_HDWIFEN4_SHIFT)) & ADC_WTIMR_HDWIFEN4_MASK) 1279 /*! @} */ 1280 1281 /*! @name DMAE - Direct Memory Access Configuration */ 1282 /*! @{ */ 1283 1284 #define ADC_DMAE_DMAEN_MASK (0x1U) 1285 #define ADC_DMAE_DMAEN_SHIFT (0U) 1286 #define ADC_DMAE_DMAEN_WIDTH (1U) 1287 #define ADC_DMAE_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DMAEN_SHIFT)) & ADC_DMAE_DMAEN_MASK) 1288 1289 #define ADC_DMAE_DCLR_MASK (0x2U) 1290 #define ADC_DMAE_DCLR_SHIFT (1U) 1291 #define ADC_DMAE_DCLR_WIDTH (1U) 1292 #define ADC_DMAE_DCLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DCLR_SHIFT)) & ADC_DMAE_DCLR_MASK) 1293 /*! @} */ 1294 1295 /*! @name DMAR0 - DMA Request Enable For Precision Inputs */ 1296 /*! @{ */ 1297 1298 #define ADC_DMAR0_PIDMAREN0_MASK (0x1U) 1299 #define ADC_DMAR0_PIDMAREN0_SHIFT (0U) 1300 #define ADC_DMAR0_PIDMAREN0_WIDTH (1U) 1301 #define ADC_DMAR0_PIDMAREN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN0_SHIFT)) & ADC_DMAR0_PIDMAREN0_MASK) 1302 1303 #define ADC_DMAR0_PIDMAREN1_MASK (0x2U) 1304 #define ADC_DMAR0_PIDMAREN1_SHIFT (1U) 1305 #define ADC_DMAR0_PIDMAREN1_WIDTH (1U) 1306 #define ADC_DMAR0_PIDMAREN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN1_SHIFT)) & ADC_DMAR0_PIDMAREN1_MASK) 1307 1308 #define ADC_DMAR0_PIDMAREN2_MASK (0x4U) 1309 #define ADC_DMAR0_PIDMAREN2_SHIFT (2U) 1310 #define ADC_DMAR0_PIDMAREN2_WIDTH (1U) 1311 #define ADC_DMAR0_PIDMAREN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN2_SHIFT)) & ADC_DMAR0_PIDMAREN2_MASK) 1312 1313 #define ADC_DMAR0_PIDMAREN3_MASK (0x8U) 1314 #define ADC_DMAR0_PIDMAREN3_SHIFT (3U) 1315 #define ADC_DMAR0_PIDMAREN3_WIDTH (1U) 1316 #define ADC_DMAR0_PIDMAREN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN3_SHIFT)) & ADC_DMAR0_PIDMAREN3_MASK) 1317 1318 #define ADC_DMAR0_PIDMAREN4_MASK (0x10U) 1319 #define ADC_DMAR0_PIDMAREN4_SHIFT (4U) 1320 #define ADC_DMAR0_PIDMAREN4_WIDTH (1U) 1321 #define ADC_DMAR0_PIDMAREN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN4_SHIFT)) & ADC_DMAR0_PIDMAREN4_MASK) 1322 1323 #define ADC_DMAR0_PIDMAREN5_MASK (0x20U) 1324 #define ADC_DMAR0_PIDMAREN5_SHIFT (5U) 1325 #define ADC_DMAR0_PIDMAREN5_WIDTH (1U) 1326 #define ADC_DMAR0_PIDMAREN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN5_SHIFT)) & ADC_DMAR0_PIDMAREN5_MASK) 1327 1328 #define ADC_DMAR0_PIDMAREN6_MASK (0x40U) 1329 #define ADC_DMAR0_PIDMAREN6_SHIFT (6U) 1330 #define ADC_DMAR0_PIDMAREN6_WIDTH (1U) 1331 #define ADC_DMAR0_PIDMAREN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN6_SHIFT)) & ADC_DMAR0_PIDMAREN6_MASK) 1332 1333 #define ADC_DMAR0_PIDMAREN7_MASK (0x80U) 1334 #define ADC_DMAR0_PIDMAREN7_SHIFT (7U) 1335 #define ADC_DMAR0_PIDMAREN7_WIDTH (1U) 1336 #define ADC_DMAR0_PIDMAREN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_PIDMAREN7_SHIFT)) & ADC_DMAR0_PIDMAREN7_MASK) 1337 /*! @} */ 1338 1339 /*! @name DMAR1 - DMA Request Enable For Standard Inputs */ 1340 /*! @{ */ 1341 1342 #define ADC_DMAR1_SIDMAREN0_MASK (0x1U) 1343 #define ADC_DMAR1_SIDMAREN0_SHIFT (0U) 1344 #define ADC_DMAR1_SIDMAREN0_WIDTH (1U) 1345 #define ADC_DMAR1_SIDMAREN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN0_SHIFT)) & ADC_DMAR1_SIDMAREN0_MASK) 1346 1347 #define ADC_DMAR1_SIDMAREN1_MASK (0x2U) 1348 #define ADC_DMAR1_SIDMAREN1_SHIFT (1U) 1349 #define ADC_DMAR1_SIDMAREN1_WIDTH (1U) 1350 #define ADC_DMAR1_SIDMAREN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN1_SHIFT)) & ADC_DMAR1_SIDMAREN1_MASK) 1351 1352 #define ADC_DMAR1_SIDMAREN2_MASK (0x4U) 1353 #define ADC_DMAR1_SIDMAREN2_SHIFT (2U) 1354 #define ADC_DMAR1_SIDMAREN2_WIDTH (1U) 1355 #define ADC_DMAR1_SIDMAREN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN2_SHIFT)) & ADC_DMAR1_SIDMAREN2_MASK) 1356 1357 #define ADC_DMAR1_SIDMAREN3_MASK (0x8U) 1358 #define ADC_DMAR1_SIDMAREN3_SHIFT (3U) 1359 #define ADC_DMAR1_SIDMAREN3_WIDTH (1U) 1360 #define ADC_DMAR1_SIDMAREN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN3_SHIFT)) & ADC_DMAR1_SIDMAREN3_MASK) 1361 1362 #define ADC_DMAR1_SIDMAREN4_MASK (0x10U) 1363 #define ADC_DMAR1_SIDMAREN4_SHIFT (4U) 1364 #define ADC_DMAR1_SIDMAREN4_WIDTH (1U) 1365 #define ADC_DMAR1_SIDMAREN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN4_SHIFT)) & ADC_DMAR1_SIDMAREN4_MASK) 1366 1367 #define ADC_DMAR1_SIDMAREN5_MASK (0x20U) 1368 #define ADC_DMAR1_SIDMAREN5_SHIFT (5U) 1369 #define ADC_DMAR1_SIDMAREN5_WIDTH (1U) 1370 #define ADC_DMAR1_SIDMAREN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN5_SHIFT)) & ADC_DMAR1_SIDMAREN5_MASK) 1371 1372 #define ADC_DMAR1_SIDMAREN6_MASK (0x40U) 1373 #define ADC_DMAR1_SIDMAREN6_SHIFT (6U) 1374 #define ADC_DMAR1_SIDMAREN6_WIDTH (1U) 1375 #define ADC_DMAR1_SIDMAREN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN6_SHIFT)) & ADC_DMAR1_SIDMAREN6_MASK) 1376 1377 #define ADC_DMAR1_SIDMAREN7_MASK (0x80U) 1378 #define ADC_DMAR1_SIDMAREN7_SHIFT (7U) 1379 #define ADC_DMAR1_SIDMAREN7_WIDTH (1U) 1380 #define ADC_DMAR1_SIDMAREN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN7_SHIFT)) & ADC_DMAR1_SIDMAREN7_MASK) 1381 1382 #define ADC_DMAR1_SIDMAREN8_MASK (0x100U) 1383 #define ADC_DMAR1_SIDMAREN8_SHIFT (8U) 1384 #define ADC_DMAR1_SIDMAREN8_WIDTH (1U) 1385 #define ADC_DMAR1_SIDMAREN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN8_SHIFT)) & ADC_DMAR1_SIDMAREN8_MASK) 1386 1387 #define ADC_DMAR1_SIDMAREN9_MASK (0x200U) 1388 #define ADC_DMAR1_SIDMAREN9_SHIFT (9U) 1389 #define ADC_DMAR1_SIDMAREN9_WIDTH (1U) 1390 #define ADC_DMAR1_SIDMAREN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN9_SHIFT)) & ADC_DMAR1_SIDMAREN9_MASK) 1391 1392 #define ADC_DMAR1_SIDMAREN10_MASK (0x400U) 1393 #define ADC_DMAR1_SIDMAREN10_SHIFT (10U) 1394 #define ADC_DMAR1_SIDMAREN10_WIDTH (1U) 1395 #define ADC_DMAR1_SIDMAREN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN10_SHIFT)) & ADC_DMAR1_SIDMAREN10_MASK) 1396 1397 #define ADC_DMAR1_SIDMAREN11_MASK (0x800U) 1398 #define ADC_DMAR1_SIDMAREN11_SHIFT (11U) 1399 #define ADC_DMAR1_SIDMAREN11_WIDTH (1U) 1400 #define ADC_DMAR1_SIDMAREN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN11_SHIFT)) & ADC_DMAR1_SIDMAREN11_MASK) 1401 1402 #define ADC_DMAR1_SIDMAREN12_MASK (0x1000U) 1403 #define ADC_DMAR1_SIDMAREN12_SHIFT (12U) 1404 #define ADC_DMAR1_SIDMAREN12_WIDTH (1U) 1405 #define ADC_DMAR1_SIDMAREN12(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN12_SHIFT)) & ADC_DMAR1_SIDMAREN12_MASK) 1406 1407 #define ADC_DMAR1_SIDMAREN13_MASK (0x2000U) 1408 #define ADC_DMAR1_SIDMAREN13_SHIFT (13U) 1409 #define ADC_DMAR1_SIDMAREN13_WIDTH (1U) 1410 #define ADC_DMAR1_SIDMAREN13(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN13_SHIFT)) & ADC_DMAR1_SIDMAREN13_MASK) 1411 1412 #define ADC_DMAR1_SIDMAREN14_MASK (0x4000U) 1413 #define ADC_DMAR1_SIDMAREN14_SHIFT (14U) 1414 #define ADC_DMAR1_SIDMAREN14_WIDTH (1U) 1415 #define ADC_DMAR1_SIDMAREN14(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN14_SHIFT)) & ADC_DMAR1_SIDMAREN14_MASK) 1416 1417 #define ADC_DMAR1_SIDMAREN15_MASK (0x8000U) 1418 #define ADC_DMAR1_SIDMAREN15_SHIFT (15U) 1419 #define ADC_DMAR1_SIDMAREN15_WIDTH (1U) 1420 #define ADC_DMAR1_SIDMAREN15(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN15_SHIFT)) & ADC_DMAR1_SIDMAREN15_MASK) 1421 1422 #define ADC_DMAR1_SIDMAREN16_MASK (0x10000U) 1423 #define ADC_DMAR1_SIDMAREN16_SHIFT (16U) 1424 #define ADC_DMAR1_SIDMAREN16_WIDTH (1U) 1425 #define ADC_DMAR1_SIDMAREN16(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN16_SHIFT)) & ADC_DMAR1_SIDMAREN16_MASK) 1426 1427 #define ADC_DMAR1_SIDMAREN17_MASK (0x20000U) 1428 #define ADC_DMAR1_SIDMAREN17_SHIFT (17U) 1429 #define ADC_DMAR1_SIDMAREN17_WIDTH (1U) 1430 #define ADC_DMAR1_SIDMAREN17(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN17_SHIFT)) & ADC_DMAR1_SIDMAREN17_MASK) 1431 1432 #define ADC_DMAR1_SIDMAREN18_MASK (0x40000U) 1433 #define ADC_DMAR1_SIDMAREN18_SHIFT (18U) 1434 #define ADC_DMAR1_SIDMAREN18_WIDTH (1U) 1435 #define ADC_DMAR1_SIDMAREN18(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN18_SHIFT)) & ADC_DMAR1_SIDMAREN18_MASK) 1436 1437 #define ADC_DMAR1_SIDMAREN19_MASK (0x80000U) 1438 #define ADC_DMAR1_SIDMAREN19_SHIFT (19U) 1439 #define ADC_DMAR1_SIDMAREN19_WIDTH (1U) 1440 #define ADC_DMAR1_SIDMAREN19(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN19_SHIFT)) & ADC_DMAR1_SIDMAREN19_MASK) 1441 1442 #define ADC_DMAR1_SIDMAREN20_MASK (0x100000U) 1443 #define ADC_DMAR1_SIDMAREN20_SHIFT (20U) 1444 #define ADC_DMAR1_SIDMAREN20_WIDTH (1U) 1445 #define ADC_DMAR1_SIDMAREN20(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN20_SHIFT)) & ADC_DMAR1_SIDMAREN20_MASK) 1446 1447 #define ADC_DMAR1_SIDMAREN21_MASK (0x200000U) 1448 #define ADC_DMAR1_SIDMAREN21_SHIFT (21U) 1449 #define ADC_DMAR1_SIDMAREN21_WIDTH (1U) 1450 #define ADC_DMAR1_SIDMAREN21(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN21_SHIFT)) & ADC_DMAR1_SIDMAREN21_MASK) 1451 1452 #define ADC_DMAR1_SIDMAREN22_MASK (0x400000U) 1453 #define ADC_DMAR1_SIDMAREN22_SHIFT (22U) 1454 #define ADC_DMAR1_SIDMAREN22_WIDTH (1U) 1455 #define ADC_DMAR1_SIDMAREN22(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN22_SHIFT)) & ADC_DMAR1_SIDMAREN22_MASK) 1456 1457 #define ADC_DMAR1_SIDMAREN23_MASK (0x800000U) 1458 #define ADC_DMAR1_SIDMAREN23_SHIFT (23U) 1459 #define ADC_DMAR1_SIDMAREN23_WIDTH (1U) 1460 #define ADC_DMAR1_SIDMAREN23(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_SIDMAREN23_SHIFT)) & ADC_DMAR1_SIDMAREN23_MASK) 1461 /*! @} */ 1462 1463 /*! @name DMAR2 - DMA Request Enable For External Inputs */ 1464 /*! @{ */ 1465 1466 #define ADC_DMAR2_EIDMAREN0_MASK (0x1U) 1467 #define ADC_DMAR2_EIDMAREN0_SHIFT (0U) 1468 #define ADC_DMAR2_EIDMAREN0_WIDTH (1U) 1469 #define ADC_DMAR2_EIDMAREN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN0_SHIFT)) & ADC_DMAR2_EIDMAREN0_MASK) 1470 1471 #define ADC_DMAR2_EIDMAREN1_MASK (0x2U) 1472 #define ADC_DMAR2_EIDMAREN1_SHIFT (1U) 1473 #define ADC_DMAR2_EIDMAREN1_WIDTH (1U) 1474 #define ADC_DMAR2_EIDMAREN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN1_SHIFT)) & ADC_DMAR2_EIDMAREN1_MASK) 1475 1476 #define ADC_DMAR2_EIDMAREN2_MASK (0x4U) 1477 #define ADC_DMAR2_EIDMAREN2_SHIFT (2U) 1478 #define ADC_DMAR2_EIDMAREN2_WIDTH (1U) 1479 #define ADC_DMAR2_EIDMAREN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN2_SHIFT)) & ADC_DMAR2_EIDMAREN2_MASK) 1480 1481 #define ADC_DMAR2_EIDMAREN3_MASK (0x8U) 1482 #define ADC_DMAR2_EIDMAREN3_SHIFT (3U) 1483 #define ADC_DMAR2_EIDMAREN3_WIDTH (1U) 1484 #define ADC_DMAR2_EIDMAREN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN3_SHIFT)) & ADC_DMAR2_EIDMAREN3_MASK) 1485 1486 #define ADC_DMAR2_EIDMAREN4_MASK (0x10U) 1487 #define ADC_DMAR2_EIDMAREN4_SHIFT (4U) 1488 #define ADC_DMAR2_EIDMAREN4_WIDTH (1U) 1489 #define ADC_DMAR2_EIDMAREN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN4_SHIFT)) & ADC_DMAR2_EIDMAREN4_MASK) 1490 1491 #define ADC_DMAR2_EIDMAREN5_MASK (0x20U) 1492 #define ADC_DMAR2_EIDMAREN5_SHIFT (5U) 1493 #define ADC_DMAR2_EIDMAREN5_WIDTH (1U) 1494 #define ADC_DMAR2_EIDMAREN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN5_SHIFT)) & ADC_DMAR2_EIDMAREN5_MASK) 1495 1496 #define ADC_DMAR2_EIDMAREN6_MASK (0x40U) 1497 #define ADC_DMAR2_EIDMAREN6_SHIFT (6U) 1498 #define ADC_DMAR2_EIDMAREN6_WIDTH (1U) 1499 #define ADC_DMAR2_EIDMAREN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN6_SHIFT)) & ADC_DMAR2_EIDMAREN6_MASK) 1500 1501 #define ADC_DMAR2_EIDMAREN7_MASK (0x80U) 1502 #define ADC_DMAR2_EIDMAREN7_SHIFT (7U) 1503 #define ADC_DMAR2_EIDMAREN7_WIDTH (1U) 1504 #define ADC_DMAR2_EIDMAREN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN7_SHIFT)) & ADC_DMAR2_EIDMAREN7_MASK) 1505 1506 #define ADC_DMAR2_EIDMAREN8_MASK (0x100U) 1507 #define ADC_DMAR2_EIDMAREN8_SHIFT (8U) 1508 #define ADC_DMAR2_EIDMAREN8_WIDTH (1U) 1509 #define ADC_DMAR2_EIDMAREN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN8_SHIFT)) & ADC_DMAR2_EIDMAREN8_MASK) 1510 1511 #define ADC_DMAR2_EIDMAREN9_MASK (0x200U) 1512 #define ADC_DMAR2_EIDMAREN9_SHIFT (9U) 1513 #define ADC_DMAR2_EIDMAREN9_WIDTH (1U) 1514 #define ADC_DMAR2_EIDMAREN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN9_SHIFT)) & ADC_DMAR2_EIDMAREN9_MASK) 1515 1516 #define ADC_DMAR2_EIDMAREN10_MASK (0x400U) 1517 #define ADC_DMAR2_EIDMAREN10_SHIFT (10U) 1518 #define ADC_DMAR2_EIDMAREN10_WIDTH (1U) 1519 #define ADC_DMAR2_EIDMAREN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN10_SHIFT)) & ADC_DMAR2_EIDMAREN10_MASK) 1520 1521 #define ADC_DMAR2_EIDMAREN11_MASK (0x800U) 1522 #define ADC_DMAR2_EIDMAREN11_SHIFT (11U) 1523 #define ADC_DMAR2_EIDMAREN11_WIDTH (1U) 1524 #define ADC_DMAR2_EIDMAREN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN11_SHIFT)) & ADC_DMAR2_EIDMAREN11_MASK) 1525 1526 #define ADC_DMAR2_EIDMAREN12_MASK (0x1000U) 1527 #define ADC_DMAR2_EIDMAREN12_SHIFT (12U) 1528 #define ADC_DMAR2_EIDMAREN12_WIDTH (1U) 1529 #define ADC_DMAR2_EIDMAREN12(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN12_SHIFT)) & ADC_DMAR2_EIDMAREN12_MASK) 1530 1531 #define ADC_DMAR2_EIDMAREN13_MASK (0x2000U) 1532 #define ADC_DMAR2_EIDMAREN13_SHIFT (13U) 1533 #define ADC_DMAR2_EIDMAREN13_WIDTH (1U) 1534 #define ADC_DMAR2_EIDMAREN13(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN13_SHIFT)) & ADC_DMAR2_EIDMAREN13_MASK) 1535 1536 #define ADC_DMAR2_EIDMAREN14_MASK (0x4000U) 1537 #define ADC_DMAR2_EIDMAREN14_SHIFT (14U) 1538 #define ADC_DMAR2_EIDMAREN14_WIDTH (1U) 1539 #define ADC_DMAR2_EIDMAREN14(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN14_SHIFT)) & ADC_DMAR2_EIDMAREN14_MASK) 1540 1541 #define ADC_DMAR2_EIDMAREN15_MASK (0x8000U) 1542 #define ADC_DMAR2_EIDMAREN15_SHIFT (15U) 1543 #define ADC_DMAR2_EIDMAREN15_WIDTH (1U) 1544 #define ADC_DMAR2_EIDMAREN15(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN15_SHIFT)) & ADC_DMAR2_EIDMAREN15_MASK) 1545 1546 #define ADC_DMAR2_EIDMAREN16_MASK (0x10000U) 1547 #define ADC_DMAR2_EIDMAREN16_SHIFT (16U) 1548 #define ADC_DMAR2_EIDMAREN16_WIDTH (1U) 1549 #define ADC_DMAR2_EIDMAREN16(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN16_SHIFT)) & ADC_DMAR2_EIDMAREN16_MASK) 1550 1551 #define ADC_DMAR2_EIDMAREN17_MASK (0x20000U) 1552 #define ADC_DMAR2_EIDMAREN17_SHIFT (17U) 1553 #define ADC_DMAR2_EIDMAREN17_WIDTH (1U) 1554 #define ADC_DMAR2_EIDMAREN17(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN17_SHIFT)) & ADC_DMAR2_EIDMAREN17_MASK) 1555 1556 #define ADC_DMAR2_EIDMAREN18_MASK (0x40000U) 1557 #define ADC_DMAR2_EIDMAREN18_SHIFT (18U) 1558 #define ADC_DMAR2_EIDMAREN18_WIDTH (1U) 1559 #define ADC_DMAR2_EIDMAREN18(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN18_SHIFT)) & ADC_DMAR2_EIDMAREN18_MASK) 1560 1561 #define ADC_DMAR2_EIDMAREN19_MASK (0x80000U) 1562 #define ADC_DMAR2_EIDMAREN19_SHIFT (19U) 1563 #define ADC_DMAR2_EIDMAREN19_WIDTH (1U) 1564 #define ADC_DMAR2_EIDMAREN19(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN19_SHIFT)) & ADC_DMAR2_EIDMAREN19_MASK) 1565 1566 #define ADC_DMAR2_EIDMAREN20_MASK (0x100000U) 1567 #define ADC_DMAR2_EIDMAREN20_SHIFT (20U) 1568 #define ADC_DMAR2_EIDMAREN20_WIDTH (1U) 1569 #define ADC_DMAR2_EIDMAREN20(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN20_SHIFT)) & ADC_DMAR2_EIDMAREN20_MASK) 1570 1571 #define ADC_DMAR2_EIDMAREN21_MASK (0x200000U) 1572 #define ADC_DMAR2_EIDMAREN21_SHIFT (21U) 1573 #define ADC_DMAR2_EIDMAREN21_WIDTH (1U) 1574 #define ADC_DMAR2_EIDMAREN21(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN21_SHIFT)) & ADC_DMAR2_EIDMAREN21_MASK) 1575 1576 #define ADC_DMAR2_EIDMAREN22_MASK (0x400000U) 1577 #define ADC_DMAR2_EIDMAREN22_SHIFT (22U) 1578 #define ADC_DMAR2_EIDMAREN22_WIDTH (1U) 1579 #define ADC_DMAR2_EIDMAREN22(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN22_SHIFT)) & ADC_DMAR2_EIDMAREN22_MASK) 1580 1581 #define ADC_DMAR2_EIDMAREN23_MASK (0x800000U) 1582 #define ADC_DMAR2_EIDMAREN23_SHIFT (23U) 1583 #define ADC_DMAR2_EIDMAREN23_WIDTH (1U) 1584 #define ADC_DMAR2_EIDMAREN23(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN23_SHIFT)) & ADC_DMAR2_EIDMAREN23_MASK) 1585 1586 #define ADC_DMAR2_EIDMAREN24_MASK (0x1000000U) 1587 #define ADC_DMAR2_EIDMAREN24_SHIFT (24U) 1588 #define ADC_DMAR2_EIDMAREN24_WIDTH (1U) 1589 #define ADC_DMAR2_EIDMAREN24(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN24_SHIFT)) & ADC_DMAR2_EIDMAREN24_MASK) 1590 1591 #define ADC_DMAR2_EIDMAREN25_MASK (0x2000000U) 1592 #define ADC_DMAR2_EIDMAREN25_SHIFT (25U) 1593 #define ADC_DMAR2_EIDMAREN25_WIDTH (1U) 1594 #define ADC_DMAR2_EIDMAREN25(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN25_SHIFT)) & ADC_DMAR2_EIDMAREN25_MASK) 1595 1596 #define ADC_DMAR2_EIDMAREN26_MASK (0x4000000U) 1597 #define ADC_DMAR2_EIDMAREN26_SHIFT (26U) 1598 #define ADC_DMAR2_EIDMAREN26_WIDTH (1U) 1599 #define ADC_DMAR2_EIDMAREN26(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN26_SHIFT)) & ADC_DMAR2_EIDMAREN26_MASK) 1600 1601 #define ADC_DMAR2_EIDMAREN27_MASK (0x8000000U) 1602 #define ADC_DMAR2_EIDMAREN27_SHIFT (27U) 1603 #define ADC_DMAR2_EIDMAREN27_WIDTH (1U) 1604 #define ADC_DMAR2_EIDMAREN27(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN27_SHIFT)) & ADC_DMAR2_EIDMAREN27_MASK) 1605 1606 #define ADC_DMAR2_EIDMAREN28_MASK (0x10000000U) 1607 #define ADC_DMAR2_EIDMAREN28_SHIFT (28U) 1608 #define ADC_DMAR2_EIDMAREN28_WIDTH (1U) 1609 #define ADC_DMAR2_EIDMAREN28(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN28_SHIFT)) & ADC_DMAR2_EIDMAREN28_MASK) 1610 1611 #define ADC_DMAR2_EIDMAREN29_MASK (0x20000000U) 1612 #define ADC_DMAR2_EIDMAREN29_SHIFT (29U) 1613 #define ADC_DMAR2_EIDMAREN29_WIDTH (1U) 1614 #define ADC_DMAR2_EIDMAREN29(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN29_SHIFT)) & ADC_DMAR2_EIDMAREN29_MASK) 1615 1616 #define ADC_DMAR2_EIDMAREN30_MASK (0x40000000U) 1617 #define ADC_DMAR2_EIDMAREN30_SHIFT (30U) 1618 #define ADC_DMAR2_EIDMAREN30_WIDTH (1U) 1619 #define ADC_DMAR2_EIDMAREN30(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN30_SHIFT)) & ADC_DMAR2_EIDMAREN30_MASK) 1620 1621 #define ADC_DMAR2_EIDMAREN31_MASK (0x80000000U) 1622 #define ADC_DMAR2_EIDMAREN31_SHIFT (31U) 1623 #define ADC_DMAR2_EIDMAREN31_WIDTH (1U) 1624 #define ADC_DMAR2_EIDMAREN31(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR2_EIDMAREN31_SHIFT)) & ADC_DMAR2_EIDMAREN31_MASK) 1625 /*! @} */ 1626 1627 /*! @name THRHLR - Analog Watchdog Threshold Values */ 1628 /*! @{ */ 1629 1630 #define ADC_THRHLR_THRL_MASK (0x7FFFU) 1631 #define ADC_THRHLR_THRL_SHIFT (0U) 1632 #define ADC_THRHLR_THRL_WIDTH (15U) 1633 #define ADC_THRHLR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR_THRL_SHIFT)) & ADC_THRHLR_THRL_MASK) 1634 1635 #define ADC_THRHLR_THRH_MASK (0x7FFF0000U) 1636 #define ADC_THRHLR_THRH_SHIFT (16U) 1637 #define ADC_THRHLR_THRH_WIDTH (15U) 1638 #define ADC_THRHLR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR_THRH_SHIFT)) & ADC_THRHLR_THRH_MASK) 1639 /*! @} */ 1640 1641 /*! @name PSCR - Presampling Control */ 1642 /*! @{ */ 1643 1644 #define ADC_PSCR_PRECONV_MASK (0x1U) 1645 #define ADC_PSCR_PRECONV_SHIFT (0U) 1646 #define ADC_PSCR_PRECONV_WIDTH (1U) 1647 #define ADC_PSCR_PRECONV(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PRECONV_SHIFT)) & ADC_PSCR_PRECONV_MASK) 1648 1649 #define ADC_PSCR_PREVAL0_MASK (0x2U) 1650 #define ADC_PSCR_PREVAL0_SHIFT (1U) 1651 #define ADC_PSCR_PREVAL0_WIDTH (1U) 1652 #define ADC_PSCR_PREVAL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL0_SHIFT)) & ADC_PSCR_PREVAL0_MASK) 1653 1654 #define ADC_PSCR_PREVAL1_MASK (0x8U) 1655 #define ADC_PSCR_PREVAL1_SHIFT (3U) 1656 #define ADC_PSCR_PREVAL1_WIDTH (1U) 1657 #define ADC_PSCR_PREVAL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL1_SHIFT)) & ADC_PSCR_PREVAL1_MASK) 1658 1659 #define ADC_PSCR_PREVAL2_MASK (0x20U) 1660 #define ADC_PSCR_PREVAL2_SHIFT (5U) 1661 #define ADC_PSCR_PREVAL2_WIDTH (1U) 1662 #define ADC_PSCR_PREVAL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL2_SHIFT)) & ADC_PSCR_PREVAL2_MASK) 1663 /*! @} */ 1664 1665 /*! @name PSR0 - Presampling Enable For Precision Inputs */ 1666 /*! @{ */ 1667 1668 #define ADC_PSR0_PRES0_MASK (0x1U) 1669 #define ADC_PSR0_PRES0_SHIFT (0U) 1670 #define ADC_PSR0_PRES0_WIDTH (1U) 1671 #define ADC_PSR0_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES0_SHIFT)) & ADC_PSR0_PRES0_MASK) 1672 1673 #define ADC_PSR0_PRES1_MASK (0x2U) 1674 #define ADC_PSR0_PRES1_SHIFT (1U) 1675 #define ADC_PSR0_PRES1_WIDTH (1U) 1676 #define ADC_PSR0_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES1_SHIFT)) & ADC_PSR0_PRES1_MASK) 1677 1678 #define ADC_PSR0_PRES2_MASK (0x4U) 1679 #define ADC_PSR0_PRES2_SHIFT (2U) 1680 #define ADC_PSR0_PRES2_WIDTH (1U) 1681 #define ADC_PSR0_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES2_SHIFT)) & ADC_PSR0_PRES2_MASK) 1682 1683 #define ADC_PSR0_PRES3_MASK (0x8U) 1684 #define ADC_PSR0_PRES3_SHIFT (3U) 1685 #define ADC_PSR0_PRES3_WIDTH (1U) 1686 #define ADC_PSR0_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES3_SHIFT)) & ADC_PSR0_PRES3_MASK) 1687 1688 #define ADC_PSR0_PRES4_MASK (0x10U) 1689 #define ADC_PSR0_PRES4_SHIFT (4U) 1690 #define ADC_PSR0_PRES4_WIDTH (1U) 1691 #define ADC_PSR0_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES4_SHIFT)) & ADC_PSR0_PRES4_MASK) 1692 1693 #define ADC_PSR0_PRES5_MASK (0x20U) 1694 #define ADC_PSR0_PRES5_SHIFT (5U) 1695 #define ADC_PSR0_PRES5_WIDTH (1U) 1696 #define ADC_PSR0_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES5_SHIFT)) & ADC_PSR0_PRES5_MASK) 1697 1698 #define ADC_PSR0_PRES6_MASK (0x40U) 1699 #define ADC_PSR0_PRES6_SHIFT (6U) 1700 #define ADC_PSR0_PRES6_WIDTH (1U) 1701 #define ADC_PSR0_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES6_SHIFT)) & ADC_PSR0_PRES6_MASK) 1702 1703 #define ADC_PSR0_PRES7_MASK (0x80U) 1704 #define ADC_PSR0_PRES7_SHIFT (7U) 1705 #define ADC_PSR0_PRES7_WIDTH (1U) 1706 #define ADC_PSR0_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES7_SHIFT)) & ADC_PSR0_PRES7_MASK) 1707 /*! @} */ 1708 1709 /*! @name PSR1 - Presampling Enable For Standard Inputs */ 1710 /*! @{ */ 1711 1712 #define ADC_PSR1_PRES0_MASK (0x1U) 1713 #define ADC_PSR1_PRES0_SHIFT (0U) 1714 #define ADC_PSR1_PRES0_WIDTH (1U) 1715 #define ADC_PSR1_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES0_SHIFT)) & ADC_PSR1_PRES0_MASK) 1716 1717 #define ADC_PSR1_PRES1_MASK (0x2U) 1718 #define ADC_PSR1_PRES1_SHIFT (1U) 1719 #define ADC_PSR1_PRES1_WIDTH (1U) 1720 #define ADC_PSR1_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES1_SHIFT)) & ADC_PSR1_PRES1_MASK) 1721 1722 #define ADC_PSR1_PRES2_MASK (0x4U) 1723 #define ADC_PSR1_PRES2_SHIFT (2U) 1724 #define ADC_PSR1_PRES2_WIDTH (1U) 1725 #define ADC_PSR1_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES2_SHIFT)) & ADC_PSR1_PRES2_MASK) 1726 1727 #define ADC_PSR1_PRES3_MASK (0x8U) 1728 #define ADC_PSR1_PRES3_SHIFT (3U) 1729 #define ADC_PSR1_PRES3_WIDTH (1U) 1730 #define ADC_PSR1_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES3_SHIFT)) & ADC_PSR1_PRES3_MASK) 1731 1732 #define ADC_PSR1_PRES4_MASK (0x10U) 1733 #define ADC_PSR1_PRES4_SHIFT (4U) 1734 #define ADC_PSR1_PRES4_WIDTH (1U) 1735 #define ADC_PSR1_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES4_SHIFT)) & ADC_PSR1_PRES4_MASK) 1736 1737 #define ADC_PSR1_PRES5_MASK (0x20U) 1738 #define ADC_PSR1_PRES5_SHIFT (5U) 1739 #define ADC_PSR1_PRES5_WIDTH (1U) 1740 #define ADC_PSR1_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES5_SHIFT)) & ADC_PSR1_PRES5_MASK) 1741 1742 #define ADC_PSR1_PRES6_MASK (0x40U) 1743 #define ADC_PSR1_PRES6_SHIFT (6U) 1744 #define ADC_PSR1_PRES6_WIDTH (1U) 1745 #define ADC_PSR1_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES6_SHIFT)) & ADC_PSR1_PRES6_MASK) 1746 1747 #define ADC_PSR1_PRES7_MASK (0x80U) 1748 #define ADC_PSR1_PRES7_SHIFT (7U) 1749 #define ADC_PSR1_PRES7_WIDTH (1U) 1750 #define ADC_PSR1_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES7_SHIFT)) & ADC_PSR1_PRES7_MASK) 1751 1752 #define ADC_PSR1_PRES8_MASK (0x100U) 1753 #define ADC_PSR1_PRES8_SHIFT (8U) 1754 #define ADC_PSR1_PRES8_WIDTH (1U) 1755 #define ADC_PSR1_PRES8(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES8_SHIFT)) & ADC_PSR1_PRES8_MASK) 1756 1757 #define ADC_PSR1_PRES9_MASK (0x200U) 1758 #define ADC_PSR1_PRES9_SHIFT (9U) 1759 #define ADC_PSR1_PRES9_WIDTH (1U) 1760 #define ADC_PSR1_PRES9(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES9_SHIFT)) & ADC_PSR1_PRES9_MASK) 1761 1762 #define ADC_PSR1_PRES10_MASK (0x400U) 1763 #define ADC_PSR1_PRES10_SHIFT (10U) 1764 #define ADC_PSR1_PRES10_WIDTH (1U) 1765 #define ADC_PSR1_PRES10(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES10_SHIFT)) & ADC_PSR1_PRES10_MASK) 1766 1767 #define ADC_PSR1_PRES11_MASK (0x800U) 1768 #define ADC_PSR1_PRES11_SHIFT (11U) 1769 #define ADC_PSR1_PRES11_WIDTH (1U) 1770 #define ADC_PSR1_PRES11(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES11_SHIFT)) & ADC_PSR1_PRES11_MASK) 1771 1772 #define ADC_PSR1_PRES12_MASK (0x1000U) 1773 #define ADC_PSR1_PRES12_SHIFT (12U) 1774 #define ADC_PSR1_PRES12_WIDTH (1U) 1775 #define ADC_PSR1_PRES12(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES12_SHIFT)) & ADC_PSR1_PRES12_MASK) 1776 1777 #define ADC_PSR1_PRES13_MASK (0x2000U) 1778 #define ADC_PSR1_PRES13_SHIFT (13U) 1779 #define ADC_PSR1_PRES13_WIDTH (1U) 1780 #define ADC_PSR1_PRES13(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES13_SHIFT)) & ADC_PSR1_PRES13_MASK) 1781 1782 #define ADC_PSR1_PRES14_MASK (0x4000U) 1783 #define ADC_PSR1_PRES14_SHIFT (14U) 1784 #define ADC_PSR1_PRES14_WIDTH (1U) 1785 #define ADC_PSR1_PRES14(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES14_SHIFT)) & ADC_PSR1_PRES14_MASK) 1786 1787 #define ADC_PSR1_PRES15_MASK (0x8000U) 1788 #define ADC_PSR1_PRES15_SHIFT (15U) 1789 #define ADC_PSR1_PRES15_WIDTH (1U) 1790 #define ADC_PSR1_PRES15(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES15_SHIFT)) & ADC_PSR1_PRES15_MASK) 1791 1792 #define ADC_PSR1_PRES16_MASK (0x10000U) 1793 #define ADC_PSR1_PRES16_SHIFT (16U) 1794 #define ADC_PSR1_PRES16_WIDTH (1U) 1795 #define ADC_PSR1_PRES16(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES16_SHIFT)) & ADC_PSR1_PRES16_MASK) 1796 1797 #define ADC_PSR1_PRES17_MASK (0x20000U) 1798 #define ADC_PSR1_PRES17_SHIFT (17U) 1799 #define ADC_PSR1_PRES17_WIDTH (1U) 1800 #define ADC_PSR1_PRES17(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES17_SHIFT)) & ADC_PSR1_PRES17_MASK) 1801 1802 #define ADC_PSR1_PRES18_MASK (0x40000U) 1803 #define ADC_PSR1_PRES18_SHIFT (18U) 1804 #define ADC_PSR1_PRES18_WIDTH (1U) 1805 #define ADC_PSR1_PRES18(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES18_SHIFT)) & ADC_PSR1_PRES18_MASK) 1806 1807 #define ADC_PSR1_PRES19_MASK (0x80000U) 1808 #define ADC_PSR1_PRES19_SHIFT (19U) 1809 #define ADC_PSR1_PRES19_WIDTH (1U) 1810 #define ADC_PSR1_PRES19(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES19_SHIFT)) & ADC_PSR1_PRES19_MASK) 1811 1812 #define ADC_PSR1_PRES20_MASK (0x100000U) 1813 #define ADC_PSR1_PRES20_SHIFT (20U) 1814 #define ADC_PSR1_PRES20_WIDTH (1U) 1815 #define ADC_PSR1_PRES20(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES20_SHIFT)) & ADC_PSR1_PRES20_MASK) 1816 1817 #define ADC_PSR1_PRES21_MASK (0x200000U) 1818 #define ADC_PSR1_PRES21_SHIFT (21U) 1819 #define ADC_PSR1_PRES21_WIDTH (1U) 1820 #define ADC_PSR1_PRES21(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES21_SHIFT)) & ADC_PSR1_PRES21_MASK) 1821 1822 #define ADC_PSR1_PRES22_MASK (0x400000U) 1823 #define ADC_PSR1_PRES22_SHIFT (22U) 1824 #define ADC_PSR1_PRES22_WIDTH (1U) 1825 #define ADC_PSR1_PRES22(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES22_SHIFT)) & ADC_PSR1_PRES22_MASK) 1826 1827 #define ADC_PSR1_PRES23_MASK (0x800000U) 1828 #define ADC_PSR1_PRES23_SHIFT (23U) 1829 #define ADC_PSR1_PRES23_WIDTH (1U) 1830 #define ADC_PSR1_PRES23(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES23_SHIFT)) & ADC_PSR1_PRES23_MASK) 1831 /*! @} */ 1832 1833 /*! @name PSR2 - Presampling Enable For External Inputs */ 1834 /*! @{ */ 1835 1836 #define ADC_PSR2_PRES0_MASK (0x1U) 1837 #define ADC_PSR2_PRES0_SHIFT (0U) 1838 #define ADC_PSR2_PRES0_WIDTH (1U) 1839 #define ADC_PSR2_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES0_SHIFT)) & ADC_PSR2_PRES0_MASK) 1840 1841 #define ADC_PSR2_PRES1_MASK (0x2U) 1842 #define ADC_PSR2_PRES1_SHIFT (1U) 1843 #define ADC_PSR2_PRES1_WIDTH (1U) 1844 #define ADC_PSR2_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES1_SHIFT)) & ADC_PSR2_PRES1_MASK) 1845 1846 #define ADC_PSR2_PRES2_MASK (0x4U) 1847 #define ADC_PSR2_PRES2_SHIFT (2U) 1848 #define ADC_PSR2_PRES2_WIDTH (1U) 1849 #define ADC_PSR2_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES2_SHIFT)) & ADC_PSR2_PRES2_MASK) 1850 1851 #define ADC_PSR2_PRES3_MASK (0x8U) 1852 #define ADC_PSR2_PRES3_SHIFT (3U) 1853 #define ADC_PSR2_PRES3_WIDTH (1U) 1854 #define ADC_PSR2_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES3_SHIFT)) & ADC_PSR2_PRES3_MASK) 1855 1856 #define ADC_PSR2_PRES4_MASK (0x10U) 1857 #define ADC_PSR2_PRES4_SHIFT (4U) 1858 #define ADC_PSR2_PRES4_WIDTH (1U) 1859 #define ADC_PSR2_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES4_SHIFT)) & ADC_PSR2_PRES4_MASK) 1860 1861 #define ADC_PSR2_PRES5_MASK (0x20U) 1862 #define ADC_PSR2_PRES5_SHIFT (5U) 1863 #define ADC_PSR2_PRES5_WIDTH (1U) 1864 #define ADC_PSR2_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES5_SHIFT)) & ADC_PSR2_PRES5_MASK) 1865 1866 #define ADC_PSR2_PRES6_MASK (0x40U) 1867 #define ADC_PSR2_PRES6_SHIFT (6U) 1868 #define ADC_PSR2_PRES6_WIDTH (1U) 1869 #define ADC_PSR2_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES6_SHIFT)) & ADC_PSR2_PRES6_MASK) 1870 1871 #define ADC_PSR2_PRES7_MASK (0x80U) 1872 #define ADC_PSR2_PRES7_SHIFT (7U) 1873 #define ADC_PSR2_PRES7_WIDTH (1U) 1874 #define ADC_PSR2_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES7_SHIFT)) & ADC_PSR2_PRES7_MASK) 1875 1876 #define ADC_PSR2_PRES8_MASK (0x100U) 1877 #define ADC_PSR2_PRES8_SHIFT (8U) 1878 #define ADC_PSR2_PRES8_WIDTH (1U) 1879 #define ADC_PSR2_PRES8(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES8_SHIFT)) & ADC_PSR2_PRES8_MASK) 1880 1881 #define ADC_PSR2_PRES9_MASK (0x200U) 1882 #define ADC_PSR2_PRES9_SHIFT (9U) 1883 #define ADC_PSR2_PRES9_WIDTH (1U) 1884 #define ADC_PSR2_PRES9(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES9_SHIFT)) & ADC_PSR2_PRES9_MASK) 1885 1886 #define ADC_PSR2_PRES10_MASK (0x400U) 1887 #define ADC_PSR2_PRES10_SHIFT (10U) 1888 #define ADC_PSR2_PRES10_WIDTH (1U) 1889 #define ADC_PSR2_PRES10(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES10_SHIFT)) & ADC_PSR2_PRES10_MASK) 1890 1891 #define ADC_PSR2_PRES11_MASK (0x800U) 1892 #define ADC_PSR2_PRES11_SHIFT (11U) 1893 #define ADC_PSR2_PRES11_WIDTH (1U) 1894 #define ADC_PSR2_PRES11(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES11_SHIFT)) & ADC_PSR2_PRES11_MASK) 1895 1896 #define ADC_PSR2_PRES12_MASK (0x1000U) 1897 #define ADC_PSR2_PRES12_SHIFT (12U) 1898 #define ADC_PSR2_PRES12_WIDTH (1U) 1899 #define ADC_PSR2_PRES12(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES12_SHIFT)) & ADC_PSR2_PRES12_MASK) 1900 1901 #define ADC_PSR2_PRES13_MASK (0x2000U) 1902 #define ADC_PSR2_PRES13_SHIFT (13U) 1903 #define ADC_PSR2_PRES13_WIDTH (1U) 1904 #define ADC_PSR2_PRES13(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES13_SHIFT)) & ADC_PSR2_PRES13_MASK) 1905 1906 #define ADC_PSR2_PRES14_MASK (0x4000U) 1907 #define ADC_PSR2_PRES14_SHIFT (14U) 1908 #define ADC_PSR2_PRES14_WIDTH (1U) 1909 #define ADC_PSR2_PRES14(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES14_SHIFT)) & ADC_PSR2_PRES14_MASK) 1910 1911 #define ADC_PSR2_PRES15_MASK (0x8000U) 1912 #define ADC_PSR2_PRES15_SHIFT (15U) 1913 #define ADC_PSR2_PRES15_WIDTH (1U) 1914 #define ADC_PSR2_PRES15(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES15_SHIFT)) & ADC_PSR2_PRES15_MASK) 1915 1916 #define ADC_PSR2_PRES16_MASK (0x10000U) 1917 #define ADC_PSR2_PRES16_SHIFT (16U) 1918 #define ADC_PSR2_PRES16_WIDTH (1U) 1919 #define ADC_PSR2_PRES16(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES16_SHIFT)) & ADC_PSR2_PRES16_MASK) 1920 1921 #define ADC_PSR2_PRES17_MASK (0x20000U) 1922 #define ADC_PSR2_PRES17_SHIFT (17U) 1923 #define ADC_PSR2_PRES17_WIDTH (1U) 1924 #define ADC_PSR2_PRES17(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES17_SHIFT)) & ADC_PSR2_PRES17_MASK) 1925 1926 #define ADC_PSR2_PRES18_MASK (0x40000U) 1927 #define ADC_PSR2_PRES18_SHIFT (18U) 1928 #define ADC_PSR2_PRES18_WIDTH (1U) 1929 #define ADC_PSR2_PRES18(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES18_SHIFT)) & ADC_PSR2_PRES18_MASK) 1930 1931 #define ADC_PSR2_PRES19_MASK (0x80000U) 1932 #define ADC_PSR2_PRES19_SHIFT (19U) 1933 #define ADC_PSR2_PRES19_WIDTH (1U) 1934 #define ADC_PSR2_PRES19(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES19_SHIFT)) & ADC_PSR2_PRES19_MASK) 1935 1936 #define ADC_PSR2_PRES20_MASK (0x100000U) 1937 #define ADC_PSR2_PRES20_SHIFT (20U) 1938 #define ADC_PSR2_PRES20_WIDTH (1U) 1939 #define ADC_PSR2_PRES20(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES20_SHIFT)) & ADC_PSR2_PRES20_MASK) 1940 1941 #define ADC_PSR2_PRES21_MASK (0x200000U) 1942 #define ADC_PSR2_PRES21_SHIFT (21U) 1943 #define ADC_PSR2_PRES21_WIDTH (1U) 1944 #define ADC_PSR2_PRES21(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES21_SHIFT)) & ADC_PSR2_PRES21_MASK) 1945 1946 #define ADC_PSR2_PRES22_MASK (0x400000U) 1947 #define ADC_PSR2_PRES22_SHIFT (22U) 1948 #define ADC_PSR2_PRES22_WIDTH (1U) 1949 #define ADC_PSR2_PRES22(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES22_SHIFT)) & ADC_PSR2_PRES22_MASK) 1950 1951 #define ADC_PSR2_PRES23_MASK (0x800000U) 1952 #define ADC_PSR2_PRES23_SHIFT (23U) 1953 #define ADC_PSR2_PRES23_WIDTH (1U) 1954 #define ADC_PSR2_PRES23(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES23_SHIFT)) & ADC_PSR2_PRES23_MASK) 1955 1956 #define ADC_PSR2_PRES24_MASK (0x1000000U) 1957 #define ADC_PSR2_PRES24_SHIFT (24U) 1958 #define ADC_PSR2_PRES24_WIDTH (1U) 1959 #define ADC_PSR2_PRES24(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES24_SHIFT)) & ADC_PSR2_PRES24_MASK) 1960 1961 #define ADC_PSR2_PRES25_MASK (0x2000000U) 1962 #define ADC_PSR2_PRES25_SHIFT (25U) 1963 #define ADC_PSR2_PRES25_WIDTH (1U) 1964 #define ADC_PSR2_PRES25(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES25_SHIFT)) & ADC_PSR2_PRES25_MASK) 1965 1966 #define ADC_PSR2_PRES26_MASK (0x4000000U) 1967 #define ADC_PSR2_PRES26_SHIFT (26U) 1968 #define ADC_PSR2_PRES26_WIDTH (1U) 1969 #define ADC_PSR2_PRES26(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES26_SHIFT)) & ADC_PSR2_PRES26_MASK) 1970 1971 #define ADC_PSR2_PRES27_MASK (0x8000000U) 1972 #define ADC_PSR2_PRES27_SHIFT (27U) 1973 #define ADC_PSR2_PRES27_WIDTH (1U) 1974 #define ADC_PSR2_PRES27(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES27_SHIFT)) & ADC_PSR2_PRES27_MASK) 1975 1976 #define ADC_PSR2_PRES28_MASK (0x10000000U) 1977 #define ADC_PSR2_PRES28_SHIFT (28U) 1978 #define ADC_PSR2_PRES28_WIDTH (1U) 1979 #define ADC_PSR2_PRES28(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES28_SHIFT)) & ADC_PSR2_PRES28_MASK) 1980 1981 #define ADC_PSR2_PRES29_MASK (0x20000000U) 1982 #define ADC_PSR2_PRES29_SHIFT (29U) 1983 #define ADC_PSR2_PRES29_WIDTH (1U) 1984 #define ADC_PSR2_PRES29(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES29_SHIFT)) & ADC_PSR2_PRES29_MASK) 1985 1986 #define ADC_PSR2_PRES30_MASK (0x40000000U) 1987 #define ADC_PSR2_PRES30_SHIFT (30U) 1988 #define ADC_PSR2_PRES30_WIDTH (1U) 1989 #define ADC_PSR2_PRES30(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES30_SHIFT)) & ADC_PSR2_PRES30_MASK) 1990 1991 #define ADC_PSR2_PRES31_MASK (0x80000000U) 1992 #define ADC_PSR2_PRES31_SHIFT (31U) 1993 #define ADC_PSR2_PRES31_WIDTH (1U) 1994 #define ADC_PSR2_PRES31(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR2_PRES31_SHIFT)) & ADC_PSR2_PRES31_MASK) 1995 /*! @} */ 1996 1997 /*! @name CTR0 - Conversion Timing For Precision Inputs */ 1998 /*! @{ */ 1999 2000 #define ADC_CTR0_INPSAMP_MASK (0xFFU) 2001 #define ADC_CTR0_INPSAMP_SHIFT (0U) 2002 #define ADC_CTR0_INPSAMP_WIDTH (8U) 2003 #define ADC_CTR0_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR0_INPSAMP_SHIFT)) & ADC_CTR0_INPSAMP_MASK) 2004 /*! @} */ 2005 2006 /*! @name CTR1 - Conversion Timing For Standard Inputs */ 2007 /*! @{ */ 2008 2009 #define ADC_CTR1_INPSAMP_MASK (0xFFU) 2010 #define ADC_CTR1_INPSAMP_SHIFT (0U) 2011 #define ADC_CTR1_INPSAMP_WIDTH (8U) 2012 #define ADC_CTR1_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR1_INPSAMP_SHIFT)) & ADC_CTR1_INPSAMP_MASK) 2013 /*! @} */ 2014 2015 /*! @name CTR2 - Conversion Timing For External Inputs */ 2016 /*! @{ */ 2017 2018 #define ADC_CTR2_INPSAMP_MASK (0xFFU) 2019 #define ADC_CTR2_INPSAMP_SHIFT (0U) 2020 #define ADC_CTR2_INPSAMP_WIDTH (8U) 2021 #define ADC_CTR2_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR2_INPSAMP_SHIFT)) & ADC_CTR2_INPSAMP_MASK) 2022 /*! @} */ 2023 2024 /*! @name NCMR0 - Normal Conversion Enable For Precision Inputs */ 2025 /*! @{ */ 2026 2027 #define ADC_NCMR0_CH0_MASK (0x1U) 2028 #define ADC_NCMR0_CH0_SHIFT (0U) 2029 #define ADC_NCMR0_CH0_WIDTH (1U) 2030 #define ADC_NCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH0_SHIFT)) & ADC_NCMR0_CH0_MASK) 2031 2032 #define ADC_NCMR0_CH1_MASK (0x2U) 2033 #define ADC_NCMR0_CH1_SHIFT (1U) 2034 #define ADC_NCMR0_CH1_WIDTH (1U) 2035 #define ADC_NCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH1_SHIFT)) & ADC_NCMR0_CH1_MASK) 2036 2037 #define ADC_NCMR0_CH2_MASK (0x4U) 2038 #define ADC_NCMR0_CH2_SHIFT (2U) 2039 #define ADC_NCMR0_CH2_WIDTH (1U) 2040 #define ADC_NCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH2_SHIFT)) & ADC_NCMR0_CH2_MASK) 2041 2042 #define ADC_NCMR0_CH3_MASK (0x8U) 2043 #define ADC_NCMR0_CH3_SHIFT (3U) 2044 #define ADC_NCMR0_CH3_WIDTH (1U) 2045 #define ADC_NCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH3_SHIFT)) & ADC_NCMR0_CH3_MASK) 2046 2047 #define ADC_NCMR0_CH4_MASK (0x10U) 2048 #define ADC_NCMR0_CH4_SHIFT (4U) 2049 #define ADC_NCMR0_CH4_WIDTH (1U) 2050 #define ADC_NCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH4_SHIFT)) & ADC_NCMR0_CH4_MASK) 2051 2052 #define ADC_NCMR0_CH5_MASK (0x20U) 2053 #define ADC_NCMR0_CH5_SHIFT (5U) 2054 #define ADC_NCMR0_CH5_WIDTH (1U) 2055 #define ADC_NCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH5_SHIFT)) & ADC_NCMR0_CH5_MASK) 2056 2057 #define ADC_NCMR0_CH6_MASK (0x40U) 2058 #define ADC_NCMR0_CH6_SHIFT (6U) 2059 #define ADC_NCMR0_CH6_WIDTH (1U) 2060 #define ADC_NCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH6_SHIFT)) & ADC_NCMR0_CH6_MASK) 2061 2062 #define ADC_NCMR0_CH7_MASK (0x80U) 2063 #define ADC_NCMR0_CH7_SHIFT (7U) 2064 #define ADC_NCMR0_CH7_WIDTH (1U) 2065 #define ADC_NCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH7_SHIFT)) & ADC_NCMR0_CH7_MASK) 2066 /*! @} */ 2067 2068 /*! @name NCMR1 - Normal Conversion Enable For Standard Inputs */ 2069 /*! @{ */ 2070 2071 #define ADC_NCMR1_CH32_MASK (0x1U) 2072 #define ADC_NCMR1_CH32_SHIFT (0U) 2073 #define ADC_NCMR1_CH32_WIDTH (1U) 2074 #define ADC_NCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH32_SHIFT)) & ADC_NCMR1_CH32_MASK) 2075 2076 #define ADC_NCMR1_CH33_MASK (0x2U) 2077 #define ADC_NCMR1_CH33_SHIFT (1U) 2078 #define ADC_NCMR1_CH33_WIDTH (1U) 2079 #define ADC_NCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH33_SHIFT)) & ADC_NCMR1_CH33_MASK) 2080 2081 #define ADC_NCMR1_CH34_MASK (0x4U) 2082 #define ADC_NCMR1_CH34_SHIFT (2U) 2083 #define ADC_NCMR1_CH34_WIDTH (1U) 2084 #define ADC_NCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH34_SHIFT)) & ADC_NCMR1_CH34_MASK) 2085 2086 #define ADC_NCMR1_CH35_MASK (0x8U) 2087 #define ADC_NCMR1_CH35_SHIFT (3U) 2088 #define ADC_NCMR1_CH35_WIDTH (1U) 2089 #define ADC_NCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH35_SHIFT)) & ADC_NCMR1_CH35_MASK) 2090 2091 #define ADC_NCMR1_CH36_MASK (0x10U) 2092 #define ADC_NCMR1_CH36_SHIFT (4U) 2093 #define ADC_NCMR1_CH36_WIDTH (1U) 2094 #define ADC_NCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH36_SHIFT)) & ADC_NCMR1_CH36_MASK) 2095 2096 #define ADC_NCMR1_CH37_MASK (0x20U) 2097 #define ADC_NCMR1_CH37_SHIFT (5U) 2098 #define ADC_NCMR1_CH37_WIDTH (1U) 2099 #define ADC_NCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH37_SHIFT)) & ADC_NCMR1_CH37_MASK) 2100 2101 #define ADC_NCMR1_CH38_MASK (0x40U) 2102 #define ADC_NCMR1_CH38_SHIFT (6U) 2103 #define ADC_NCMR1_CH38_WIDTH (1U) 2104 #define ADC_NCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH38_SHIFT)) & ADC_NCMR1_CH38_MASK) 2105 2106 #define ADC_NCMR1_CH39_MASK (0x80U) 2107 #define ADC_NCMR1_CH39_SHIFT (7U) 2108 #define ADC_NCMR1_CH39_WIDTH (1U) 2109 #define ADC_NCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH39_SHIFT)) & ADC_NCMR1_CH39_MASK) 2110 2111 #define ADC_NCMR1_CH40_MASK (0x100U) 2112 #define ADC_NCMR1_CH40_SHIFT (8U) 2113 #define ADC_NCMR1_CH40_WIDTH (1U) 2114 #define ADC_NCMR1_CH40(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH40_SHIFT)) & ADC_NCMR1_CH40_MASK) 2115 2116 #define ADC_NCMR1_CH41_MASK (0x200U) 2117 #define ADC_NCMR1_CH41_SHIFT (9U) 2118 #define ADC_NCMR1_CH41_WIDTH (1U) 2119 #define ADC_NCMR1_CH41(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH41_SHIFT)) & ADC_NCMR1_CH41_MASK) 2120 2121 #define ADC_NCMR1_CH42_MASK (0x400U) 2122 #define ADC_NCMR1_CH42_SHIFT (10U) 2123 #define ADC_NCMR1_CH42_WIDTH (1U) 2124 #define ADC_NCMR1_CH42(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH42_SHIFT)) & ADC_NCMR1_CH42_MASK) 2125 2126 #define ADC_NCMR1_CH43_MASK (0x800U) 2127 #define ADC_NCMR1_CH43_SHIFT (11U) 2128 #define ADC_NCMR1_CH43_WIDTH (1U) 2129 #define ADC_NCMR1_CH43(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH43_SHIFT)) & ADC_NCMR1_CH43_MASK) 2130 2131 #define ADC_NCMR1_CH44_MASK (0x1000U) 2132 #define ADC_NCMR1_CH44_SHIFT (12U) 2133 #define ADC_NCMR1_CH44_WIDTH (1U) 2134 #define ADC_NCMR1_CH44(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH44_SHIFT)) & ADC_NCMR1_CH44_MASK) 2135 2136 #define ADC_NCMR1_CH45_MASK (0x2000U) 2137 #define ADC_NCMR1_CH45_SHIFT (13U) 2138 #define ADC_NCMR1_CH45_WIDTH (1U) 2139 #define ADC_NCMR1_CH45(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH45_SHIFT)) & ADC_NCMR1_CH45_MASK) 2140 2141 #define ADC_NCMR1_CH46_MASK (0x4000U) 2142 #define ADC_NCMR1_CH46_SHIFT (14U) 2143 #define ADC_NCMR1_CH46_WIDTH (1U) 2144 #define ADC_NCMR1_CH46(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH46_SHIFT)) & ADC_NCMR1_CH46_MASK) 2145 2146 #define ADC_NCMR1_CH47_MASK (0x8000U) 2147 #define ADC_NCMR1_CH47_SHIFT (15U) 2148 #define ADC_NCMR1_CH47_WIDTH (1U) 2149 #define ADC_NCMR1_CH47(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH47_SHIFT)) & ADC_NCMR1_CH47_MASK) 2150 2151 #define ADC_NCMR1_CH48_MASK (0x10000U) 2152 #define ADC_NCMR1_CH48_SHIFT (16U) 2153 #define ADC_NCMR1_CH48_WIDTH (1U) 2154 #define ADC_NCMR1_CH48(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH48_SHIFT)) & ADC_NCMR1_CH48_MASK) 2155 2156 #define ADC_NCMR1_CH49_MASK (0x20000U) 2157 #define ADC_NCMR1_CH49_SHIFT (17U) 2158 #define ADC_NCMR1_CH49_WIDTH (1U) 2159 #define ADC_NCMR1_CH49(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH49_SHIFT)) & ADC_NCMR1_CH49_MASK) 2160 2161 #define ADC_NCMR1_CH50_MASK (0x40000U) 2162 #define ADC_NCMR1_CH50_SHIFT (18U) 2163 #define ADC_NCMR1_CH50_WIDTH (1U) 2164 #define ADC_NCMR1_CH50(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH50_SHIFT)) & ADC_NCMR1_CH50_MASK) 2165 2166 #define ADC_NCMR1_CH51_MASK (0x80000U) 2167 #define ADC_NCMR1_CH51_SHIFT (19U) 2168 #define ADC_NCMR1_CH51_WIDTH (1U) 2169 #define ADC_NCMR1_CH51(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH51_SHIFT)) & ADC_NCMR1_CH51_MASK) 2170 2171 #define ADC_NCMR1_CH52_MASK (0x100000U) 2172 #define ADC_NCMR1_CH52_SHIFT (20U) 2173 #define ADC_NCMR1_CH52_WIDTH (1U) 2174 #define ADC_NCMR1_CH52(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH52_SHIFT)) & ADC_NCMR1_CH52_MASK) 2175 2176 #define ADC_NCMR1_CH53_MASK (0x200000U) 2177 #define ADC_NCMR1_CH53_SHIFT (21U) 2178 #define ADC_NCMR1_CH53_WIDTH (1U) 2179 #define ADC_NCMR1_CH53(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH53_SHIFT)) & ADC_NCMR1_CH53_MASK) 2180 2181 #define ADC_NCMR1_CH54_MASK (0x400000U) 2182 #define ADC_NCMR1_CH54_SHIFT (22U) 2183 #define ADC_NCMR1_CH54_WIDTH (1U) 2184 #define ADC_NCMR1_CH54(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH54_SHIFT)) & ADC_NCMR1_CH54_MASK) 2185 2186 #define ADC_NCMR1_CH55_MASK (0x800000U) 2187 #define ADC_NCMR1_CH55_SHIFT (23U) 2188 #define ADC_NCMR1_CH55_WIDTH (1U) 2189 #define ADC_NCMR1_CH55(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH55_SHIFT)) & ADC_NCMR1_CH55_MASK) 2190 /*! @} */ 2191 2192 /*! @name NCMR2 - Normal Conversion Enable For External Inputs */ 2193 /*! @{ */ 2194 2195 #define ADC_NCMR2_CH64_MASK (0x1U) 2196 #define ADC_NCMR2_CH64_SHIFT (0U) 2197 #define ADC_NCMR2_CH64_WIDTH (1U) 2198 #define ADC_NCMR2_CH64(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH64_SHIFT)) & ADC_NCMR2_CH64_MASK) 2199 2200 #define ADC_NCMR2_CH65_MASK (0x2U) 2201 #define ADC_NCMR2_CH65_SHIFT (1U) 2202 #define ADC_NCMR2_CH65_WIDTH (1U) 2203 #define ADC_NCMR2_CH65(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH65_SHIFT)) & ADC_NCMR2_CH65_MASK) 2204 2205 #define ADC_NCMR2_CH66_MASK (0x4U) 2206 #define ADC_NCMR2_CH66_SHIFT (2U) 2207 #define ADC_NCMR2_CH66_WIDTH (1U) 2208 #define ADC_NCMR2_CH66(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH66_SHIFT)) & ADC_NCMR2_CH66_MASK) 2209 2210 #define ADC_NCMR2_CH67_MASK (0x8U) 2211 #define ADC_NCMR2_CH67_SHIFT (3U) 2212 #define ADC_NCMR2_CH67_WIDTH (1U) 2213 #define ADC_NCMR2_CH67(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH67_SHIFT)) & ADC_NCMR2_CH67_MASK) 2214 2215 #define ADC_NCMR2_CH68_MASK (0x10U) 2216 #define ADC_NCMR2_CH68_SHIFT (4U) 2217 #define ADC_NCMR2_CH68_WIDTH (1U) 2218 #define ADC_NCMR2_CH68(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH68_SHIFT)) & ADC_NCMR2_CH68_MASK) 2219 2220 #define ADC_NCMR2_CH69_MASK (0x20U) 2221 #define ADC_NCMR2_CH69_SHIFT (5U) 2222 #define ADC_NCMR2_CH69_WIDTH (1U) 2223 #define ADC_NCMR2_CH69(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH69_SHIFT)) & ADC_NCMR2_CH69_MASK) 2224 2225 #define ADC_NCMR2_CH70_MASK (0x40U) 2226 #define ADC_NCMR2_CH70_SHIFT (6U) 2227 #define ADC_NCMR2_CH70_WIDTH (1U) 2228 #define ADC_NCMR2_CH70(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH70_SHIFT)) & ADC_NCMR2_CH70_MASK) 2229 2230 #define ADC_NCMR2_CH71_MASK (0x80U) 2231 #define ADC_NCMR2_CH71_SHIFT (7U) 2232 #define ADC_NCMR2_CH71_WIDTH (1U) 2233 #define ADC_NCMR2_CH71(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH71_SHIFT)) & ADC_NCMR2_CH71_MASK) 2234 2235 #define ADC_NCMR2_CH72_MASK (0x100U) 2236 #define ADC_NCMR2_CH72_SHIFT (8U) 2237 #define ADC_NCMR2_CH72_WIDTH (1U) 2238 #define ADC_NCMR2_CH72(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH72_SHIFT)) & ADC_NCMR2_CH72_MASK) 2239 2240 #define ADC_NCMR2_CH73_MASK (0x200U) 2241 #define ADC_NCMR2_CH73_SHIFT (9U) 2242 #define ADC_NCMR2_CH73_WIDTH (1U) 2243 #define ADC_NCMR2_CH73(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH73_SHIFT)) & ADC_NCMR2_CH73_MASK) 2244 2245 #define ADC_NCMR2_CH74_MASK (0x400U) 2246 #define ADC_NCMR2_CH74_SHIFT (10U) 2247 #define ADC_NCMR2_CH74_WIDTH (1U) 2248 #define ADC_NCMR2_CH74(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH74_SHIFT)) & ADC_NCMR2_CH74_MASK) 2249 2250 #define ADC_NCMR2_CH75_MASK (0x800U) 2251 #define ADC_NCMR2_CH75_SHIFT (11U) 2252 #define ADC_NCMR2_CH75_WIDTH (1U) 2253 #define ADC_NCMR2_CH75(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH75_SHIFT)) & ADC_NCMR2_CH75_MASK) 2254 2255 #define ADC_NCMR2_CH76_MASK (0x1000U) 2256 #define ADC_NCMR2_CH76_SHIFT (12U) 2257 #define ADC_NCMR2_CH76_WIDTH (1U) 2258 #define ADC_NCMR2_CH76(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH76_SHIFT)) & ADC_NCMR2_CH76_MASK) 2259 2260 #define ADC_NCMR2_CH77_MASK (0x2000U) 2261 #define ADC_NCMR2_CH77_SHIFT (13U) 2262 #define ADC_NCMR2_CH77_WIDTH (1U) 2263 #define ADC_NCMR2_CH77(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH77_SHIFT)) & ADC_NCMR2_CH77_MASK) 2264 2265 #define ADC_NCMR2_CH78_MASK (0x4000U) 2266 #define ADC_NCMR2_CH78_SHIFT (14U) 2267 #define ADC_NCMR2_CH78_WIDTH (1U) 2268 #define ADC_NCMR2_CH78(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH78_SHIFT)) & ADC_NCMR2_CH78_MASK) 2269 2270 #define ADC_NCMR2_CH79_MASK (0x8000U) 2271 #define ADC_NCMR2_CH79_SHIFT (15U) 2272 #define ADC_NCMR2_CH79_WIDTH (1U) 2273 #define ADC_NCMR2_CH79(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH79_SHIFT)) & ADC_NCMR2_CH79_MASK) 2274 2275 #define ADC_NCMR2_CH80_MASK (0x10000U) 2276 #define ADC_NCMR2_CH80_SHIFT (16U) 2277 #define ADC_NCMR2_CH80_WIDTH (1U) 2278 #define ADC_NCMR2_CH80(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH80_SHIFT)) & ADC_NCMR2_CH80_MASK) 2279 2280 #define ADC_NCMR2_CH81_MASK (0x20000U) 2281 #define ADC_NCMR2_CH81_SHIFT (17U) 2282 #define ADC_NCMR2_CH81_WIDTH (1U) 2283 #define ADC_NCMR2_CH81(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH81_SHIFT)) & ADC_NCMR2_CH81_MASK) 2284 2285 #define ADC_NCMR2_CH82_MASK (0x40000U) 2286 #define ADC_NCMR2_CH82_SHIFT (18U) 2287 #define ADC_NCMR2_CH82_WIDTH (1U) 2288 #define ADC_NCMR2_CH82(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH82_SHIFT)) & ADC_NCMR2_CH82_MASK) 2289 2290 #define ADC_NCMR2_CH83_MASK (0x80000U) 2291 #define ADC_NCMR2_CH83_SHIFT (19U) 2292 #define ADC_NCMR2_CH83_WIDTH (1U) 2293 #define ADC_NCMR2_CH83(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH83_SHIFT)) & ADC_NCMR2_CH83_MASK) 2294 2295 #define ADC_NCMR2_CH84_MASK (0x100000U) 2296 #define ADC_NCMR2_CH84_SHIFT (20U) 2297 #define ADC_NCMR2_CH84_WIDTH (1U) 2298 #define ADC_NCMR2_CH84(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH84_SHIFT)) & ADC_NCMR2_CH84_MASK) 2299 2300 #define ADC_NCMR2_CH85_MASK (0x200000U) 2301 #define ADC_NCMR2_CH85_SHIFT (21U) 2302 #define ADC_NCMR2_CH85_WIDTH (1U) 2303 #define ADC_NCMR2_CH85(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH85_SHIFT)) & ADC_NCMR2_CH85_MASK) 2304 2305 #define ADC_NCMR2_CH86_MASK (0x400000U) 2306 #define ADC_NCMR2_CH86_SHIFT (22U) 2307 #define ADC_NCMR2_CH86_WIDTH (1U) 2308 #define ADC_NCMR2_CH86(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH86_SHIFT)) & ADC_NCMR2_CH86_MASK) 2309 2310 #define ADC_NCMR2_CH87_MASK (0x800000U) 2311 #define ADC_NCMR2_CH87_SHIFT (23U) 2312 #define ADC_NCMR2_CH87_WIDTH (1U) 2313 #define ADC_NCMR2_CH87(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH87_SHIFT)) & ADC_NCMR2_CH87_MASK) 2314 2315 #define ADC_NCMR2_CH88_MASK (0x1000000U) 2316 #define ADC_NCMR2_CH88_SHIFT (24U) 2317 #define ADC_NCMR2_CH88_WIDTH (1U) 2318 #define ADC_NCMR2_CH88(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH88_SHIFT)) & ADC_NCMR2_CH88_MASK) 2319 2320 #define ADC_NCMR2_CH89_MASK (0x2000000U) 2321 #define ADC_NCMR2_CH89_SHIFT (25U) 2322 #define ADC_NCMR2_CH89_WIDTH (1U) 2323 #define ADC_NCMR2_CH89(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH89_SHIFT)) & ADC_NCMR2_CH89_MASK) 2324 2325 #define ADC_NCMR2_CH90_MASK (0x4000000U) 2326 #define ADC_NCMR2_CH90_SHIFT (26U) 2327 #define ADC_NCMR2_CH90_WIDTH (1U) 2328 #define ADC_NCMR2_CH90(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH90_SHIFT)) & ADC_NCMR2_CH90_MASK) 2329 2330 #define ADC_NCMR2_CH91_MASK (0x8000000U) 2331 #define ADC_NCMR2_CH91_SHIFT (27U) 2332 #define ADC_NCMR2_CH91_WIDTH (1U) 2333 #define ADC_NCMR2_CH91(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH91_SHIFT)) & ADC_NCMR2_CH91_MASK) 2334 2335 #define ADC_NCMR2_CH92_MASK (0x10000000U) 2336 #define ADC_NCMR2_CH92_SHIFT (28U) 2337 #define ADC_NCMR2_CH92_WIDTH (1U) 2338 #define ADC_NCMR2_CH92(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH92_SHIFT)) & ADC_NCMR2_CH92_MASK) 2339 2340 #define ADC_NCMR2_CH93_MASK (0x20000000U) 2341 #define ADC_NCMR2_CH93_SHIFT (29U) 2342 #define ADC_NCMR2_CH93_WIDTH (1U) 2343 #define ADC_NCMR2_CH93(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH93_SHIFT)) & ADC_NCMR2_CH93_MASK) 2344 2345 #define ADC_NCMR2_CH94_MASK (0x40000000U) 2346 #define ADC_NCMR2_CH94_SHIFT (30U) 2347 #define ADC_NCMR2_CH94_WIDTH (1U) 2348 #define ADC_NCMR2_CH94(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH94_SHIFT)) & ADC_NCMR2_CH94_MASK) 2349 2350 #define ADC_NCMR2_CH95_MASK (0x80000000U) 2351 #define ADC_NCMR2_CH95_SHIFT (31U) 2352 #define ADC_NCMR2_CH95_WIDTH (1U) 2353 #define ADC_NCMR2_CH95(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR2_CH95_SHIFT)) & ADC_NCMR2_CH95_MASK) 2354 /*! @} */ 2355 2356 /*! @name JCMR0 - Injected Conversion Enable For Precision Inputs */ 2357 /*! @{ */ 2358 2359 #define ADC_JCMR0_CH0_MASK (0x1U) 2360 #define ADC_JCMR0_CH0_SHIFT (0U) 2361 #define ADC_JCMR0_CH0_WIDTH (1U) 2362 #define ADC_JCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH0_SHIFT)) & ADC_JCMR0_CH0_MASK) 2363 2364 #define ADC_JCMR0_CH1_MASK (0x2U) 2365 #define ADC_JCMR0_CH1_SHIFT (1U) 2366 #define ADC_JCMR0_CH1_WIDTH (1U) 2367 #define ADC_JCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH1_SHIFT)) & ADC_JCMR0_CH1_MASK) 2368 2369 #define ADC_JCMR0_CH2_MASK (0x4U) 2370 #define ADC_JCMR0_CH2_SHIFT (2U) 2371 #define ADC_JCMR0_CH2_WIDTH (1U) 2372 #define ADC_JCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH2_SHIFT)) & ADC_JCMR0_CH2_MASK) 2373 2374 #define ADC_JCMR0_CH3_MASK (0x8U) 2375 #define ADC_JCMR0_CH3_SHIFT (3U) 2376 #define ADC_JCMR0_CH3_WIDTH (1U) 2377 #define ADC_JCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH3_SHIFT)) & ADC_JCMR0_CH3_MASK) 2378 2379 #define ADC_JCMR0_CH4_MASK (0x10U) 2380 #define ADC_JCMR0_CH4_SHIFT (4U) 2381 #define ADC_JCMR0_CH4_WIDTH (1U) 2382 #define ADC_JCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH4_SHIFT)) & ADC_JCMR0_CH4_MASK) 2383 2384 #define ADC_JCMR0_CH5_MASK (0x20U) 2385 #define ADC_JCMR0_CH5_SHIFT (5U) 2386 #define ADC_JCMR0_CH5_WIDTH (1U) 2387 #define ADC_JCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH5_SHIFT)) & ADC_JCMR0_CH5_MASK) 2388 2389 #define ADC_JCMR0_CH6_MASK (0x40U) 2390 #define ADC_JCMR0_CH6_SHIFT (6U) 2391 #define ADC_JCMR0_CH6_WIDTH (1U) 2392 #define ADC_JCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH6_SHIFT)) & ADC_JCMR0_CH6_MASK) 2393 2394 #define ADC_JCMR0_CH7_MASK (0x80U) 2395 #define ADC_JCMR0_CH7_SHIFT (7U) 2396 #define ADC_JCMR0_CH7_WIDTH (1U) 2397 #define ADC_JCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH7_SHIFT)) & ADC_JCMR0_CH7_MASK) 2398 /*! @} */ 2399 2400 /*! @name JCMR1 - Injected Conversion Enable For Standard Inputs */ 2401 /*! @{ */ 2402 2403 #define ADC_JCMR1_CH32_MASK (0x1U) 2404 #define ADC_JCMR1_CH32_SHIFT (0U) 2405 #define ADC_JCMR1_CH32_WIDTH (1U) 2406 #define ADC_JCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH32_SHIFT)) & ADC_JCMR1_CH32_MASK) 2407 2408 #define ADC_JCMR1_CH33_MASK (0x2U) 2409 #define ADC_JCMR1_CH33_SHIFT (1U) 2410 #define ADC_JCMR1_CH33_WIDTH (1U) 2411 #define ADC_JCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH33_SHIFT)) & ADC_JCMR1_CH33_MASK) 2412 2413 #define ADC_JCMR1_CH34_MASK (0x4U) 2414 #define ADC_JCMR1_CH34_SHIFT (2U) 2415 #define ADC_JCMR1_CH34_WIDTH (1U) 2416 #define ADC_JCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH34_SHIFT)) & ADC_JCMR1_CH34_MASK) 2417 2418 #define ADC_JCMR1_CH35_MASK (0x8U) 2419 #define ADC_JCMR1_CH35_SHIFT (3U) 2420 #define ADC_JCMR1_CH35_WIDTH (1U) 2421 #define ADC_JCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH35_SHIFT)) & ADC_JCMR1_CH35_MASK) 2422 2423 #define ADC_JCMR1_CH36_MASK (0x10U) 2424 #define ADC_JCMR1_CH36_SHIFT (4U) 2425 #define ADC_JCMR1_CH36_WIDTH (1U) 2426 #define ADC_JCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH36_SHIFT)) & ADC_JCMR1_CH36_MASK) 2427 2428 #define ADC_JCMR1_CH37_MASK (0x20U) 2429 #define ADC_JCMR1_CH37_SHIFT (5U) 2430 #define ADC_JCMR1_CH37_WIDTH (1U) 2431 #define ADC_JCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH37_SHIFT)) & ADC_JCMR1_CH37_MASK) 2432 2433 #define ADC_JCMR1_CH38_MASK (0x40U) 2434 #define ADC_JCMR1_CH38_SHIFT (6U) 2435 #define ADC_JCMR1_CH38_WIDTH (1U) 2436 #define ADC_JCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH38_SHIFT)) & ADC_JCMR1_CH38_MASK) 2437 2438 #define ADC_JCMR1_CH39_MASK (0x80U) 2439 #define ADC_JCMR1_CH39_SHIFT (7U) 2440 #define ADC_JCMR1_CH39_WIDTH (1U) 2441 #define ADC_JCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH39_SHIFT)) & ADC_JCMR1_CH39_MASK) 2442 2443 #define ADC_JCMR1_CH40_MASK (0x100U) 2444 #define ADC_JCMR1_CH40_SHIFT (8U) 2445 #define ADC_JCMR1_CH40_WIDTH (1U) 2446 #define ADC_JCMR1_CH40(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH40_SHIFT)) & ADC_JCMR1_CH40_MASK) 2447 2448 #define ADC_JCMR1_CH41_MASK (0x200U) 2449 #define ADC_JCMR1_CH41_SHIFT (9U) 2450 #define ADC_JCMR1_CH41_WIDTH (1U) 2451 #define ADC_JCMR1_CH41(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH41_SHIFT)) & ADC_JCMR1_CH41_MASK) 2452 2453 #define ADC_JCMR1_CH42_MASK (0x400U) 2454 #define ADC_JCMR1_CH42_SHIFT (10U) 2455 #define ADC_JCMR1_CH42_WIDTH (1U) 2456 #define ADC_JCMR1_CH42(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH42_SHIFT)) & ADC_JCMR1_CH42_MASK) 2457 2458 #define ADC_JCMR1_CH43_MASK (0x800U) 2459 #define ADC_JCMR1_CH43_SHIFT (11U) 2460 #define ADC_JCMR1_CH43_WIDTH (1U) 2461 #define ADC_JCMR1_CH43(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH43_SHIFT)) & ADC_JCMR1_CH43_MASK) 2462 2463 #define ADC_JCMR1_CH44_MASK (0x1000U) 2464 #define ADC_JCMR1_CH44_SHIFT (12U) 2465 #define ADC_JCMR1_CH44_WIDTH (1U) 2466 #define ADC_JCMR1_CH44(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH44_SHIFT)) & ADC_JCMR1_CH44_MASK) 2467 2468 #define ADC_JCMR1_CH45_MASK (0x2000U) 2469 #define ADC_JCMR1_CH45_SHIFT (13U) 2470 #define ADC_JCMR1_CH45_WIDTH (1U) 2471 #define ADC_JCMR1_CH45(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH45_SHIFT)) & ADC_JCMR1_CH45_MASK) 2472 2473 #define ADC_JCMR1_CH46_MASK (0x4000U) 2474 #define ADC_JCMR1_CH46_SHIFT (14U) 2475 #define ADC_JCMR1_CH46_WIDTH (1U) 2476 #define ADC_JCMR1_CH46(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH46_SHIFT)) & ADC_JCMR1_CH46_MASK) 2477 2478 #define ADC_JCMR1_CH47_MASK (0x8000U) 2479 #define ADC_JCMR1_CH47_SHIFT (15U) 2480 #define ADC_JCMR1_CH47_WIDTH (1U) 2481 #define ADC_JCMR1_CH47(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH47_SHIFT)) & ADC_JCMR1_CH47_MASK) 2482 2483 #define ADC_JCMR1_CH48_MASK (0x10000U) 2484 #define ADC_JCMR1_CH48_SHIFT (16U) 2485 #define ADC_JCMR1_CH48_WIDTH (1U) 2486 #define ADC_JCMR1_CH48(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH48_SHIFT)) & ADC_JCMR1_CH48_MASK) 2487 2488 #define ADC_JCMR1_CH49_MASK (0x20000U) 2489 #define ADC_JCMR1_CH49_SHIFT (17U) 2490 #define ADC_JCMR1_CH49_WIDTH (1U) 2491 #define ADC_JCMR1_CH49(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH49_SHIFT)) & ADC_JCMR1_CH49_MASK) 2492 2493 #define ADC_JCMR1_CH50_MASK (0x40000U) 2494 #define ADC_JCMR1_CH50_SHIFT (18U) 2495 #define ADC_JCMR1_CH50_WIDTH (1U) 2496 #define ADC_JCMR1_CH50(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH50_SHIFT)) & ADC_JCMR1_CH50_MASK) 2497 2498 #define ADC_JCMR1_CH51_MASK (0x80000U) 2499 #define ADC_JCMR1_CH51_SHIFT (19U) 2500 #define ADC_JCMR1_CH51_WIDTH (1U) 2501 #define ADC_JCMR1_CH51(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH51_SHIFT)) & ADC_JCMR1_CH51_MASK) 2502 2503 #define ADC_JCMR1_CH52_MASK (0x100000U) 2504 #define ADC_JCMR1_CH52_SHIFT (20U) 2505 #define ADC_JCMR1_CH52_WIDTH (1U) 2506 #define ADC_JCMR1_CH52(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH52_SHIFT)) & ADC_JCMR1_CH52_MASK) 2507 2508 #define ADC_JCMR1_CH53_MASK (0x200000U) 2509 #define ADC_JCMR1_CH53_SHIFT (21U) 2510 #define ADC_JCMR1_CH53_WIDTH (1U) 2511 #define ADC_JCMR1_CH53(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH53_SHIFT)) & ADC_JCMR1_CH53_MASK) 2512 2513 #define ADC_JCMR1_CH54_MASK (0x400000U) 2514 #define ADC_JCMR1_CH54_SHIFT (22U) 2515 #define ADC_JCMR1_CH54_WIDTH (1U) 2516 #define ADC_JCMR1_CH54(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH54_SHIFT)) & ADC_JCMR1_CH54_MASK) 2517 2518 #define ADC_JCMR1_CH55_MASK (0x800000U) 2519 #define ADC_JCMR1_CH55_SHIFT (23U) 2520 #define ADC_JCMR1_CH55_WIDTH (1U) 2521 #define ADC_JCMR1_CH55(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH55_SHIFT)) & ADC_JCMR1_CH55_MASK) 2522 /*! @} */ 2523 2524 /*! @name JCMR2 - Injected Conversion Enable For External Inputs */ 2525 /*! @{ */ 2526 2527 #define ADC_JCMR2_CH64_MASK (0x1U) 2528 #define ADC_JCMR2_CH64_SHIFT (0U) 2529 #define ADC_JCMR2_CH64_WIDTH (1U) 2530 #define ADC_JCMR2_CH64(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH64_SHIFT)) & ADC_JCMR2_CH64_MASK) 2531 2532 #define ADC_JCMR2_CH65_MASK (0x2U) 2533 #define ADC_JCMR2_CH65_SHIFT (1U) 2534 #define ADC_JCMR2_CH65_WIDTH (1U) 2535 #define ADC_JCMR2_CH65(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH65_SHIFT)) & ADC_JCMR2_CH65_MASK) 2536 2537 #define ADC_JCMR2_CH66_MASK (0x4U) 2538 #define ADC_JCMR2_CH66_SHIFT (2U) 2539 #define ADC_JCMR2_CH66_WIDTH (1U) 2540 #define ADC_JCMR2_CH66(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH66_SHIFT)) & ADC_JCMR2_CH66_MASK) 2541 2542 #define ADC_JCMR2_CH67_MASK (0x8U) 2543 #define ADC_JCMR2_CH67_SHIFT (3U) 2544 #define ADC_JCMR2_CH67_WIDTH (1U) 2545 #define ADC_JCMR2_CH67(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH67_SHIFT)) & ADC_JCMR2_CH67_MASK) 2546 2547 #define ADC_JCMR2_CH68_MASK (0x10U) 2548 #define ADC_JCMR2_CH68_SHIFT (4U) 2549 #define ADC_JCMR2_CH68_WIDTH (1U) 2550 #define ADC_JCMR2_CH68(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH68_SHIFT)) & ADC_JCMR2_CH68_MASK) 2551 2552 #define ADC_JCMR2_CH69_MASK (0x20U) 2553 #define ADC_JCMR2_CH69_SHIFT (5U) 2554 #define ADC_JCMR2_CH69_WIDTH (1U) 2555 #define ADC_JCMR2_CH69(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH69_SHIFT)) & ADC_JCMR2_CH69_MASK) 2556 2557 #define ADC_JCMR2_CH70_MASK (0x40U) 2558 #define ADC_JCMR2_CH70_SHIFT (6U) 2559 #define ADC_JCMR2_CH70_WIDTH (1U) 2560 #define ADC_JCMR2_CH70(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH70_SHIFT)) & ADC_JCMR2_CH70_MASK) 2561 2562 #define ADC_JCMR2_CH71_MASK (0x80U) 2563 #define ADC_JCMR2_CH71_SHIFT (7U) 2564 #define ADC_JCMR2_CH71_WIDTH (1U) 2565 #define ADC_JCMR2_CH71(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH71_SHIFT)) & ADC_JCMR2_CH71_MASK) 2566 2567 #define ADC_JCMR2_CH72_MASK (0x100U) 2568 #define ADC_JCMR2_CH72_SHIFT (8U) 2569 #define ADC_JCMR2_CH72_WIDTH (1U) 2570 #define ADC_JCMR2_CH72(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH72_SHIFT)) & ADC_JCMR2_CH72_MASK) 2571 2572 #define ADC_JCMR2_CH73_MASK (0x200U) 2573 #define ADC_JCMR2_CH73_SHIFT (9U) 2574 #define ADC_JCMR2_CH73_WIDTH (1U) 2575 #define ADC_JCMR2_CH73(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH73_SHIFT)) & ADC_JCMR2_CH73_MASK) 2576 2577 #define ADC_JCMR2_CH74_MASK (0x400U) 2578 #define ADC_JCMR2_CH74_SHIFT (10U) 2579 #define ADC_JCMR2_CH74_WIDTH (1U) 2580 #define ADC_JCMR2_CH74(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH74_SHIFT)) & ADC_JCMR2_CH74_MASK) 2581 2582 #define ADC_JCMR2_CH75_MASK (0x800U) 2583 #define ADC_JCMR2_CH75_SHIFT (11U) 2584 #define ADC_JCMR2_CH75_WIDTH (1U) 2585 #define ADC_JCMR2_CH75(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH75_SHIFT)) & ADC_JCMR2_CH75_MASK) 2586 2587 #define ADC_JCMR2_CH76_MASK (0x1000U) 2588 #define ADC_JCMR2_CH76_SHIFT (12U) 2589 #define ADC_JCMR2_CH76_WIDTH (1U) 2590 #define ADC_JCMR2_CH76(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH76_SHIFT)) & ADC_JCMR2_CH76_MASK) 2591 2592 #define ADC_JCMR2_CH77_MASK (0x2000U) 2593 #define ADC_JCMR2_CH77_SHIFT (13U) 2594 #define ADC_JCMR2_CH77_WIDTH (1U) 2595 #define ADC_JCMR2_CH77(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH77_SHIFT)) & ADC_JCMR2_CH77_MASK) 2596 2597 #define ADC_JCMR2_CH78_MASK (0x4000U) 2598 #define ADC_JCMR2_CH78_SHIFT (14U) 2599 #define ADC_JCMR2_CH78_WIDTH (1U) 2600 #define ADC_JCMR2_CH78(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH78_SHIFT)) & ADC_JCMR2_CH78_MASK) 2601 2602 #define ADC_JCMR2_CH79_MASK (0x8000U) 2603 #define ADC_JCMR2_CH79_SHIFT (15U) 2604 #define ADC_JCMR2_CH79_WIDTH (1U) 2605 #define ADC_JCMR2_CH79(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH79_SHIFT)) & ADC_JCMR2_CH79_MASK) 2606 2607 #define ADC_JCMR2_CH80_MASK (0x10000U) 2608 #define ADC_JCMR2_CH80_SHIFT (16U) 2609 #define ADC_JCMR2_CH80_WIDTH (1U) 2610 #define ADC_JCMR2_CH80(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH80_SHIFT)) & ADC_JCMR2_CH80_MASK) 2611 2612 #define ADC_JCMR2_CH81_MASK (0x20000U) 2613 #define ADC_JCMR2_CH81_SHIFT (17U) 2614 #define ADC_JCMR2_CH81_WIDTH (1U) 2615 #define ADC_JCMR2_CH81(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH81_SHIFT)) & ADC_JCMR2_CH81_MASK) 2616 2617 #define ADC_JCMR2_CH82_MASK (0x40000U) 2618 #define ADC_JCMR2_CH82_SHIFT (18U) 2619 #define ADC_JCMR2_CH82_WIDTH (1U) 2620 #define ADC_JCMR2_CH82(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH82_SHIFT)) & ADC_JCMR2_CH82_MASK) 2621 2622 #define ADC_JCMR2_CH83_MASK (0x80000U) 2623 #define ADC_JCMR2_CH83_SHIFT (19U) 2624 #define ADC_JCMR2_CH83_WIDTH (1U) 2625 #define ADC_JCMR2_CH83(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH83_SHIFT)) & ADC_JCMR2_CH83_MASK) 2626 2627 #define ADC_JCMR2_CH84_MASK (0x100000U) 2628 #define ADC_JCMR2_CH84_SHIFT (20U) 2629 #define ADC_JCMR2_CH84_WIDTH (1U) 2630 #define ADC_JCMR2_CH84(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH84_SHIFT)) & ADC_JCMR2_CH84_MASK) 2631 2632 #define ADC_JCMR2_CH85_MASK (0x200000U) 2633 #define ADC_JCMR2_CH85_SHIFT (21U) 2634 #define ADC_JCMR2_CH85_WIDTH (1U) 2635 #define ADC_JCMR2_CH85(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH85_SHIFT)) & ADC_JCMR2_CH85_MASK) 2636 2637 #define ADC_JCMR2_CH86_MASK (0x400000U) 2638 #define ADC_JCMR2_CH86_SHIFT (22U) 2639 #define ADC_JCMR2_CH86_WIDTH (1U) 2640 #define ADC_JCMR2_CH86(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH86_SHIFT)) & ADC_JCMR2_CH86_MASK) 2641 2642 #define ADC_JCMR2_CH87_MASK (0x800000U) 2643 #define ADC_JCMR2_CH87_SHIFT (23U) 2644 #define ADC_JCMR2_CH87_WIDTH (1U) 2645 #define ADC_JCMR2_CH87(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH87_SHIFT)) & ADC_JCMR2_CH87_MASK) 2646 2647 #define ADC_JCMR2_CH88_MASK (0x1000000U) 2648 #define ADC_JCMR2_CH88_SHIFT (24U) 2649 #define ADC_JCMR2_CH88_WIDTH (1U) 2650 #define ADC_JCMR2_CH88(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH88_SHIFT)) & ADC_JCMR2_CH88_MASK) 2651 2652 #define ADC_JCMR2_CH89_MASK (0x2000000U) 2653 #define ADC_JCMR2_CH89_SHIFT (25U) 2654 #define ADC_JCMR2_CH89_WIDTH (1U) 2655 #define ADC_JCMR2_CH89(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH89_SHIFT)) & ADC_JCMR2_CH89_MASK) 2656 2657 #define ADC_JCMR2_CH90_MASK (0x4000000U) 2658 #define ADC_JCMR2_CH90_SHIFT (26U) 2659 #define ADC_JCMR2_CH90_WIDTH (1U) 2660 #define ADC_JCMR2_CH90(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH90_SHIFT)) & ADC_JCMR2_CH90_MASK) 2661 2662 #define ADC_JCMR2_CH91_MASK (0x8000000U) 2663 #define ADC_JCMR2_CH91_SHIFT (27U) 2664 #define ADC_JCMR2_CH91_WIDTH (1U) 2665 #define ADC_JCMR2_CH91(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH91_SHIFT)) & ADC_JCMR2_CH91_MASK) 2666 2667 #define ADC_JCMR2_CH92_MASK (0x10000000U) 2668 #define ADC_JCMR2_CH92_SHIFT (28U) 2669 #define ADC_JCMR2_CH92_WIDTH (1U) 2670 #define ADC_JCMR2_CH92(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH92_SHIFT)) & ADC_JCMR2_CH92_MASK) 2671 2672 #define ADC_JCMR2_CH93_MASK (0x20000000U) 2673 #define ADC_JCMR2_CH93_SHIFT (29U) 2674 #define ADC_JCMR2_CH93_WIDTH (1U) 2675 #define ADC_JCMR2_CH93(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH93_SHIFT)) & ADC_JCMR2_CH93_MASK) 2676 2677 #define ADC_JCMR2_CH94_MASK (0x40000000U) 2678 #define ADC_JCMR2_CH94_SHIFT (30U) 2679 #define ADC_JCMR2_CH94_WIDTH (1U) 2680 #define ADC_JCMR2_CH94(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH94_SHIFT)) & ADC_JCMR2_CH94_MASK) 2681 2682 #define ADC_JCMR2_CH95_MASK (0x80000000U) 2683 #define ADC_JCMR2_CH95_SHIFT (31U) 2684 #define ADC_JCMR2_CH95_WIDTH (1U) 2685 #define ADC_JCMR2_CH95(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR2_CH95_SHIFT)) & ADC_JCMR2_CH95_MASK) 2686 /*! @} */ 2687 2688 /*! @name DSDR - Delay Start Of Data Conversion */ 2689 /*! @{ */ 2690 2691 #define ADC_DSDR_DSD_MASK (0xFFFFU) 2692 #define ADC_DSDR_DSD_SHIFT (0U) 2693 #define ADC_DSDR_DSD_WIDTH (16U) 2694 #define ADC_DSDR_DSD(x) (((uint32_t)(((uint32_t)(x)) << ADC_DSDR_DSD_SHIFT)) & ADC_DSDR_DSD_MASK) 2695 /*! @} */ 2696 2697 /*! @name PDEDR - Power Down Exit Delay */ 2698 /*! @{ */ 2699 2700 #define ADC_PDEDR_PDED_MASK (0xFFU) 2701 #define ADC_PDEDR_PDED_SHIFT (0U) 2702 #define ADC_PDEDR_PDED_WIDTH (8U) 2703 #define ADC_PDEDR_PDED(x) (((uint32_t)(((uint32_t)(x)) << ADC_PDEDR_PDED_SHIFT)) & ADC_PDEDR_PDED_MASK) 2704 /*! @} */ 2705 2706 /*! @name PCDR - Precision Input n Conversion Data */ 2707 /*! @{ */ 2708 2709 #define ADC_PCDR_CDATA_MASK (0xFFFFU) 2710 #define ADC_PCDR_CDATA_SHIFT (0U) 2711 #define ADC_PCDR_CDATA_WIDTH (16U) 2712 #define ADC_PCDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_CDATA_SHIFT)) & ADC_PCDR_CDATA_MASK) 2713 2714 #define ADC_PCDR_RESULT_MASK (0x30000U) 2715 #define ADC_PCDR_RESULT_SHIFT (16U) 2716 #define ADC_PCDR_RESULT_WIDTH (2U) 2717 #define ADC_PCDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_RESULT_SHIFT)) & ADC_PCDR_RESULT_MASK) 2718 2719 #define ADC_PCDR_OVERW_MASK (0x40000U) 2720 #define ADC_PCDR_OVERW_SHIFT (18U) 2721 #define ADC_PCDR_OVERW_WIDTH (1U) 2722 #define ADC_PCDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_OVERW_SHIFT)) & ADC_PCDR_OVERW_MASK) 2723 2724 #define ADC_PCDR_VALID_MASK (0x80000U) 2725 #define ADC_PCDR_VALID_SHIFT (19U) 2726 #define ADC_PCDR_VALID_WIDTH (1U) 2727 #define ADC_PCDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_VALID_SHIFT)) & ADC_PCDR_VALID_MASK) 2728 /*! @} */ 2729 2730 /*! @name ICDR - Standard Input n Conversion Data */ 2731 /*! @{ */ 2732 2733 #define ADC_ICDR_CDATA_MASK (0xFFFFU) 2734 #define ADC_ICDR_CDATA_SHIFT (0U) 2735 #define ADC_ICDR_CDATA_WIDTH (16U) 2736 #define ADC_ICDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_CDATA_SHIFT)) & ADC_ICDR_CDATA_MASK) 2737 2738 #define ADC_ICDR_RESULT_MASK (0x30000U) 2739 #define ADC_ICDR_RESULT_SHIFT (16U) 2740 #define ADC_ICDR_RESULT_WIDTH (2U) 2741 #define ADC_ICDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_RESULT_SHIFT)) & ADC_ICDR_RESULT_MASK) 2742 2743 #define ADC_ICDR_OVERW_MASK (0x40000U) 2744 #define ADC_ICDR_OVERW_SHIFT (18U) 2745 #define ADC_ICDR_OVERW_WIDTH (1U) 2746 #define ADC_ICDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_OVERW_SHIFT)) & ADC_ICDR_OVERW_MASK) 2747 2748 #define ADC_ICDR_VALID_MASK (0x80000U) 2749 #define ADC_ICDR_VALID_SHIFT (19U) 2750 #define ADC_ICDR_VALID_WIDTH (1U) 2751 #define ADC_ICDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_VALID_SHIFT)) & ADC_ICDR_VALID_MASK) 2752 /*! @} */ 2753 2754 /*! @name ECDR - External Input n Conversion Data */ 2755 /*! @{ */ 2756 2757 #define ADC_ECDR_CDATA_MASK (0xFFFFU) 2758 #define ADC_ECDR_CDATA_SHIFT (0U) 2759 #define ADC_ECDR_CDATA_WIDTH (16U) 2760 #define ADC_ECDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ECDR_CDATA_SHIFT)) & ADC_ECDR_CDATA_MASK) 2761 2762 #define ADC_ECDR_RESULT_MASK (0x30000U) 2763 #define ADC_ECDR_RESULT_SHIFT (16U) 2764 #define ADC_ECDR_RESULT_WIDTH (2U) 2765 #define ADC_ECDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ECDR_RESULT_SHIFT)) & ADC_ECDR_RESULT_MASK) 2766 2767 #define ADC_ECDR_OVERW_MASK (0x40000U) 2768 #define ADC_ECDR_OVERW_SHIFT (18U) 2769 #define ADC_ECDR_OVERW_WIDTH (1U) 2770 #define ADC_ECDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ECDR_OVERW_SHIFT)) & ADC_ECDR_OVERW_MASK) 2771 2772 #define ADC_ECDR_VALID_MASK (0x80000U) 2773 #define ADC_ECDR_VALID_SHIFT (19U) 2774 #define ADC_ECDR_VALID_WIDTH (1U) 2775 #define ADC_ECDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ECDR_VALID_SHIFT)) & ADC_ECDR_VALID_MASK) 2776 /*! @} */ 2777 2778 /*! @name CWSELRPI - Channel Analog Watchdog Select For Precision Inputs */ 2779 /*! @{ */ 2780 2781 #define ADC_CWSELRPI_WSEL_SI0_0_MASK (0x3U) 2782 #define ADC_CWSELRPI_WSEL_SI0_0_SHIFT (0U) 2783 #define ADC_CWSELRPI_WSEL_SI0_0_WIDTH (2U) 2784 #define ADC_CWSELRPI_WSEL_SI0_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_0_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_0_MASK) 2785 2786 #define ADC_CWSELRPI_WSEL_SI0_1_MASK (0x30U) 2787 #define ADC_CWSELRPI_WSEL_SI0_1_SHIFT (4U) 2788 #define ADC_CWSELRPI_WSEL_SI0_1_WIDTH (2U) 2789 #define ADC_CWSELRPI_WSEL_SI0_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_1_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_1_MASK) 2790 2791 #define ADC_CWSELRPI_WSEL_SI0_2_MASK (0x300U) 2792 #define ADC_CWSELRPI_WSEL_SI0_2_SHIFT (8U) 2793 #define ADC_CWSELRPI_WSEL_SI0_2_WIDTH (2U) 2794 #define ADC_CWSELRPI_WSEL_SI0_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_2_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_2_MASK) 2795 2796 #define ADC_CWSELRPI_WSEL_SI0_3_MASK (0x3000U) 2797 #define ADC_CWSELRPI_WSEL_SI0_3_SHIFT (12U) 2798 #define ADC_CWSELRPI_WSEL_SI0_3_WIDTH (2U) 2799 #define ADC_CWSELRPI_WSEL_SI0_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_3_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_3_MASK) 2800 2801 #define ADC_CWSELRPI_WSEL_SI0_4_MASK (0x30000U) 2802 #define ADC_CWSELRPI_WSEL_SI0_4_SHIFT (16U) 2803 #define ADC_CWSELRPI_WSEL_SI0_4_WIDTH (2U) 2804 #define ADC_CWSELRPI_WSEL_SI0_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_4_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_4_MASK) 2805 2806 #define ADC_CWSELRPI_WSEL_SI0_5_MASK (0x300000U) 2807 #define ADC_CWSELRPI_WSEL_SI0_5_SHIFT (20U) 2808 #define ADC_CWSELRPI_WSEL_SI0_5_WIDTH (2U) 2809 #define ADC_CWSELRPI_WSEL_SI0_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_5_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_5_MASK) 2810 2811 #define ADC_CWSELRPI_WSEL_SI0_6_MASK (0x3000000U) 2812 #define ADC_CWSELRPI_WSEL_SI0_6_SHIFT (24U) 2813 #define ADC_CWSELRPI_WSEL_SI0_6_WIDTH (2U) 2814 #define ADC_CWSELRPI_WSEL_SI0_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_6_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_6_MASK) 2815 2816 #define ADC_CWSELRPI_WSEL_SI0_7_MASK (0x30000000U) 2817 #define ADC_CWSELRPI_WSEL_SI0_7_SHIFT (28U) 2818 #define ADC_CWSELRPI_WSEL_SI0_7_WIDTH (2U) 2819 #define ADC_CWSELRPI_WSEL_SI0_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRPI_WSEL_SI0_7_SHIFT)) & ADC_CWSELRPI_WSEL_SI0_7_MASK) 2820 /*! @} */ 2821 2822 /*! @name CWSELRSI - Channel Analog Watchdog Select For Standard Inputs */ 2823 /*! @{ */ 2824 2825 #define ADC_CWSELRSI_WSEL_SI0_0_MASK (0x3U) 2826 #define ADC_CWSELRSI_WSEL_SI0_0_SHIFT (0U) 2827 #define ADC_CWSELRSI_WSEL_SI0_0_WIDTH (2U) 2828 #define ADC_CWSELRSI_WSEL_SI0_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI0_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI0_0_MASK) 2829 2830 #define ADC_CWSELRSI_WSEL_SI0_1_MASK (0x3U) 2831 #define ADC_CWSELRSI_WSEL_SI0_1_SHIFT (0U) 2832 #define ADC_CWSELRSI_WSEL_SI0_1_WIDTH (2U) 2833 #define ADC_CWSELRSI_WSEL_SI0_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI0_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI0_1_MASK) 2834 2835 #define ADC_CWSELRSI_WSEL_SI0_2_MASK (0x3U) 2836 #define ADC_CWSELRSI_WSEL_SI0_2_SHIFT (0U) 2837 #define ADC_CWSELRSI_WSEL_SI0_2_WIDTH (2U) 2838 #define ADC_CWSELRSI_WSEL_SI0_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI0_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI0_2_MASK) 2839 2840 #define ADC_CWSELRSI_WSEL_SI1_0_MASK (0x30U) 2841 #define ADC_CWSELRSI_WSEL_SI1_0_SHIFT (4U) 2842 #define ADC_CWSELRSI_WSEL_SI1_0_WIDTH (2U) 2843 #define ADC_CWSELRSI_WSEL_SI1_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI1_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI1_0_MASK) 2844 2845 #define ADC_CWSELRSI_WSEL_SI1_1_MASK (0x30U) 2846 #define ADC_CWSELRSI_WSEL_SI1_1_SHIFT (4U) 2847 #define ADC_CWSELRSI_WSEL_SI1_1_WIDTH (2U) 2848 #define ADC_CWSELRSI_WSEL_SI1_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI1_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI1_1_MASK) 2849 2850 #define ADC_CWSELRSI_WSEL_SI1_2_MASK (0x30U) 2851 #define ADC_CWSELRSI_WSEL_SI1_2_SHIFT (4U) 2852 #define ADC_CWSELRSI_WSEL_SI1_2_WIDTH (2U) 2853 #define ADC_CWSELRSI_WSEL_SI1_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI1_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI1_2_MASK) 2854 2855 #define ADC_CWSELRSI_WSEL_SI2_0_MASK (0x300U) 2856 #define ADC_CWSELRSI_WSEL_SI2_0_SHIFT (8U) 2857 #define ADC_CWSELRSI_WSEL_SI2_0_WIDTH (2U) 2858 #define ADC_CWSELRSI_WSEL_SI2_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI2_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI2_0_MASK) 2859 2860 #define ADC_CWSELRSI_WSEL_SI2_1_MASK (0x300U) 2861 #define ADC_CWSELRSI_WSEL_SI2_1_SHIFT (8U) 2862 #define ADC_CWSELRSI_WSEL_SI2_1_WIDTH (2U) 2863 #define ADC_CWSELRSI_WSEL_SI2_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI2_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI2_1_MASK) 2864 2865 #define ADC_CWSELRSI_WSEL_SI2_2_MASK (0x300U) 2866 #define ADC_CWSELRSI_WSEL_SI2_2_SHIFT (8U) 2867 #define ADC_CWSELRSI_WSEL_SI2_2_WIDTH (2U) 2868 #define ADC_CWSELRSI_WSEL_SI2_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI2_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI2_2_MASK) 2869 2870 #define ADC_CWSELRSI_WSEL_SI3_0_MASK (0x3000U) 2871 #define ADC_CWSELRSI_WSEL_SI3_0_SHIFT (12U) 2872 #define ADC_CWSELRSI_WSEL_SI3_0_WIDTH (2U) 2873 #define ADC_CWSELRSI_WSEL_SI3_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI3_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI3_0_MASK) 2874 2875 #define ADC_CWSELRSI_WSEL_SI3_1_MASK (0x3000U) 2876 #define ADC_CWSELRSI_WSEL_SI3_1_SHIFT (12U) 2877 #define ADC_CWSELRSI_WSEL_SI3_1_WIDTH (2U) 2878 #define ADC_CWSELRSI_WSEL_SI3_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI3_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI3_1_MASK) 2879 2880 #define ADC_CWSELRSI_WSEL_SI3_2_MASK (0x3000U) 2881 #define ADC_CWSELRSI_WSEL_SI3_2_SHIFT (12U) 2882 #define ADC_CWSELRSI_WSEL_SI3_2_WIDTH (2U) 2883 #define ADC_CWSELRSI_WSEL_SI3_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI3_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI3_2_MASK) 2884 2885 #define ADC_CWSELRSI_WSEL_SI4_0_MASK (0x30000U) 2886 #define ADC_CWSELRSI_WSEL_SI4_0_SHIFT (16U) 2887 #define ADC_CWSELRSI_WSEL_SI4_0_WIDTH (2U) 2888 #define ADC_CWSELRSI_WSEL_SI4_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI4_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI4_0_MASK) 2889 2890 #define ADC_CWSELRSI_WSEL_SI4_1_MASK (0x30000U) 2891 #define ADC_CWSELRSI_WSEL_SI4_1_SHIFT (16U) 2892 #define ADC_CWSELRSI_WSEL_SI4_1_WIDTH (2U) 2893 #define ADC_CWSELRSI_WSEL_SI4_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI4_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI4_1_MASK) 2894 2895 #define ADC_CWSELRSI_WSEL_SI4_2_MASK (0x30000U) 2896 #define ADC_CWSELRSI_WSEL_SI4_2_SHIFT (16U) 2897 #define ADC_CWSELRSI_WSEL_SI4_2_WIDTH (2U) 2898 #define ADC_CWSELRSI_WSEL_SI4_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI4_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI4_2_MASK) 2899 2900 #define ADC_CWSELRSI_WSEL_SI5_0_MASK (0x300000U) 2901 #define ADC_CWSELRSI_WSEL_SI5_0_SHIFT (20U) 2902 #define ADC_CWSELRSI_WSEL_SI5_0_WIDTH (2U) 2903 #define ADC_CWSELRSI_WSEL_SI5_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI5_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI5_0_MASK) 2904 2905 #define ADC_CWSELRSI_WSEL_SI5_1_MASK (0x300000U) 2906 #define ADC_CWSELRSI_WSEL_SI5_1_SHIFT (20U) 2907 #define ADC_CWSELRSI_WSEL_SI5_1_WIDTH (2U) 2908 #define ADC_CWSELRSI_WSEL_SI5_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI5_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI5_1_MASK) 2909 2910 #define ADC_CWSELRSI_WSEL_SI5_2_MASK (0x300000U) 2911 #define ADC_CWSELRSI_WSEL_SI5_2_SHIFT (20U) 2912 #define ADC_CWSELRSI_WSEL_SI5_2_WIDTH (2U) 2913 #define ADC_CWSELRSI_WSEL_SI5_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI5_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI5_2_MASK) 2914 2915 #define ADC_CWSELRSI_WSEL_SI6_0_MASK (0x3000000U) 2916 #define ADC_CWSELRSI_WSEL_SI6_0_SHIFT (24U) 2917 #define ADC_CWSELRSI_WSEL_SI6_0_WIDTH (2U) 2918 #define ADC_CWSELRSI_WSEL_SI6_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI6_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI6_0_MASK) 2919 2920 #define ADC_CWSELRSI_WSEL_SI6_1_MASK (0x3000000U) 2921 #define ADC_CWSELRSI_WSEL_SI6_1_SHIFT (24U) 2922 #define ADC_CWSELRSI_WSEL_SI6_1_WIDTH (2U) 2923 #define ADC_CWSELRSI_WSEL_SI6_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI6_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI6_1_MASK) 2924 2925 #define ADC_CWSELRSI_WSEL_SI6_2_MASK (0x3000000U) 2926 #define ADC_CWSELRSI_WSEL_SI6_2_SHIFT (24U) 2927 #define ADC_CWSELRSI_WSEL_SI6_2_WIDTH (2U) 2928 #define ADC_CWSELRSI_WSEL_SI6_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI6_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI6_2_MASK) 2929 2930 #define ADC_CWSELRSI_WSEL_SI7_0_MASK (0x30000000U) 2931 #define ADC_CWSELRSI_WSEL_SI7_0_SHIFT (28U) 2932 #define ADC_CWSELRSI_WSEL_SI7_0_WIDTH (2U) 2933 #define ADC_CWSELRSI_WSEL_SI7_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI7_0_SHIFT)) & ADC_CWSELRSI_WSEL_SI7_0_MASK) 2934 2935 #define ADC_CWSELRSI_WSEL_SI7_1_MASK (0x30000000U) 2936 #define ADC_CWSELRSI_WSEL_SI7_1_SHIFT (28U) 2937 #define ADC_CWSELRSI_WSEL_SI7_1_WIDTH (2U) 2938 #define ADC_CWSELRSI_WSEL_SI7_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI7_1_SHIFT)) & ADC_CWSELRSI_WSEL_SI7_1_MASK) 2939 2940 #define ADC_CWSELRSI_WSEL_SI7_2_MASK (0x30000000U) 2941 #define ADC_CWSELRSI_WSEL_SI7_2_SHIFT (28U) 2942 #define ADC_CWSELRSI_WSEL_SI7_2_WIDTH (2U) 2943 #define ADC_CWSELRSI_WSEL_SI7_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELRSI_WSEL_SI7_2_SHIFT)) & ADC_CWSELRSI_WSEL_SI7_2_MASK) 2944 /*! @} */ 2945 2946 /*! @name CWSELREI - Channel Analog Watchdog Select For External inputs */ 2947 /*! @{ */ 2948 2949 #define ADC_CWSELREI_WSEL_SI0_0_MASK (0x3U) 2950 #define ADC_CWSELREI_WSEL_SI0_0_SHIFT (0U) 2951 #define ADC_CWSELREI_WSEL_SI0_0_WIDTH (2U) 2952 #define ADC_CWSELREI_WSEL_SI0_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_0_SHIFT)) & ADC_CWSELREI_WSEL_SI0_0_MASK) 2953 2954 #define ADC_CWSELREI_WSEL_SI1_8_MASK (0x3U) 2955 #define ADC_CWSELREI_WSEL_SI1_8_SHIFT (0U) 2956 #define ADC_CWSELREI_WSEL_SI1_8_WIDTH (2U) 2957 #define ADC_CWSELREI_WSEL_SI1_8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_8_SHIFT)) & ADC_CWSELREI_WSEL_SI1_8_MASK) 2958 2959 #define ADC_CWSELREI_WSEL_SI2_16_MASK (0x3U) 2960 #define ADC_CWSELREI_WSEL_SI2_16_SHIFT (0U) 2961 #define ADC_CWSELREI_WSEL_SI2_16_WIDTH (2U) 2962 #define ADC_CWSELREI_WSEL_SI2_16(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_16_SHIFT)) & ADC_CWSELREI_WSEL_SI2_16_MASK) 2963 2964 #define ADC_CWSELREI_WSEL_SI3_24_MASK (0x3U) 2965 #define ADC_CWSELREI_WSEL_SI3_24_SHIFT (0U) 2966 #define ADC_CWSELREI_WSEL_SI3_24_WIDTH (2U) 2967 #define ADC_CWSELREI_WSEL_SI3_24(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_24_SHIFT)) & ADC_CWSELREI_WSEL_SI3_24_MASK) 2968 2969 #define ADC_CWSELREI_WSEL_SI0_1_MASK (0x30U) 2970 #define ADC_CWSELREI_WSEL_SI0_1_SHIFT (4U) 2971 #define ADC_CWSELREI_WSEL_SI0_1_WIDTH (2U) 2972 #define ADC_CWSELREI_WSEL_SI0_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_1_SHIFT)) & ADC_CWSELREI_WSEL_SI0_1_MASK) 2973 2974 #define ADC_CWSELREI_WSEL_SI1_9_MASK (0x30U) 2975 #define ADC_CWSELREI_WSEL_SI1_9_SHIFT (4U) 2976 #define ADC_CWSELREI_WSEL_SI1_9_WIDTH (2U) 2977 #define ADC_CWSELREI_WSEL_SI1_9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_9_SHIFT)) & ADC_CWSELREI_WSEL_SI1_9_MASK) 2978 2979 #define ADC_CWSELREI_WSEL_SI2_17_MASK (0x30U) 2980 #define ADC_CWSELREI_WSEL_SI2_17_SHIFT (4U) 2981 #define ADC_CWSELREI_WSEL_SI2_17_WIDTH (2U) 2982 #define ADC_CWSELREI_WSEL_SI2_17(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_17_SHIFT)) & ADC_CWSELREI_WSEL_SI2_17_MASK) 2983 2984 #define ADC_CWSELREI_WSEL_SI3_25_MASK (0x30U) 2985 #define ADC_CWSELREI_WSEL_SI3_25_SHIFT (4U) 2986 #define ADC_CWSELREI_WSEL_SI3_25_WIDTH (2U) 2987 #define ADC_CWSELREI_WSEL_SI3_25(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_25_SHIFT)) & ADC_CWSELREI_WSEL_SI3_25_MASK) 2988 2989 #define ADC_CWSELREI_WSEL_SI0_2_MASK (0x300U) 2990 #define ADC_CWSELREI_WSEL_SI0_2_SHIFT (8U) 2991 #define ADC_CWSELREI_WSEL_SI0_2_WIDTH (2U) 2992 #define ADC_CWSELREI_WSEL_SI0_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_2_SHIFT)) & ADC_CWSELREI_WSEL_SI0_2_MASK) 2993 2994 #define ADC_CWSELREI_WSEL_SI1_10_MASK (0x300U) 2995 #define ADC_CWSELREI_WSEL_SI1_10_SHIFT (8U) 2996 #define ADC_CWSELREI_WSEL_SI1_10_WIDTH (2U) 2997 #define ADC_CWSELREI_WSEL_SI1_10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_10_SHIFT)) & ADC_CWSELREI_WSEL_SI1_10_MASK) 2998 2999 #define ADC_CWSELREI_WSEL_SI2_18_MASK (0x300U) 3000 #define ADC_CWSELREI_WSEL_SI2_18_SHIFT (8U) 3001 #define ADC_CWSELREI_WSEL_SI2_18_WIDTH (2U) 3002 #define ADC_CWSELREI_WSEL_SI2_18(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_18_SHIFT)) & ADC_CWSELREI_WSEL_SI2_18_MASK) 3003 3004 #define ADC_CWSELREI_WSEL_SI3_26_MASK (0x300U) 3005 #define ADC_CWSELREI_WSEL_SI3_26_SHIFT (8U) 3006 #define ADC_CWSELREI_WSEL_SI3_26_WIDTH (2U) 3007 #define ADC_CWSELREI_WSEL_SI3_26(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_26_SHIFT)) & ADC_CWSELREI_WSEL_SI3_26_MASK) 3008 3009 #define ADC_CWSELREI_WSEL_SI0_3_MASK (0x3000U) 3010 #define ADC_CWSELREI_WSEL_SI0_3_SHIFT (12U) 3011 #define ADC_CWSELREI_WSEL_SI0_3_WIDTH (2U) 3012 #define ADC_CWSELREI_WSEL_SI0_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_3_SHIFT)) & ADC_CWSELREI_WSEL_SI0_3_MASK) 3013 3014 #define ADC_CWSELREI_WSEL_SI1_11_MASK (0x3000U) 3015 #define ADC_CWSELREI_WSEL_SI1_11_SHIFT (12U) 3016 #define ADC_CWSELREI_WSEL_SI1_11_WIDTH (2U) 3017 #define ADC_CWSELREI_WSEL_SI1_11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_11_SHIFT)) & ADC_CWSELREI_WSEL_SI1_11_MASK) 3018 3019 #define ADC_CWSELREI_WSEL_SI2_19_MASK (0x3000U) 3020 #define ADC_CWSELREI_WSEL_SI2_19_SHIFT (12U) 3021 #define ADC_CWSELREI_WSEL_SI2_19_WIDTH (2U) 3022 #define ADC_CWSELREI_WSEL_SI2_19(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_19_SHIFT)) & ADC_CWSELREI_WSEL_SI2_19_MASK) 3023 3024 #define ADC_CWSELREI_WSEL_SI3_27_MASK (0x3000U) 3025 #define ADC_CWSELREI_WSEL_SI3_27_SHIFT (12U) 3026 #define ADC_CWSELREI_WSEL_SI3_27_WIDTH (2U) 3027 #define ADC_CWSELREI_WSEL_SI3_27(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_27_SHIFT)) & ADC_CWSELREI_WSEL_SI3_27_MASK) 3028 3029 #define ADC_CWSELREI_WSEL_SI0_4_MASK (0x30000U) 3030 #define ADC_CWSELREI_WSEL_SI0_4_SHIFT (16U) 3031 #define ADC_CWSELREI_WSEL_SI0_4_WIDTH (2U) 3032 #define ADC_CWSELREI_WSEL_SI0_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_4_SHIFT)) & ADC_CWSELREI_WSEL_SI0_4_MASK) 3033 3034 #define ADC_CWSELREI_WSEL_SI1_12_MASK (0x30000U) 3035 #define ADC_CWSELREI_WSEL_SI1_12_SHIFT (16U) 3036 #define ADC_CWSELREI_WSEL_SI1_12_WIDTH (2U) 3037 #define ADC_CWSELREI_WSEL_SI1_12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_12_SHIFT)) & ADC_CWSELREI_WSEL_SI1_12_MASK) 3038 3039 #define ADC_CWSELREI_WSEL_SI2_20_MASK (0x30000U) 3040 #define ADC_CWSELREI_WSEL_SI2_20_SHIFT (16U) 3041 #define ADC_CWSELREI_WSEL_SI2_20_WIDTH (2U) 3042 #define ADC_CWSELREI_WSEL_SI2_20(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_20_SHIFT)) & ADC_CWSELREI_WSEL_SI2_20_MASK) 3043 3044 #define ADC_CWSELREI_WSEL_SI3_28_MASK (0x30000U) 3045 #define ADC_CWSELREI_WSEL_SI3_28_SHIFT (16U) 3046 #define ADC_CWSELREI_WSEL_SI3_28_WIDTH (2U) 3047 #define ADC_CWSELREI_WSEL_SI3_28(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_28_SHIFT)) & ADC_CWSELREI_WSEL_SI3_28_MASK) 3048 3049 #define ADC_CWSELREI_WSEL_SI0_5_MASK (0x300000U) 3050 #define ADC_CWSELREI_WSEL_SI0_5_SHIFT (20U) 3051 #define ADC_CWSELREI_WSEL_SI0_5_WIDTH (2U) 3052 #define ADC_CWSELREI_WSEL_SI0_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_5_SHIFT)) & ADC_CWSELREI_WSEL_SI0_5_MASK) 3053 3054 #define ADC_CWSELREI_WSEL_SI1_13_MASK (0x300000U) 3055 #define ADC_CWSELREI_WSEL_SI1_13_SHIFT (20U) 3056 #define ADC_CWSELREI_WSEL_SI1_13_WIDTH (2U) 3057 #define ADC_CWSELREI_WSEL_SI1_13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_13_SHIFT)) & ADC_CWSELREI_WSEL_SI1_13_MASK) 3058 3059 #define ADC_CWSELREI_WSEL_SI2_21_MASK (0x300000U) 3060 #define ADC_CWSELREI_WSEL_SI2_21_SHIFT (20U) 3061 #define ADC_CWSELREI_WSEL_SI2_21_WIDTH (2U) 3062 #define ADC_CWSELREI_WSEL_SI2_21(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_21_SHIFT)) & ADC_CWSELREI_WSEL_SI2_21_MASK) 3063 3064 #define ADC_CWSELREI_WSEL_SI3_29_MASK (0x300000U) 3065 #define ADC_CWSELREI_WSEL_SI3_29_SHIFT (20U) 3066 #define ADC_CWSELREI_WSEL_SI3_29_WIDTH (2U) 3067 #define ADC_CWSELREI_WSEL_SI3_29(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_29_SHIFT)) & ADC_CWSELREI_WSEL_SI3_29_MASK) 3068 3069 #define ADC_CWSELREI_WSEL_SI0_6_MASK (0x3000000U) 3070 #define ADC_CWSELREI_WSEL_SI0_6_SHIFT (24U) 3071 #define ADC_CWSELREI_WSEL_SI0_6_WIDTH (2U) 3072 #define ADC_CWSELREI_WSEL_SI0_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_6_SHIFT)) & ADC_CWSELREI_WSEL_SI0_6_MASK) 3073 3074 #define ADC_CWSELREI_WSEL_SI1_14_MASK (0x3000000U) 3075 #define ADC_CWSELREI_WSEL_SI1_14_SHIFT (24U) 3076 #define ADC_CWSELREI_WSEL_SI1_14_WIDTH (2U) 3077 #define ADC_CWSELREI_WSEL_SI1_14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_14_SHIFT)) & ADC_CWSELREI_WSEL_SI1_14_MASK) 3078 3079 #define ADC_CWSELREI_WSEL_SI2_22_MASK (0x3000000U) 3080 #define ADC_CWSELREI_WSEL_SI2_22_SHIFT (24U) 3081 #define ADC_CWSELREI_WSEL_SI2_22_WIDTH (2U) 3082 #define ADC_CWSELREI_WSEL_SI2_22(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_22_SHIFT)) & ADC_CWSELREI_WSEL_SI2_22_MASK) 3083 3084 #define ADC_CWSELREI_WSEL_SI3_30_MASK (0x3000000U) 3085 #define ADC_CWSELREI_WSEL_SI3_30_SHIFT (24U) 3086 #define ADC_CWSELREI_WSEL_SI3_30_WIDTH (2U) 3087 #define ADC_CWSELREI_WSEL_SI3_30(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_30_SHIFT)) & ADC_CWSELREI_WSEL_SI3_30_MASK) 3088 3089 #define ADC_CWSELREI_WSEL_SI0_7_MASK (0x30000000U) 3090 #define ADC_CWSELREI_WSEL_SI0_7_SHIFT (28U) 3091 #define ADC_CWSELREI_WSEL_SI0_7_WIDTH (2U) 3092 #define ADC_CWSELREI_WSEL_SI0_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI0_7_SHIFT)) & ADC_CWSELREI_WSEL_SI0_7_MASK) 3093 3094 #define ADC_CWSELREI_WSEL_SI1_15_MASK (0x30000000U) 3095 #define ADC_CWSELREI_WSEL_SI1_15_SHIFT (28U) 3096 #define ADC_CWSELREI_WSEL_SI1_15_WIDTH (2U) 3097 #define ADC_CWSELREI_WSEL_SI1_15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI1_15_SHIFT)) & ADC_CWSELREI_WSEL_SI1_15_MASK) 3098 3099 #define ADC_CWSELREI_WSEL_SI2_23_MASK (0x30000000U) 3100 #define ADC_CWSELREI_WSEL_SI2_23_SHIFT (28U) 3101 #define ADC_CWSELREI_WSEL_SI2_23_WIDTH (2U) 3102 #define ADC_CWSELREI_WSEL_SI2_23(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI2_23_SHIFT)) & ADC_CWSELREI_WSEL_SI2_23_MASK) 3103 3104 #define ADC_CWSELREI_WSEL_SI3_31_MASK (0x30000000U) 3105 #define ADC_CWSELREI_WSEL_SI3_31_SHIFT (28U) 3106 #define ADC_CWSELREI_WSEL_SI3_31_WIDTH (2U) 3107 #define ADC_CWSELREI_WSEL_SI3_31(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELREI_WSEL_SI3_31_SHIFT)) & ADC_CWSELREI_WSEL_SI3_31_MASK) 3108 /*! @} */ 3109 3110 /*! @name CWENR0 - Channel Watchdog Enable For Precision Inputs */ 3111 /*! @{ */ 3112 3113 #define ADC_CWENR0_CWEN0_MASK (0x1U) 3114 #define ADC_CWENR0_CWEN0_SHIFT (0U) 3115 #define ADC_CWENR0_CWEN0_WIDTH (1U) 3116 #define ADC_CWENR0_CWEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN0_SHIFT)) & ADC_CWENR0_CWEN0_MASK) 3117 3118 #define ADC_CWENR0_CWEN1_MASK (0x2U) 3119 #define ADC_CWENR0_CWEN1_SHIFT (1U) 3120 #define ADC_CWENR0_CWEN1_WIDTH (1U) 3121 #define ADC_CWENR0_CWEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN1_SHIFT)) & ADC_CWENR0_CWEN1_MASK) 3122 3123 #define ADC_CWENR0_CWEN2_MASK (0x4U) 3124 #define ADC_CWENR0_CWEN2_SHIFT (2U) 3125 #define ADC_CWENR0_CWEN2_WIDTH (1U) 3126 #define ADC_CWENR0_CWEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN2_SHIFT)) & ADC_CWENR0_CWEN2_MASK) 3127 3128 #define ADC_CWENR0_CWEN3_MASK (0x8U) 3129 #define ADC_CWENR0_CWEN3_SHIFT (3U) 3130 #define ADC_CWENR0_CWEN3_WIDTH (1U) 3131 #define ADC_CWENR0_CWEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN3_SHIFT)) & ADC_CWENR0_CWEN3_MASK) 3132 3133 #define ADC_CWENR0_CWEN4_MASK (0x10U) 3134 #define ADC_CWENR0_CWEN4_SHIFT (4U) 3135 #define ADC_CWENR0_CWEN4_WIDTH (1U) 3136 #define ADC_CWENR0_CWEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN4_SHIFT)) & ADC_CWENR0_CWEN4_MASK) 3137 3138 #define ADC_CWENR0_CWEN5_MASK (0x20U) 3139 #define ADC_CWENR0_CWEN5_SHIFT (5U) 3140 #define ADC_CWENR0_CWEN5_WIDTH (1U) 3141 #define ADC_CWENR0_CWEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN5_SHIFT)) & ADC_CWENR0_CWEN5_MASK) 3142 3143 #define ADC_CWENR0_CWEN6_MASK (0x40U) 3144 #define ADC_CWENR0_CWEN6_SHIFT (6U) 3145 #define ADC_CWENR0_CWEN6_WIDTH (1U) 3146 #define ADC_CWENR0_CWEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN6_SHIFT)) & ADC_CWENR0_CWEN6_MASK) 3147 3148 #define ADC_CWENR0_CWEN7_MASK (0x80U) 3149 #define ADC_CWENR0_CWEN7_SHIFT (7U) 3150 #define ADC_CWENR0_CWEN7_WIDTH (1U) 3151 #define ADC_CWENR0_CWEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN7_SHIFT)) & ADC_CWENR0_CWEN7_MASK) 3152 /*! @} */ 3153 3154 /*! @name CWENR1 - Channel Watchdog Enable For Standard Inputs */ 3155 /*! @{ */ 3156 3157 #define ADC_CWENR1_CWEN32_MASK (0x1U) 3158 #define ADC_CWENR1_CWEN32_SHIFT (0U) 3159 #define ADC_CWENR1_CWEN32_WIDTH (1U) 3160 #define ADC_CWENR1_CWEN32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN32_SHIFT)) & ADC_CWENR1_CWEN32_MASK) 3161 3162 #define ADC_CWENR1_CWEN33_MASK (0x2U) 3163 #define ADC_CWENR1_CWEN33_SHIFT (1U) 3164 #define ADC_CWENR1_CWEN33_WIDTH (1U) 3165 #define ADC_CWENR1_CWEN33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN33_SHIFT)) & ADC_CWENR1_CWEN33_MASK) 3166 3167 #define ADC_CWENR1_CWEN34_MASK (0x4U) 3168 #define ADC_CWENR1_CWEN34_SHIFT (2U) 3169 #define ADC_CWENR1_CWEN34_WIDTH (1U) 3170 #define ADC_CWENR1_CWEN34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN34_SHIFT)) & ADC_CWENR1_CWEN34_MASK) 3171 3172 #define ADC_CWENR1_CWEN35_MASK (0x8U) 3173 #define ADC_CWENR1_CWEN35_SHIFT (3U) 3174 #define ADC_CWENR1_CWEN35_WIDTH (1U) 3175 #define ADC_CWENR1_CWEN35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN35_SHIFT)) & ADC_CWENR1_CWEN35_MASK) 3176 3177 #define ADC_CWENR1_CWEN36_MASK (0x10U) 3178 #define ADC_CWENR1_CWEN36_SHIFT (4U) 3179 #define ADC_CWENR1_CWEN36_WIDTH (1U) 3180 #define ADC_CWENR1_CWEN36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN36_SHIFT)) & ADC_CWENR1_CWEN36_MASK) 3181 3182 #define ADC_CWENR1_CWEN37_MASK (0x20U) 3183 #define ADC_CWENR1_CWEN37_SHIFT (5U) 3184 #define ADC_CWENR1_CWEN37_WIDTH (1U) 3185 #define ADC_CWENR1_CWEN37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN37_SHIFT)) & ADC_CWENR1_CWEN37_MASK) 3186 3187 #define ADC_CWENR1_CWEN38_MASK (0x40U) 3188 #define ADC_CWENR1_CWEN38_SHIFT (6U) 3189 #define ADC_CWENR1_CWEN38_WIDTH (1U) 3190 #define ADC_CWENR1_CWEN38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN38_SHIFT)) & ADC_CWENR1_CWEN38_MASK) 3191 3192 #define ADC_CWENR1_CWEN39_MASK (0x80U) 3193 #define ADC_CWENR1_CWEN39_SHIFT (7U) 3194 #define ADC_CWENR1_CWEN39_WIDTH (1U) 3195 #define ADC_CWENR1_CWEN39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN39_SHIFT)) & ADC_CWENR1_CWEN39_MASK) 3196 3197 #define ADC_CWENR1_CWEN40_MASK (0x100U) 3198 #define ADC_CWENR1_CWEN40_SHIFT (8U) 3199 #define ADC_CWENR1_CWEN40_WIDTH (1U) 3200 #define ADC_CWENR1_CWEN40(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN40_SHIFT)) & ADC_CWENR1_CWEN40_MASK) 3201 3202 #define ADC_CWENR1_CWEN41_MASK (0x200U) 3203 #define ADC_CWENR1_CWEN41_SHIFT (9U) 3204 #define ADC_CWENR1_CWEN41_WIDTH (1U) 3205 #define ADC_CWENR1_CWEN41(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN41_SHIFT)) & ADC_CWENR1_CWEN41_MASK) 3206 3207 #define ADC_CWENR1_CWEN42_MASK (0x400U) 3208 #define ADC_CWENR1_CWEN42_SHIFT (10U) 3209 #define ADC_CWENR1_CWEN42_WIDTH (1U) 3210 #define ADC_CWENR1_CWEN42(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN42_SHIFT)) & ADC_CWENR1_CWEN42_MASK) 3211 3212 #define ADC_CWENR1_CWEN43_MASK (0x800U) 3213 #define ADC_CWENR1_CWEN43_SHIFT (11U) 3214 #define ADC_CWENR1_CWEN43_WIDTH (1U) 3215 #define ADC_CWENR1_CWEN43(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN43_SHIFT)) & ADC_CWENR1_CWEN43_MASK) 3216 3217 #define ADC_CWENR1_CWEN44_MASK (0x1000U) 3218 #define ADC_CWENR1_CWEN44_SHIFT (12U) 3219 #define ADC_CWENR1_CWEN44_WIDTH (1U) 3220 #define ADC_CWENR1_CWEN44(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN44_SHIFT)) & ADC_CWENR1_CWEN44_MASK) 3221 3222 #define ADC_CWENR1_CWEN45_MASK (0x2000U) 3223 #define ADC_CWENR1_CWEN45_SHIFT (13U) 3224 #define ADC_CWENR1_CWEN45_WIDTH (1U) 3225 #define ADC_CWENR1_CWEN45(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN45_SHIFT)) & ADC_CWENR1_CWEN45_MASK) 3226 3227 #define ADC_CWENR1_CWEN46_MASK (0x4000U) 3228 #define ADC_CWENR1_CWEN46_SHIFT (14U) 3229 #define ADC_CWENR1_CWEN46_WIDTH (1U) 3230 #define ADC_CWENR1_CWEN46(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN46_SHIFT)) & ADC_CWENR1_CWEN46_MASK) 3231 3232 #define ADC_CWENR1_CWEN47_MASK (0x8000U) 3233 #define ADC_CWENR1_CWEN47_SHIFT (15U) 3234 #define ADC_CWENR1_CWEN47_WIDTH (1U) 3235 #define ADC_CWENR1_CWEN47(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN47_SHIFT)) & ADC_CWENR1_CWEN47_MASK) 3236 3237 #define ADC_CWENR1_CWEN48_MASK (0x10000U) 3238 #define ADC_CWENR1_CWEN48_SHIFT (16U) 3239 #define ADC_CWENR1_CWEN48_WIDTH (1U) 3240 #define ADC_CWENR1_CWEN48(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN48_SHIFT)) & ADC_CWENR1_CWEN48_MASK) 3241 3242 #define ADC_CWENR1_CWEN49_MASK (0x20000U) 3243 #define ADC_CWENR1_CWEN49_SHIFT (17U) 3244 #define ADC_CWENR1_CWEN49_WIDTH (1U) 3245 #define ADC_CWENR1_CWEN49(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN49_SHIFT)) & ADC_CWENR1_CWEN49_MASK) 3246 3247 #define ADC_CWENR1_CWEN50_MASK (0x40000U) 3248 #define ADC_CWENR1_CWEN50_SHIFT (18U) 3249 #define ADC_CWENR1_CWEN50_WIDTH (1U) 3250 #define ADC_CWENR1_CWEN50(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN50_SHIFT)) & ADC_CWENR1_CWEN50_MASK) 3251 3252 #define ADC_CWENR1_CWEN51_MASK (0x80000U) 3253 #define ADC_CWENR1_CWEN51_SHIFT (19U) 3254 #define ADC_CWENR1_CWEN51_WIDTH (1U) 3255 #define ADC_CWENR1_CWEN51(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN51_SHIFT)) & ADC_CWENR1_CWEN51_MASK) 3256 3257 #define ADC_CWENR1_CWEN52_MASK (0x100000U) 3258 #define ADC_CWENR1_CWEN52_SHIFT (20U) 3259 #define ADC_CWENR1_CWEN52_WIDTH (1U) 3260 #define ADC_CWENR1_CWEN52(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN52_SHIFT)) & ADC_CWENR1_CWEN52_MASK) 3261 3262 #define ADC_CWENR1_CWEN53_MASK (0x200000U) 3263 #define ADC_CWENR1_CWEN53_SHIFT (21U) 3264 #define ADC_CWENR1_CWEN53_WIDTH (1U) 3265 #define ADC_CWENR1_CWEN53(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN53_SHIFT)) & ADC_CWENR1_CWEN53_MASK) 3266 3267 #define ADC_CWENR1_CWEN54_MASK (0x400000U) 3268 #define ADC_CWENR1_CWEN54_SHIFT (22U) 3269 #define ADC_CWENR1_CWEN54_WIDTH (1U) 3270 #define ADC_CWENR1_CWEN54(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN54_SHIFT)) & ADC_CWENR1_CWEN54_MASK) 3271 3272 #define ADC_CWENR1_CWEN55_MASK (0x800000U) 3273 #define ADC_CWENR1_CWEN55_SHIFT (23U) 3274 #define ADC_CWENR1_CWEN55_WIDTH (1U) 3275 #define ADC_CWENR1_CWEN55(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN55_SHIFT)) & ADC_CWENR1_CWEN55_MASK) 3276 /*! @} */ 3277 3278 /*! @name CWENR2 - Channel Watchdog Enable For External Inputs */ 3279 /*! @{ */ 3280 3281 #define ADC_CWENR2_CWEN64_MASK (0x1U) 3282 #define ADC_CWENR2_CWEN64_SHIFT (0U) 3283 #define ADC_CWENR2_CWEN64_WIDTH (1U) 3284 #define ADC_CWENR2_CWEN64(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN64_SHIFT)) & ADC_CWENR2_CWEN64_MASK) 3285 3286 #define ADC_CWENR2_CWEN65_MASK (0x2U) 3287 #define ADC_CWENR2_CWEN65_SHIFT (1U) 3288 #define ADC_CWENR2_CWEN65_WIDTH (1U) 3289 #define ADC_CWENR2_CWEN65(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN65_SHIFT)) & ADC_CWENR2_CWEN65_MASK) 3290 3291 #define ADC_CWENR2_CWEN66_MASK (0x4U) 3292 #define ADC_CWENR2_CWEN66_SHIFT (2U) 3293 #define ADC_CWENR2_CWEN66_WIDTH (1U) 3294 #define ADC_CWENR2_CWEN66(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN66_SHIFT)) & ADC_CWENR2_CWEN66_MASK) 3295 3296 #define ADC_CWENR2_CWEN67_MASK (0x8U) 3297 #define ADC_CWENR2_CWEN67_SHIFT (3U) 3298 #define ADC_CWENR2_CWEN67_WIDTH (1U) 3299 #define ADC_CWENR2_CWEN67(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN67_SHIFT)) & ADC_CWENR2_CWEN67_MASK) 3300 3301 #define ADC_CWENR2_CWEN68_MASK (0x10U) 3302 #define ADC_CWENR2_CWEN68_SHIFT (4U) 3303 #define ADC_CWENR2_CWEN68_WIDTH (1U) 3304 #define ADC_CWENR2_CWEN68(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN68_SHIFT)) & ADC_CWENR2_CWEN68_MASK) 3305 3306 #define ADC_CWENR2_CWEN69_MASK (0x20U) 3307 #define ADC_CWENR2_CWEN69_SHIFT (5U) 3308 #define ADC_CWENR2_CWEN69_WIDTH (1U) 3309 #define ADC_CWENR2_CWEN69(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN69_SHIFT)) & ADC_CWENR2_CWEN69_MASK) 3310 3311 #define ADC_CWENR2_CWEN70_MASK (0x40U) 3312 #define ADC_CWENR2_CWEN70_SHIFT (6U) 3313 #define ADC_CWENR2_CWEN70_WIDTH (1U) 3314 #define ADC_CWENR2_CWEN70(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN70_SHIFT)) & ADC_CWENR2_CWEN70_MASK) 3315 3316 #define ADC_CWENR2_CWEN71_MASK (0x80U) 3317 #define ADC_CWENR2_CWEN71_SHIFT (7U) 3318 #define ADC_CWENR2_CWEN71_WIDTH (1U) 3319 #define ADC_CWENR2_CWEN71(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN71_SHIFT)) & ADC_CWENR2_CWEN71_MASK) 3320 3321 #define ADC_CWENR2_CWEN72_MASK (0x100U) 3322 #define ADC_CWENR2_CWEN72_SHIFT (8U) 3323 #define ADC_CWENR2_CWEN72_WIDTH (1U) 3324 #define ADC_CWENR2_CWEN72(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN72_SHIFT)) & ADC_CWENR2_CWEN72_MASK) 3325 3326 #define ADC_CWENR2_CWEN73_MASK (0x200U) 3327 #define ADC_CWENR2_CWEN73_SHIFT (9U) 3328 #define ADC_CWENR2_CWEN73_WIDTH (1U) 3329 #define ADC_CWENR2_CWEN73(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN73_SHIFT)) & ADC_CWENR2_CWEN73_MASK) 3330 3331 #define ADC_CWENR2_CWEN74_MASK (0x400U) 3332 #define ADC_CWENR2_CWEN74_SHIFT (10U) 3333 #define ADC_CWENR2_CWEN74_WIDTH (1U) 3334 #define ADC_CWENR2_CWEN74(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN74_SHIFT)) & ADC_CWENR2_CWEN74_MASK) 3335 3336 #define ADC_CWENR2_CWEN75_MASK (0x800U) 3337 #define ADC_CWENR2_CWEN75_SHIFT (11U) 3338 #define ADC_CWENR2_CWEN75_WIDTH (1U) 3339 #define ADC_CWENR2_CWEN75(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN75_SHIFT)) & ADC_CWENR2_CWEN75_MASK) 3340 3341 #define ADC_CWENR2_CWEN76_MASK (0x1000U) 3342 #define ADC_CWENR2_CWEN76_SHIFT (12U) 3343 #define ADC_CWENR2_CWEN76_WIDTH (1U) 3344 #define ADC_CWENR2_CWEN76(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN76_SHIFT)) & ADC_CWENR2_CWEN76_MASK) 3345 3346 #define ADC_CWENR2_CWEN77_MASK (0x2000U) 3347 #define ADC_CWENR2_CWEN77_SHIFT (13U) 3348 #define ADC_CWENR2_CWEN77_WIDTH (1U) 3349 #define ADC_CWENR2_CWEN77(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN77_SHIFT)) & ADC_CWENR2_CWEN77_MASK) 3350 3351 #define ADC_CWENR2_CWEN78_MASK (0x4000U) 3352 #define ADC_CWENR2_CWEN78_SHIFT (14U) 3353 #define ADC_CWENR2_CWEN78_WIDTH (1U) 3354 #define ADC_CWENR2_CWEN78(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN78_SHIFT)) & ADC_CWENR2_CWEN78_MASK) 3355 3356 #define ADC_CWENR2_CWEN79_MASK (0x8000U) 3357 #define ADC_CWENR2_CWEN79_SHIFT (15U) 3358 #define ADC_CWENR2_CWEN79_WIDTH (1U) 3359 #define ADC_CWENR2_CWEN79(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN79_SHIFT)) & ADC_CWENR2_CWEN79_MASK) 3360 3361 #define ADC_CWENR2_CWEN80_MASK (0x10000U) 3362 #define ADC_CWENR2_CWEN80_SHIFT (16U) 3363 #define ADC_CWENR2_CWEN80_WIDTH (1U) 3364 #define ADC_CWENR2_CWEN80(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN80_SHIFT)) & ADC_CWENR2_CWEN80_MASK) 3365 3366 #define ADC_CWENR2_CWEN81_MASK (0x20000U) 3367 #define ADC_CWENR2_CWEN81_SHIFT (17U) 3368 #define ADC_CWENR2_CWEN81_WIDTH (1U) 3369 #define ADC_CWENR2_CWEN81(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN81_SHIFT)) & ADC_CWENR2_CWEN81_MASK) 3370 3371 #define ADC_CWENR2_CWEN82_MASK (0x40000U) 3372 #define ADC_CWENR2_CWEN82_SHIFT (18U) 3373 #define ADC_CWENR2_CWEN82_WIDTH (1U) 3374 #define ADC_CWENR2_CWEN82(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN82_SHIFT)) & ADC_CWENR2_CWEN82_MASK) 3375 3376 #define ADC_CWENR2_CWEN83_MASK (0x80000U) 3377 #define ADC_CWENR2_CWEN83_SHIFT (19U) 3378 #define ADC_CWENR2_CWEN83_WIDTH (1U) 3379 #define ADC_CWENR2_CWEN83(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN83_SHIFT)) & ADC_CWENR2_CWEN83_MASK) 3380 3381 #define ADC_CWENR2_CWEN84_MASK (0x100000U) 3382 #define ADC_CWENR2_CWEN84_SHIFT (20U) 3383 #define ADC_CWENR2_CWEN84_WIDTH (1U) 3384 #define ADC_CWENR2_CWEN84(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN84_SHIFT)) & ADC_CWENR2_CWEN84_MASK) 3385 3386 #define ADC_CWENR2_CWEN85_MASK (0x200000U) 3387 #define ADC_CWENR2_CWEN85_SHIFT (21U) 3388 #define ADC_CWENR2_CWEN85_WIDTH (1U) 3389 #define ADC_CWENR2_CWEN85(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN85_SHIFT)) & ADC_CWENR2_CWEN85_MASK) 3390 3391 #define ADC_CWENR2_CWEN86_MASK (0x400000U) 3392 #define ADC_CWENR2_CWEN86_SHIFT (22U) 3393 #define ADC_CWENR2_CWEN86_WIDTH (1U) 3394 #define ADC_CWENR2_CWEN86(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN86_SHIFT)) & ADC_CWENR2_CWEN86_MASK) 3395 3396 #define ADC_CWENR2_CWEN87_MASK (0x800000U) 3397 #define ADC_CWENR2_CWEN87_SHIFT (23U) 3398 #define ADC_CWENR2_CWEN87_WIDTH (1U) 3399 #define ADC_CWENR2_CWEN87(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN87_SHIFT)) & ADC_CWENR2_CWEN87_MASK) 3400 3401 #define ADC_CWENR2_CWEN88_MASK (0x1000000U) 3402 #define ADC_CWENR2_CWEN88_SHIFT (24U) 3403 #define ADC_CWENR2_CWEN88_WIDTH (1U) 3404 #define ADC_CWENR2_CWEN88(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN88_SHIFT)) & ADC_CWENR2_CWEN88_MASK) 3405 3406 #define ADC_CWENR2_CWEN89_MASK (0x2000000U) 3407 #define ADC_CWENR2_CWEN89_SHIFT (25U) 3408 #define ADC_CWENR2_CWEN89_WIDTH (1U) 3409 #define ADC_CWENR2_CWEN89(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN89_SHIFT)) & ADC_CWENR2_CWEN89_MASK) 3410 3411 #define ADC_CWENR2_CWEN90_MASK (0x4000000U) 3412 #define ADC_CWENR2_CWEN90_SHIFT (26U) 3413 #define ADC_CWENR2_CWEN90_WIDTH (1U) 3414 #define ADC_CWENR2_CWEN90(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN90_SHIFT)) & ADC_CWENR2_CWEN90_MASK) 3415 3416 #define ADC_CWENR2_CWEN91_MASK (0x8000000U) 3417 #define ADC_CWENR2_CWEN91_SHIFT (27U) 3418 #define ADC_CWENR2_CWEN91_WIDTH (1U) 3419 #define ADC_CWENR2_CWEN91(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN91_SHIFT)) & ADC_CWENR2_CWEN91_MASK) 3420 3421 #define ADC_CWENR2_CWEN92_MASK (0x10000000U) 3422 #define ADC_CWENR2_CWEN92_SHIFT (28U) 3423 #define ADC_CWENR2_CWEN92_WIDTH (1U) 3424 #define ADC_CWENR2_CWEN92(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN92_SHIFT)) & ADC_CWENR2_CWEN92_MASK) 3425 3426 #define ADC_CWENR2_CWEN93_MASK (0x20000000U) 3427 #define ADC_CWENR2_CWEN93_SHIFT (29U) 3428 #define ADC_CWENR2_CWEN93_WIDTH (1U) 3429 #define ADC_CWENR2_CWEN93(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN93_SHIFT)) & ADC_CWENR2_CWEN93_MASK) 3430 3431 #define ADC_CWENR2_CWEN94_MASK (0x40000000U) 3432 #define ADC_CWENR2_CWEN94_SHIFT (30U) 3433 #define ADC_CWENR2_CWEN94_WIDTH (1U) 3434 #define ADC_CWENR2_CWEN94(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN94_SHIFT)) & ADC_CWENR2_CWEN94_MASK) 3435 3436 #define ADC_CWENR2_CWEN95_MASK (0x80000000U) 3437 #define ADC_CWENR2_CWEN95_SHIFT (31U) 3438 #define ADC_CWENR2_CWEN95_WIDTH (1U) 3439 #define ADC_CWENR2_CWEN95(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR2_CWEN95_SHIFT)) & ADC_CWENR2_CWEN95_MASK) 3440 /*! @} */ 3441 3442 /*! @name AWORR0 - Analog Watchdog Out Of Range For Precision Inputs */ 3443 /*! @{ */ 3444 3445 #define ADC_AWORR0_AWOR_CH0_MASK (0x1U) 3446 #define ADC_AWORR0_AWOR_CH0_SHIFT (0U) 3447 #define ADC_AWORR0_AWOR_CH0_WIDTH (1U) 3448 #define ADC_AWORR0_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK) 3449 3450 #define ADC_AWORR0_AWOR_CH1_MASK (0x2U) 3451 #define ADC_AWORR0_AWOR_CH1_SHIFT (1U) 3452 #define ADC_AWORR0_AWOR_CH1_WIDTH (1U) 3453 #define ADC_AWORR0_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK) 3454 3455 #define ADC_AWORR0_AWOR_CH2_MASK (0x4U) 3456 #define ADC_AWORR0_AWOR_CH2_SHIFT (2U) 3457 #define ADC_AWORR0_AWOR_CH2_WIDTH (1U) 3458 #define ADC_AWORR0_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK) 3459 3460 #define ADC_AWORR0_AWOR_CH3_MASK (0x8U) 3461 #define ADC_AWORR0_AWOR_CH3_SHIFT (3U) 3462 #define ADC_AWORR0_AWOR_CH3_WIDTH (1U) 3463 #define ADC_AWORR0_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK) 3464 3465 #define ADC_AWORR0_AWOR_CH4_MASK (0x10U) 3466 #define ADC_AWORR0_AWOR_CH4_SHIFT (4U) 3467 #define ADC_AWORR0_AWOR_CH4_WIDTH (1U) 3468 #define ADC_AWORR0_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK) 3469 3470 #define ADC_AWORR0_AWOR_CH5_MASK (0x20U) 3471 #define ADC_AWORR0_AWOR_CH5_SHIFT (5U) 3472 #define ADC_AWORR0_AWOR_CH5_WIDTH (1U) 3473 #define ADC_AWORR0_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK) 3474 3475 #define ADC_AWORR0_AWOR_CH6_MASK (0x40U) 3476 #define ADC_AWORR0_AWOR_CH6_SHIFT (6U) 3477 #define ADC_AWORR0_AWOR_CH6_WIDTH (1U) 3478 #define ADC_AWORR0_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK) 3479 3480 #define ADC_AWORR0_AWOR_CH7_MASK (0x80U) 3481 #define ADC_AWORR0_AWOR_CH7_SHIFT (7U) 3482 #define ADC_AWORR0_AWOR_CH7_WIDTH (1U) 3483 #define ADC_AWORR0_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK) 3484 /*! @} */ 3485 3486 /*! @name AWORR1 - Analog Watchdog Out Of Range For Standard Inputs */ 3487 /*! @{ */ 3488 3489 #define ADC_AWORR1_AWOR_CH0_MASK (0x1U) 3490 #define ADC_AWORR1_AWOR_CH0_SHIFT (0U) 3491 #define ADC_AWORR1_AWOR_CH0_WIDTH (1U) 3492 #define ADC_AWORR1_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH0_SHIFT)) & ADC_AWORR1_AWOR_CH0_MASK) 3493 3494 #define ADC_AWORR1_AWOR_CH1_MASK (0x2U) 3495 #define ADC_AWORR1_AWOR_CH1_SHIFT (1U) 3496 #define ADC_AWORR1_AWOR_CH1_WIDTH (1U) 3497 #define ADC_AWORR1_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH1_SHIFT)) & ADC_AWORR1_AWOR_CH1_MASK) 3498 3499 #define ADC_AWORR1_AWOR_CH2_MASK (0x4U) 3500 #define ADC_AWORR1_AWOR_CH2_SHIFT (2U) 3501 #define ADC_AWORR1_AWOR_CH2_WIDTH (1U) 3502 #define ADC_AWORR1_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH2_SHIFT)) & ADC_AWORR1_AWOR_CH2_MASK) 3503 3504 #define ADC_AWORR1_AWOR_CH3_MASK (0x8U) 3505 #define ADC_AWORR1_AWOR_CH3_SHIFT (3U) 3506 #define ADC_AWORR1_AWOR_CH3_WIDTH (1U) 3507 #define ADC_AWORR1_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH3_SHIFT)) & ADC_AWORR1_AWOR_CH3_MASK) 3508 3509 #define ADC_AWORR1_AWOR_CH4_MASK (0x10U) 3510 #define ADC_AWORR1_AWOR_CH4_SHIFT (4U) 3511 #define ADC_AWORR1_AWOR_CH4_WIDTH (1U) 3512 #define ADC_AWORR1_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH4_SHIFT)) & ADC_AWORR1_AWOR_CH4_MASK) 3513 3514 #define ADC_AWORR1_AWOR_CH5_MASK (0x20U) 3515 #define ADC_AWORR1_AWOR_CH5_SHIFT (5U) 3516 #define ADC_AWORR1_AWOR_CH5_WIDTH (1U) 3517 #define ADC_AWORR1_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH5_SHIFT)) & ADC_AWORR1_AWOR_CH5_MASK) 3518 3519 #define ADC_AWORR1_AWOR_CH6_MASK (0x40U) 3520 #define ADC_AWORR1_AWOR_CH6_SHIFT (6U) 3521 #define ADC_AWORR1_AWOR_CH6_WIDTH (1U) 3522 #define ADC_AWORR1_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH6_SHIFT)) & ADC_AWORR1_AWOR_CH6_MASK) 3523 3524 #define ADC_AWORR1_AWOR_CH7_MASK (0x80U) 3525 #define ADC_AWORR1_AWOR_CH7_SHIFT (7U) 3526 #define ADC_AWORR1_AWOR_CH7_WIDTH (1U) 3527 #define ADC_AWORR1_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH7_SHIFT)) & ADC_AWORR1_AWOR_CH7_MASK) 3528 3529 #define ADC_AWORR1_AWOR_CH8_MASK (0x100U) 3530 #define ADC_AWORR1_AWOR_CH8_SHIFT (8U) 3531 #define ADC_AWORR1_AWOR_CH8_WIDTH (1U) 3532 #define ADC_AWORR1_AWOR_CH8(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH8_SHIFT)) & ADC_AWORR1_AWOR_CH8_MASK) 3533 3534 #define ADC_AWORR1_AWOR_CH9_MASK (0x200U) 3535 #define ADC_AWORR1_AWOR_CH9_SHIFT (9U) 3536 #define ADC_AWORR1_AWOR_CH9_WIDTH (1U) 3537 #define ADC_AWORR1_AWOR_CH9(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH9_SHIFT)) & ADC_AWORR1_AWOR_CH9_MASK) 3538 3539 #define ADC_AWORR1_AWOR_CH10_MASK (0x400U) 3540 #define ADC_AWORR1_AWOR_CH10_SHIFT (10U) 3541 #define ADC_AWORR1_AWOR_CH10_WIDTH (1U) 3542 #define ADC_AWORR1_AWOR_CH10(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH10_SHIFT)) & ADC_AWORR1_AWOR_CH10_MASK) 3543 3544 #define ADC_AWORR1_AWOR_CH11_MASK (0x800U) 3545 #define ADC_AWORR1_AWOR_CH11_SHIFT (11U) 3546 #define ADC_AWORR1_AWOR_CH11_WIDTH (1U) 3547 #define ADC_AWORR1_AWOR_CH11(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH11_SHIFT)) & ADC_AWORR1_AWOR_CH11_MASK) 3548 3549 #define ADC_AWORR1_AWOR_CH12_MASK (0x1000U) 3550 #define ADC_AWORR1_AWOR_CH12_SHIFT (12U) 3551 #define ADC_AWORR1_AWOR_CH12_WIDTH (1U) 3552 #define ADC_AWORR1_AWOR_CH12(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH12_SHIFT)) & ADC_AWORR1_AWOR_CH12_MASK) 3553 3554 #define ADC_AWORR1_AWOR_CH13_MASK (0x2000U) 3555 #define ADC_AWORR1_AWOR_CH13_SHIFT (13U) 3556 #define ADC_AWORR1_AWOR_CH13_WIDTH (1U) 3557 #define ADC_AWORR1_AWOR_CH13(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH13_SHIFT)) & ADC_AWORR1_AWOR_CH13_MASK) 3558 3559 #define ADC_AWORR1_AWOR_CH14_MASK (0x4000U) 3560 #define ADC_AWORR1_AWOR_CH14_SHIFT (14U) 3561 #define ADC_AWORR1_AWOR_CH14_WIDTH (1U) 3562 #define ADC_AWORR1_AWOR_CH14(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH14_SHIFT)) & ADC_AWORR1_AWOR_CH14_MASK) 3563 3564 #define ADC_AWORR1_AWOR_CH15_MASK (0x8000U) 3565 #define ADC_AWORR1_AWOR_CH15_SHIFT (15U) 3566 #define ADC_AWORR1_AWOR_CH15_WIDTH (1U) 3567 #define ADC_AWORR1_AWOR_CH15(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH15_SHIFT)) & ADC_AWORR1_AWOR_CH15_MASK) 3568 3569 #define ADC_AWORR1_AWOR_CH16_MASK (0x10000U) 3570 #define ADC_AWORR1_AWOR_CH16_SHIFT (16U) 3571 #define ADC_AWORR1_AWOR_CH16_WIDTH (1U) 3572 #define ADC_AWORR1_AWOR_CH16(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH16_SHIFT)) & ADC_AWORR1_AWOR_CH16_MASK) 3573 3574 #define ADC_AWORR1_AWOR_CH17_MASK (0x20000U) 3575 #define ADC_AWORR1_AWOR_CH17_SHIFT (17U) 3576 #define ADC_AWORR1_AWOR_CH17_WIDTH (1U) 3577 #define ADC_AWORR1_AWOR_CH17(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH17_SHIFT)) & ADC_AWORR1_AWOR_CH17_MASK) 3578 3579 #define ADC_AWORR1_AWOR_CH18_MASK (0x40000U) 3580 #define ADC_AWORR1_AWOR_CH18_SHIFT (18U) 3581 #define ADC_AWORR1_AWOR_CH18_WIDTH (1U) 3582 #define ADC_AWORR1_AWOR_CH18(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH18_SHIFT)) & ADC_AWORR1_AWOR_CH18_MASK) 3583 3584 #define ADC_AWORR1_AWOR_CH19_MASK (0x80000U) 3585 #define ADC_AWORR1_AWOR_CH19_SHIFT (19U) 3586 #define ADC_AWORR1_AWOR_CH19_WIDTH (1U) 3587 #define ADC_AWORR1_AWOR_CH19(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH19_SHIFT)) & ADC_AWORR1_AWOR_CH19_MASK) 3588 3589 #define ADC_AWORR1_AWOR_CH20_MASK (0x100000U) 3590 #define ADC_AWORR1_AWOR_CH20_SHIFT (20U) 3591 #define ADC_AWORR1_AWOR_CH20_WIDTH (1U) 3592 #define ADC_AWORR1_AWOR_CH20(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH20_SHIFT)) & ADC_AWORR1_AWOR_CH20_MASK) 3593 3594 #define ADC_AWORR1_AWOR_CH21_MASK (0x200000U) 3595 #define ADC_AWORR1_AWOR_CH21_SHIFT (21U) 3596 #define ADC_AWORR1_AWOR_CH21_WIDTH (1U) 3597 #define ADC_AWORR1_AWOR_CH21(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH21_SHIFT)) & ADC_AWORR1_AWOR_CH21_MASK) 3598 3599 #define ADC_AWORR1_AWOR_CH22_MASK (0x400000U) 3600 #define ADC_AWORR1_AWOR_CH22_SHIFT (22U) 3601 #define ADC_AWORR1_AWOR_CH22_WIDTH (1U) 3602 #define ADC_AWORR1_AWOR_CH22(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH22_SHIFT)) & ADC_AWORR1_AWOR_CH22_MASK) 3603 3604 #define ADC_AWORR1_AWOR_CH23_MASK (0x800000U) 3605 #define ADC_AWORR1_AWOR_CH23_SHIFT (23U) 3606 #define ADC_AWORR1_AWOR_CH23_WIDTH (1U) 3607 #define ADC_AWORR1_AWOR_CH23(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH23_SHIFT)) & ADC_AWORR1_AWOR_CH23_MASK) 3608 /*! @} */ 3609 3610 /*! @name AWORR2 - Analog Watchdog Out Of Range For External Inputs */ 3611 /*! @{ */ 3612 3613 #define ADC_AWORR2_AWOR_CH0_MASK (0x1U) 3614 #define ADC_AWORR2_AWOR_CH0_SHIFT (0U) 3615 #define ADC_AWORR2_AWOR_CH0_WIDTH (1U) 3616 #define ADC_AWORR2_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH0_SHIFT)) & ADC_AWORR2_AWOR_CH0_MASK) 3617 3618 #define ADC_AWORR2_AWOR_CH1_MASK (0x2U) 3619 #define ADC_AWORR2_AWOR_CH1_SHIFT (1U) 3620 #define ADC_AWORR2_AWOR_CH1_WIDTH (1U) 3621 #define ADC_AWORR2_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH1_SHIFT)) & ADC_AWORR2_AWOR_CH1_MASK) 3622 3623 #define ADC_AWORR2_AWOR_CH2_MASK (0x4U) 3624 #define ADC_AWORR2_AWOR_CH2_SHIFT (2U) 3625 #define ADC_AWORR2_AWOR_CH2_WIDTH (1U) 3626 #define ADC_AWORR2_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH2_SHIFT)) & ADC_AWORR2_AWOR_CH2_MASK) 3627 3628 #define ADC_AWORR2_AWOR_CH3_MASK (0x8U) 3629 #define ADC_AWORR2_AWOR_CH3_SHIFT (3U) 3630 #define ADC_AWORR2_AWOR_CH3_WIDTH (1U) 3631 #define ADC_AWORR2_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH3_SHIFT)) & ADC_AWORR2_AWOR_CH3_MASK) 3632 3633 #define ADC_AWORR2_AWOR_CH4_MASK (0x10U) 3634 #define ADC_AWORR2_AWOR_CH4_SHIFT (4U) 3635 #define ADC_AWORR2_AWOR_CH4_WIDTH (1U) 3636 #define ADC_AWORR2_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH4_SHIFT)) & ADC_AWORR2_AWOR_CH4_MASK) 3637 3638 #define ADC_AWORR2_AWOR_CH5_MASK (0x20U) 3639 #define ADC_AWORR2_AWOR_CH5_SHIFT (5U) 3640 #define ADC_AWORR2_AWOR_CH5_WIDTH (1U) 3641 #define ADC_AWORR2_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH5_SHIFT)) & ADC_AWORR2_AWOR_CH5_MASK) 3642 3643 #define ADC_AWORR2_AWOR_CH6_MASK (0x40U) 3644 #define ADC_AWORR2_AWOR_CH6_SHIFT (6U) 3645 #define ADC_AWORR2_AWOR_CH6_WIDTH (1U) 3646 #define ADC_AWORR2_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH6_SHIFT)) & ADC_AWORR2_AWOR_CH6_MASK) 3647 3648 #define ADC_AWORR2_AWOR_CH7_MASK (0x80U) 3649 #define ADC_AWORR2_AWOR_CH7_SHIFT (7U) 3650 #define ADC_AWORR2_AWOR_CH7_WIDTH (1U) 3651 #define ADC_AWORR2_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH7_SHIFT)) & ADC_AWORR2_AWOR_CH7_MASK) 3652 3653 #define ADC_AWORR2_AWOR_CH8_MASK (0x100U) 3654 #define ADC_AWORR2_AWOR_CH8_SHIFT (8U) 3655 #define ADC_AWORR2_AWOR_CH8_WIDTH (1U) 3656 #define ADC_AWORR2_AWOR_CH8(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH8_SHIFT)) & ADC_AWORR2_AWOR_CH8_MASK) 3657 3658 #define ADC_AWORR2_AWOR_CH9_MASK (0x200U) 3659 #define ADC_AWORR2_AWOR_CH9_SHIFT (9U) 3660 #define ADC_AWORR2_AWOR_CH9_WIDTH (1U) 3661 #define ADC_AWORR2_AWOR_CH9(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH9_SHIFT)) & ADC_AWORR2_AWOR_CH9_MASK) 3662 3663 #define ADC_AWORR2_AWOR_CH10_MASK (0x400U) 3664 #define ADC_AWORR2_AWOR_CH10_SHIFT (10U) 3665 #define ADC_AWORR2_AWOR_CH10_WIDTH (1U) 3666 #define ADC_AWORR2_AWOR_CH10(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH10_SHIFT)) & ADC_AWORR2_AWOR_CH10_MASK) 3667 3668 #define ADC_AWORR2_AWOR_CH11_MASK (0x800U) 3669 #define ADC_AWORR2_AWOR_CH11_SHIFT (11U) 3670 #define ADC_AWORR2_AWOR_CH11_WIDTH (1U) 3671 #define ADC_AWORR2_AWOR_CH11(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH11_SHIFT)) & ADC_AWORR2_AWOR_CH11_MASK) 3672 3673 #define ADC_AWORR2_AWOR_CH12_MASK (0x1000U) 3674 #define ADC_AWORR2_AWOR_CH12_SHIFT (12U) 3675 #define ADC_AWORR2_AWOR_CH12_WIDTH (1U) 3676 #define ADC_AWORR2_AWOR_CH12(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH12_SHIFT)) & ADC_AWORR2_AWOR_CH12_MASK) 3677 3678 #define ADC_AWORR2_AWOR_CH13_MASK (0x2000U) 3679 #define ADC_AWORR2_AWOR_CH13_SHIFT (13U) 3680 #define ADC_AWORR2_AWOR_CH13_WIDTH (1U) 3681 #define ADC_AWORR2_AWOR_CH13(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH13_SHIFT)) & ADC_AWORR2_AWOR_CH13_MASK) 3682 3683 #define ADC_AWORR2_AWOR_CH14_MASK (0x4000U) 3684 #define ADC_AWORR2_AWOR_CH14_SHIFT (14U) 3685 #define ADC_AWORR2_AWOR_CH14_WIDTH (1U) 3686 #define ADC_AWORR2_AWOR_CH14(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH14_SHIFT)) & ADC_AWORR2_AWOR_CH14_MASK) 3687 3688 #define ADC_AWORR2_AWOR_CH15_MASK (0x8000U) 3689 #define ADC_AWORR2_AWOR_CH15_SHIFT (15U) 3690 #define ADC_AWORR2_AWOR_CH15_WIDTH (1U) 3691 #define ADC_AWORR2_AWOR_CH15(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH15_SHIFT)) & ADC_AWORR2_AWOR_CH15_MASK) 3692 3693 #define ADC_AWORR2_AWOR_CH16_MASK (0x10000U) 3694 #define ADC_AWORR2_AWOR_CH16_SHIFT (16U) 3695 #define ADC_AWORR2_AWOR_CH16_WIDTH (1U) 3696 #define ADC_AWORR2_AWOR_CH16(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH16_SHIFT)) & ADC_AWORR2_AWOR_CH16_MASK) 3697 3698 #define ADC_AWORR2_AWOR_CH17_MASK (0x20000U) 3699 #define ADC_AWORR2_AWOR_CH17_SHIFT (17U) 3700 #define ADC_AWORR2_AWOR_CH17_WIDTH (1U) 3701 #define ADC_AWORR2_AWOR_CH17(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH17_SHIFT)) & ADC_AWORR2_AWOR_CH17_MASK) 3702 3703 #define ADC_AWORR2_AWOR_CH18_MASK (0x40000U) 3704 #define ADC_AWORR2_AWOR_CH18_SHIFT (18U) 3705 #define ADC_AWORR2_AWOR_CH18_WIDTH (1U) 3706 #define ADC_AWORR2_AWOR_CH18(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH18_SHIFT)) & ADC_AWORR2_AWOR_CH18_MASK) 3707 3708 #define ADC_AWORR2_AWOR_CH19_MASK (0x80000U) 3709 #define ADC_AWORR2_AWOR_CH19_SHIFT (19U) 3710 #define ADC_AWORR2_AWOR_CH19_WIDTH (1U) 3711 #define ADC_AWORR2_AWOR_CH19(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH19_SHIFT)) & ADC_AWORR2_AWOR_CH19_MASK) 3712 3713 #define ADC_AWORR2_AWOR_CH20_MASK (0x100000U) 3714 #define ADC_AWORR2_AWOR_CH20_SHIFT (20U) 3715 #define ADC_AWORR2_AWOR_CH20_WIDTH (1U) 3716 #define ADC_AWORR2_AWOR_CH20(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH20_SHIFT)) & ADC_AWORR2_AWOR_CH20_MASK) 3717 3718 #define ADC_AWORR2_AWOR_CH21_MASK (0x200000U) 3719 #define ADC_AWORR2_AWOR_CH21_SHIFT (21U) 3720 #define ADC_AWORR2_AWOR_CH21_WIDTH (1U) 3721 #define ADC_AWORR2_AWOR_CH21(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH21_SHIFT)) & ADC_AWORR2_AWOR_CH21_MASK) 3722 3723 #define ADC_AWORR2_AWOR_CH22_MASK (0x400000U) 3724 #define ADC_AWORR2_AWOR_CH22_SHIFT (22U) 3725 #define ADC_AWORR2_AWOR_CH22_WIDTH (1U) 3726 #define ADC_AWORR2_AWOR_CH22(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH22_SHIFT)) & ADC_AWORR2_AWOR_CH22_MASK) 3727 3728 #define ADC_AWORR2_AWOR_CH23_MASK (0x800000U) 3729 #define ADC_AWORR2_AWOR_CH23_SHIFT (23U) 3730 #define ADC_AWORR2_AWOR_CH23_WIDTH (1U) 3731 #define ADC_AWORR2_AWOR_CH23(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH23_SHIFT)) & ADC_AWORR2_AWOR_CH23_MASK) 3732 3733 #define ADC_AWORR2_AWOR_CH24_MASK (0x1000000U) 3734 #define ADC_AWORR2_AWOR_CH24_SHIFT (24U) 3735 #define ADC_AWORR2_AWOR_CH24_WIDTH (1U) 3736 #define ADC_AWORR2_AWOR_CH24(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH24_SHIFT)) & ADC_AWORR2_AWOR_CH24_MASK) 3737 3738 #define ADC_AWORR2_AWOR_CH25_MASK (0x2000000U) 3739 #define ADC_AWORR2_AWOR_CH25_SHIFT (25U) 3740 #define ADC_AWORR2_AWOR_CH25_WIDTH (1U) 3741 #define ADC_AWORR2_AWOR_CH25(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH25_SHIFT)) & ADC_AWORR2_AWOR_CH25_MASK) 3742 3743 #define ADC_AWORR2_AWOR_CH26_MASK (0x4000000U) 3744 #define ADC_AWORR2_AWOR_CH26_SHIFT (26U) 3745 #define ADC_AWORR2_AWOR_CH26_WIDTH (1U) 3746 #define ADC_AWORR2_AWOR_CH26(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH26_SHIFT)) & ADC_AWORR2_AWOR_CH26_MASK) 3747 3748 #define ADC_AWORR2_AWOR_CH27_MASK (0x8000000U) 3749 #define ADC_AWORR2_AWOR_CH27_SHIFT (27U) 3750 #define ADC_AWORR2_AWOR_CH27_WIDTH (1U) 3751 #define ADC_AWORR2_AWOR_CH27(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH27_SHIFT)) & ADC_AWORR2_AWOR_CH27_MASK) 3752 3753 #define ADC_AWORR2_AWOR_CH28_MASK (0x10000000U) 3754 #define ADC_AWORR2_AWOR_CH28_SHIFT (28U) 3755 #define ADC_AWORR2_AWOR_CH28_WIDTH (1U) 3756 #define ADC_AWORR2_AWOR_CH28(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH28_SHIFT)) & ADC_AWORR2_AWOR_CH28_MASK) 3757 3758 #define ADC_AWORR2_AWOR_CH29_MASK (0x20000000U) 3759 #define ADC_AWORR2_AWOR_CH29_SHIFT (29U) 3760 #define ADC_AWORR2_AWOR_CH29_WIDTH (1U) 3761 #define ADC_AWORR2_AWOR_CH29(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH29_SHIFT)) & ADC_AWORR2_AWOR_CH29_MASK) 3762 3763 #define ADC_AWORR2_AWOR_CH30_MASK (0x40000000U) 3764 #define ADC_AWORR2_AWOR_CH30_SHIFT (30U) 3765 #define ADC_AWORR2_AWOR_CH30_WIDTH (1U) 3766 #define ADC_AWORR2_AWOR_CH30(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH30_SHIFT)) & ADC_AWORR2_AWOR_CH30_MASK) 3767 3768 #define ADC_AWORR2_AWOR_CH31_MASK (0x80000000U) 3769 #define ADC_AWORR2_AWOR_CH31_SHIFT (31U) 3770 #define ADC_AWORR2_AWOR_CH31_WIDTH (1U) 3771 #define ADC_AWORR2_AWOR_CH31(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR2_AWOR_CH31_SHIFT)) & ADC_AWORR2_AWOR_CH31_MASK) 3772 /*! @} */ 3773 3774 /*! @name STCR1 - Self-Test Configuration 1 */ 3775 /*! @{ */ 3776 3777 #define ADC_STCR1_INPSAMP_S_MASK (0xFF00U) 3778 #define ADC_STCR1_INPSAMP_S_SHIFT (8U) 3779 #define ADC_STCR1_INPSAMP_S_WIDTH (8U) 3780 #define ADC_STCR1_INPSAMP_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_S_SHIFT)) & ADC_STCR1_INPSAMP_S_MASK) 3781 3782 #define ADC_STCR1_INPSAMP_C_MASK (0xFF000000U) 3783 #define ADC_STCR1_INPSAMP_C_SHIFT (24U) 3784 #define ADC_STCR1_INPSAMP_C_WIDTH (8U) 3785 #define ADC_STCR1_INPSAMP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_C_SHIFT)) & ADC_STCR1_INPSAMP_C_MASK) 3786 /*! @} */ 3787 3788 /*! @name STCR2 - Self-Test Configuration 2 */ 3789 /*! @{ */ 3790 3791 #define ADC_STCR2_FMA_S_MASK (0x1U) 3792 #define ADC_STCR2_FMA_S_SHIFT (0U) 3793 #define ADC_STCR2_FMA_S_WIDTH (1U) 3794 #define ADC_STCR2_FMA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_S_SHIFT)) & ADC_STCR2_FMA_S_MASK) 3795 3796 #define ADC_STCR2_FMA_C_MASK (0x4U) 3797 #define ADC_STCR2_FMA_C_SHIFT (2U) 3798 #define ADC_STCR2_FMA_C_WIDTH (1U) 3799 #define ADC_STCR2_FMA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_C_SHIFT)) & ADC_STCR2_FMA_C_MASK) 3800 3801 #define ADC_STCR2_FMA_WDTERR_MASK (0x8U) 3802 #define ADC_STCR2_FMA_WDTERR_SHIFT (3U) 3803 #define ADC_STCR2_FMA_WDTERR_WIDTH (1U) 3804 #define ADC_STCR2_FMA_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDTERR_SHIFT)) & ADC_STCR2_FMA_WDTERR_MASK) 3805 3806 #define ADC_STCR2_FMA_WDSERR_MASK (0x10U) 3807 #define ADC_STCR2_FMA_WDSERR_SHIFT (4U) 3808 #define ADC_STCR2_FMA_WDSERR_WIDTH (1U) 3809 #define ADC_STCR2_FMA_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDSERR_SHIFT)) & ADC_STCR2_FMA_WDSERR_MASK) 3810 3811 #define ADC_STCR2_EN_MASK (0x80U) 3812 #define ADC_STCR2_EN_SHIFT (7U) 3813 #define ADC_STCR2_EN_WIDTH (1U) 3814 #define ADC_STCR2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_EN_SHIFT)) & ADC_STCR2_EN_MASK) 3815 3816 #define ADC_STCR2_MSKERR_S0_MASK (0x800U) 3817 #define ADC_STCR2_MSKERR_S0_SHIFT (11U) 3818 #define ADC_STCR2_MSKERR_S0_WIDTH (1U) 3819 #define ADC_STCR2_MSKERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S0_SHIFT)) & ADC_STCR2_MSKERR_S0_MASK) 3820 3821 #define ADC_STCR2_MSKERR_S1_MASK (0x1000U) 3822 #define ADC_STCR2_MSKERR_S1_SHIFT (12U) 3823 #define ADC_STCR2_MSKERR_S1_WIDTH (1U) 3824 #define ADC_STCR2_MSKERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S1_SHIFT)) & ADC_STCR2_MSKERR_S1_MASK) 3825 3826 #define ADC_STCR2_MSKERR_S2_MASK (0x2000U) 3827 #define ADC_STCR2_MSKERR_S2_SHIFT (13U) 3828 #define ADC_STCR2_MSKERR_S2_WIDTH (1U) 3829 #define ADC_STCR2_MSKERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S2_SHIFT)) & ADC_STCR2_MSKERR_S2_MASK) 3830 3831 #define ADC_STCR2_MSKERR_C_MASK (0x8000U) 3832 #define ADC_STCR2_MSKERR_C_SHIFT (15U) 3833 #define ADC_STCR2_MSKERR_C_WIDTH (1U) 3834 #define ADC_STCR2_MSKERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_C_SHIFT)) & ADC_STCR2_MSKERR_C_MASK) 3835 3836 #define ADC_STCR2_MSKWDG_EOA_S_MASK (0x10000U) 3837 #define ADC_STCR2_MSKWDG_EOA_S_SHIFT (16U) 3838 #define ADC_STCR2_MSKWDG_EOA_S_WIDTH (1U) 3839 #define ADC_STCR2_MSKWDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_S_SHIFT)) & ADC_STCR2_MSKWDG_EOA_S_MASK) 3840 3841 #define ADC_STCR2_MSKWDG_EOA_C_MASK (0x40000U) 3842 #define ADC_STCR2_MSKWDG_EOA_C_SHIFT (18U) 3843 #define ADC_STCR2_MSKWDG_EOA_C_WIDTH (1U) 3844 #define ADC_STCR2_MSKWDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_C_SHIFT)) & ADC_STCR2_MSKWDG_EOA_C_MASK) 3845 3846 #define ADC_STCR2_MSKST_EOC_MASK (0x800000U) 3847 #define ADC_STCR2_MSKST_EOC_SHIFT (23U) 3848 #define ADC_STCR2_MSKST_EOC_WIDTH (1U) 3849 #define ADC_STCR2_MSKST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKST_EOC_SHIFT)) & ADC_STCR2_MSKST_EOC_MASK) 3850 3851 #define ADC_STCR2_MSKWDTERR_MASK (0x2000000U) 3852 #define ADC_STCR2_MSKWDTERR_SHIFT (25U) 3853 #define ADC_STCR2_MSKWDTERR_WIDTH (1U) 3854 #define ADC_STCR2_MSKWDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDTERR_SHIFT)) & ADC_STCR2_MSKWDTERR_MASK) 3855 3856 #define ADC_STCR2_SERR_MASK (0x4000000U) 3857 #define ADC_STCR2_SERR_SHIFT (26U) 3858 #define ADC_STCR2_SERR_WIDTH (1U) 3859 #define ADC_STCR2_SERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_SERR_SHIFT)) & ADC_STCR2_SERR_MASK) 3860 3861 #define ADC_STCR2_MSKWDSERR_MASK (0x8000000U) 3862 #define ADC_STCR2_MSKWDSERR_SHIFT (27U) 3863 #define ADC_STCR2_MSKWDSERR_WIDTH (1U) 3864 #define ADC_STCR2_MSKWDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDSERR_SHIFT)) & ADC_STCR2_MSKWDSERR_MASK) 3865 /*! @} */ 3866 3867 /*! @name STCR3 - Self-Test Configuration 3 */ 3868 /*! @{ */ 3869 3870 #define ADC_STCR3_MSTEP_MASK (0x1FU) 3871 #define ADC_STCR3_MSTEP_SHIFT (0U) 3872 #define ADC_STCR3_MSTEP_WIDTH (5U) 3873 #define ADC_STCR3_MSTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_MSTEP_SHIFT)) & ADC_STCR3_MSTEP_MASK) 3874 3875 #define ADC_STCR3_ALG_MASK (0x300U) 3876 #define ADC_STCR3_ALG_SHIFT (8U) 3877 #define ADC_STCR3_ALG_WIDTH (2U) 3878 #define ADC_STCR3_ALG(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_ALG_SHIFT)) & ADC_STCR3_ALG_MASK) 3879 /*! @} */ 3880 3881 /*! @name STBRR - Self-Test Baud Rate */ 3882 /*! @{ */ 3883 3884 #define ADC_STBRR_BR_MASK (0xFFU) 3885 #define ADC_STBRR_BR_SHIFT (0U) 3886 #define ADC_STBRR_BR_WIDTH (8U) 3887 #define ADC_STBRR_BR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_BR_SHIFT)) & ADC_STBRR_BR_MASK) 3888 3889 #define ADC_STBRR_WDT_MASK (0x70000U) 3890 #define ADC_STBRR_WDT_SHIFT (16U) 3891 #define ADC_STBRR_WDT_WIDTH (3U) 3892 #define ADC_STBRR_WDT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_WDT_SHIFT)) & ADC_STBRR_WDT_MASK) 3893 /*! @} */ 3894 3895 /*! @name STSR1 - Self-Test Status 1 */ 3896 /*! @{ */ 3897 3898 #define ADC_STSR1_STEP_C_MASK (0x3E0U) 3899 #define ADC_STSR1_STEP_C_SHIFT (5U) 3900 #define ADC_STSR1_STEP_C_WIDTH (5U) 3901 #define ADC_STSR1_STEP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_STEP_C_SHIFT)) & ADC_STSR1_STEP_C_MASK) 3902 3903 #define ADC_STSR1_ERR_S0_MASK (0x800U) 3904 #define ADC_STSR1_ERR_S0_SHIFT (11U) 3905 #define ADC_STSR1_ERR_S0_WIDTH (1U) 3906 #define ADC_STSR1_ERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK) 3907 3908 #define ADC_STSR1_ERR_S1_MASK (0x1000U) 3909 #define ADC_STSR1_ERR_S1_SHIFT (12U) 3910 #define ADC_STSR1_ERR_S1_WIDTH (1U) 3911 #define ADC_STSR1_ERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK) 3912 3913 #define ADC_STSR1_ERR_S2_MASK (0x2000U) 3914 #define ADC_STSR1_ERR_S2_SHIFT (13U) 3915 #define ADC_STSR1_ERR_S2_WIDTH (1U) 3916 #define ADC_STSR1_ERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK) 3917 3918 #define ADC_STSR1_ERR_C_MASK (0x8000U) 3919 #define ADC_STSR1_ERR_C_SHIFT (15U) 3920 #define ADC_STSR1_ERR_C_WIDTH (1U) 3921 #define ADC_STSR1_ERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK) 3922 3923 #define ADC_STSR1_WDG_EOA_S_MASK (0x10000U) 3924 #define ADC_STSR1_WDG_EOA_S_SHIFT (16U) 3925 #define ADC_STSR1_WDG_EOA_S_WIDTH (1U) 3926 #define ADC_STSR1_WDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK) 3927 3928 #define ADC_STSR1_WDG_EOA_C_MASK (0x40000U) 3929 #define ADC_STSR1_WDG_EOA_C_SHIFT (18U) 3930 #define ADC_STSR1_WDG_EOA_C_WIDTH (1U) 3931 #define ADC_STSR1_WDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK) 3932 3933 #define ADC_STSR1_ST_EOC_MASK (0x800000U) 3934 #define ADC_STSR1_ST_EOC_SHIFT (23U) 3935 #define ADC_STSR1_ST_EOC_WIDTH (1U) 3936 #define ADC_STSR1_ST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK) 3937 3938 #define ADC_STSR1_OVERWR_MASK (0x1000000U) 3939 #define ADC_STSR1_OVERWR_SHIFT (24U) 3940 #define ADC_STSR1_OVERWR_WIDTH (1U) 3941 #define ADC_STSR1_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK) 3942 3943 #define ADC_STSR1_WDTERR_MASK (0x2000000U) 3944 #define ADC_STSR1_WDTERR_SHIFT (25U) 3945 #define ADC_STSR1_WDTERR_WIDTH (1U) 3946 #define ADC_STSR1_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK) 3947 3948 #define ADC_STSR1_WDSERR_MASK (0x8000000U) 3949 #define ADC_STSR1_WDSERR_SHIFT (27U) 3950 #define ADC_STSR1_WDSERR_WIDTH (1U) 3951 #define ADC_STSR1_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK) 3952 /*! @} */ 3953 3954 /*! @name STSR2 - Self-Test Status 2 */ 3955 /*! @{ */ 3956 3957 #define ADC_STSR2_DATA0_MASK (0x7FFFU) 3958 #define ADC_STSR2_DATA0_SHIFT (0U) 3959 #define ADC_STSR2_DATA0_WIDTH (15U) 3960 #define ADC_STSR2_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA0_SHIFT)) & ADC_STSR2_DATA0_MASK) 3961 /*! @} */ 3962 3963 /*! @name STSR3 - Self-Test Status 3 */ 3964 /*! @{ */ 3965 3966 #define ADC_STSR3_DATA0_MASK (0x7FFFU) 3967 #define ADC_STSR3_DATA0_SHIFT (0U) 3968 #define ADC_STSR3_DATA0_WIDTH (15U) 3969 #define ADC_STSR3_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA0_SHIFT)) & ADC_STSR3_DATA0_MASK) 3970 3971 #define ADC_STSR3_DATA1_MASK (0x7FFF0000U) 3972 #define ADC_STSR3_DATA1_SHIFT (16U) 3973 #define ADC_STSR3_DATA1_WIDTH (15U) 3974 #define ADC_STSR3_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA1_SHIFT)) & ADC_STSR3_DATA1_MASK) 3975 /*! @} */ 3976 3977 /*! @name STSR4 - Self-Test Status 4 */ 3978 /*! @{ */ 3979 3980 #define ADC_STSR4_DATA1_MASK (0x7FFF0000U) 3981 #define ADC_STSR4_DATA1_SHIFT (16U) 3982 #define ADC_STSR4_DATA1_WIDTH (15U) 3983 #define ADC_STSR4_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR4_DATA1_SHIFT)) & ADC_STSR4_DATA1_MASK) 3984 /*! @} */ 3985 3986 /*! @name STDR1 - Self-Test Conversion Data 1 */ 3987 /*! @{ */ 3988 3989 #define ADC_STDR1_TCDATA_MASK (0x7FFFU) 3990 #define ADC_STDR1_TCDATA_SHIFT (0U) 3991 #define ADC_STDR1_TCDATA_WIDTH (15U) 3992 #define ADC_STDR1_TCDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_TCDATA_SHIFT)) & ADC_STDR1_TCDATA_MASK) 3993 3994 #define ADC_STDR1_OWERWR_MASK (0x40000U) 3995 #define ADC_STDR1_OWERWR_SHIFT (18U) 3996 #define ADC_STDR1_OWERWR_WIDTH (1U) 3997 #define ADC_STDR1_OWERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_OWERWR_SHIFT)) & ADC_STDR1_OWERWR_MASK) 3998 3999 #define ADC_STDR1_VALID_MASK (0x80000U) 4000 #define ADC_STDR1_VALID_SHIFT (19U) 4001 #define ADC_STDR1_VALID_WIDTH (1U) 4002 #define ADC_STDR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_VALID_SHIFT)) & ADC_STDR1_VALID_MASK) 4003 /*! @} */ 4004 4005 /*! @name STAW0R - Self-Test Analog Watchdog S0 */ 4006 /*! @{ */ 4007 4008 #define ADC_STAW0R_THRL_MASK (0x7FFFU) 4009 #define ADC_STAW0R_THRL_SHIFT (0U) 4010 #define ADC_STAW0R_THRL_WIDTH (15U) 4011 #define ADC_STAW0R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRL_SHIFT)) & ADC_STAW0R_THRL_MASK) 4012 4013 #define ADC_STAW0R_THRH_MASK (0x3FFF0000U) 4014 #define ADC_STAW0R_THRH_SHIFT (16U) 4015 #define ADC_STAW0R_THRH_WIDTH (14U) 4016 #define ADC_STAW0R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRH_SHIFT)) & ADC_STAW0R_THRH_MASK) 4017 4018 #define ADC_STAW0R_WDTE_MASK (0x40000000U) 4019 #define ADC_STAW0R_WDTE_SHIFT (30U) 4020 #define ADC_STAW0R_WDTE_WIDTH (1U) 4021 #define ADC_STAW0R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_WDTE_SHIFT)) & ADC_STAW0R_WDTE_MASK) 4022 4023 #define ADC_STAW0R_AWDE_MASK (0x80000000U) 4024 #define ADC_STAW0R_AWDE_SHIFT (31U) 4025 #define ADC_STAW0R_AWDE_WIDTH (1U) 4026 #define ADC_STAW0R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_AWDE_SHIFT)) & ADC_STAW0R_AWDE_MASK) 4027 /*! @} */ 4028 4029 /*! @name STAW1R - Self-Test Analog Watchdog S1 */ 4030 /*! @{ */ 4031 4032 #define ADC_STAW1R_THRL_MASK (0x7FFFU) 4033 #define ADC_STAW1R_THRL_SHIFT (0U) 4034 #define ADC_STAW1R_THRL_WIDTH (15U) 4035 #define ADC_STAW1R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1R_THRL_SHIFT)) & ADC_STAW1R_THRL_MASK) 4036 4037 #define ADC_STAW1R_AWDE_MASK (0x80000000U) 4038 #define ADC_STAW1R_AWDE_SHIFT (31U) 4039 #define ADC_STAW1R_AWDE_WIDTH (1U) 4040 #define ADC_STAW1R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1R_AWDE_SHIFT)) & ADC_STAW1R_AWDE_MASK) 4041 /*! @} */ 4042 4043 /*! @name STAW2R - Self-Test Analog Watchdog S2 */ 4044 /*! @{ */ 4045 4046 #define ADC_STAW2R_THRL_MASK (0x7FFFU) 4047 #define ADC_STAW2R_THRL_SHIFT (0U) 4048 #define ADC_STAW2R_THRL_WIDTH (15U) 4049 #define ADC_STAW2R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_THRL_SHIFT)) & ADC_STAW2R_THRL_MASK) 4050 4051 #define ADC_STAW2R_AWDE_MASK (0x80000000U) 4052 #define ADC_STAW2R_AWDE_SHIFT (31U) 4053 #define ADC_STAW2R_AWDE_WIDTH (1U) 4054 #define ADC_STAW2R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_AWDE_SHIFT)) & ADC_STAW2R_AWDE_MASK) 4055 /*! @} */ 4056 4057 /*! @name STAW4R - Self-Test Analog Watchdog C0 */ 4058 /*! @{ */ 4059 4060 #define ADC_STAW4R_THRL_MASK (0x7FFFU) 4061 #define ADC_STAW4R_THRL_SHIFT (0U) 4062 #define ADC_STAW4R_THRL_WIDTH (15U) 4063 #define ADC_STAW4R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRL_SHIFT)) & ADC_STAW4R_THRL_MASK) 4064 4065 #define ADC_STAW4R_THRH_MASK (0x3FFF0000U) 4066 #define ADC_STAW4R_THRH_SHIFT (16U) 4067 #define ADC_STAW4R_THRH_WIDTH (14U) 4068 #define ADC_STAW4R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRH_SHIFT)) & ADC_STAW4R_THRH_MASK) 4069 4070 #define ADC_STAW4R_WDTE_MASK (0x40000000U) 4071 #define ADC_STAW4R_WDTE_SHIFT (30U) 4072 #define ADC_STAW4R_WDTE_WIDTH (1U) 4073 #define ADC_STAW4R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_WDTE_SHIFT)) & ADC_STAW4R_WDTE_MASK) 4074 4075 #define ADC_STAW4R_AWDE_MASK (0x80000000U) 4076 #define ADC_STAW4R_AWDE_SHIFT (31U) 4077 #define ADC_STAW4R_AWDE_WIDTH (1U) 4078 #define ADC_STAW4R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_AWDE_SHIFT)) & ADC_STAW4R_AWDE_MASK) 4079 /*! @} */ 4080 4081 /*! @name STAW5R - Self-Test Analog Watchdog C */ 4082 /*! @{ */ 4083 4084 #define ADC_STAW5R_THRL_MASK (0x7FFFU) 4085 #define ADC_STAW5R_THRL_SHIFT (0U) 4086 #define ADC_STAW5R_THRL_WIDTH (15U) 4087 #define ADC_STAW5R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRL_SHIFT)) & ADC_STAW5R_THRL_MASK) 4088 4089 #define ADC_STAW5R_THRH_MASK (0x7FFF0000U) 4090 #define ADC_STAW5R_THRH_SHIFT (16U) 4091 #define ADC_STAW5R_THRH_WIDTH (15U) 4092 #define ADC_STAW5R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRH_SHIFT)) & ADC_STAW5R_THRH_MASK) 4093 /*! @} */ 4094 4095 /*! @name AMSIO - Analog Miscellaneous In/Out register */ 4096 /*! @{ */ 4097 4098 #define ADC_AMSIO_HSEN_MASK (0x60000U) 4099 #define ADC_AMSIO_HSEN_SHIFT (17U) 4100 #define ADC_AMSIO_HSEN_WIDTH (2U) 4101 #define ADC_AMSIO_HSEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_AMSIO_HSEN_SHIFT)) & ADC_AMSIO_HSEN_MASK) 4102 /*! @} */ 4103 4104 /*! @name CALBISTREG - Control And Calibration Status */ 4105 /*! @{ */ 4106 4107 #define ADC_CALBISTREG_TEST_EN_MASK (0x1U) 4108 #define ADC_CALBISTREG_TEST_EN_SHIFT (0U) 4109 #define ADC_CALBISTREG_TEST_EN_WIDTH (1U) 4110 #define ADC_CALBISTREG_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_TEST_EN_SHIFT)) & ADC_CALBISTREG_TEST_EN_MASK) 4111 4112 #define ADC_CALBISTREG_TEST_FAIL_MASK (0x8U) 4113 #define ADC_CALBISTREG_TEST_FAIL_SHIFT (3U) 4114 #define ADC_CALBISTREG_TEST_FAIL_WIDTH (1U) 4115 #define ADC_CALBISTREG_TEST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_TEST_FAIL_SHIFT)) & ADC_CALBISTREG_TEST_FAIL_MASK) 4116 4117 #define ADC_CALBISTREG_AVG_EN_MASK (0x10U) 4118 #define ADC_CALBISTREG_AVG_EN_SHIFT (4U) 4119 #define ADC_CALBISTREG_AVG_EN_WIDTH (1U) 4120 #define ADC_CALBISTREG_AVG_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_AVG_EN_SHIFT)) & ADC_CALBISTREG_AVG_EN_MASK) 4121 4122 #define ADC_CALBISTREG_NR_SMPL_MASK (0x60U) 4123 #define ADC_CALBISTREG_NR_SMPL_SHIFT (5U) 4124 #define ADC_CALBISTREG_NR_SMPL_WIDTH (2U) 4125 #define ADC_CALBISTREG_NR_SMPL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_NR_SMPL_SHIFT)) & ADC_CALBISTREG_NR_SMPL_MASK) 4126 4127 #define ADC_CALBISTREG_CALSTFUL_MASK (0x4000U) 4128 #define ADC_CALBISTREG_CALSTFUL_SHIFT (14U) 4129 #define ADC_CALBISTREG_CALSTFUL_WIDTH (1U) 4130 #define ADC_CALBISTREG_CALSTFUL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_CALSTFUL_SHIFT)) & ADC_CALBISTREG_CALSTFUL_MASK) 4131 4132 #define ADC_CALBISTREG_C_T_BUSY_MASK (0x8000U) 4133 #define ADC_CALBISTREG_C_T_BUSY_SHIFT (15U) 4134 #define ADC_CALBISTREG_C_T_BUSY_WIDTH (1U) 4135 #define ADC_CALBISTREG_C_T_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_C_T_BUSY_SHIFT)) & ADC_CALBISTREG_C_T_BUSY_MASK) 4136 4137 #define ADC_CALBISTREG_TSAMP_MASK (0x18000000U) 4138 #define ADC_CALBISTREG_TSAMP_SHIFT (27U) 4139 #define ADC_CALBISTREG_TSAMP_WIDTH (2U) 4140 #define ADC_CALBISTREG_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_TSAMP_SHIFT)) & ADC_CALBISTREG_TSAMP_MASK) 4141 4142 #define ADC_CALBISTREG_RESN_MASK (0xE0000000U) 4143 #define ADC_CALBISTREG_RESN_SHIFT (29U) 4144 #define ADC_CALBISTREG_RESN_WIDTH (3U) 4145 #define ADC_CALBISTREG_RESN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALBISTREG_RESN_SHIFT)) & ADC_CALBISTREG_RESN_MASK) 4146 /*! @} */ 4147 4148 /*! @name OFSGNUSR - Offset And Gain User */ 4149 /*! @{ */ 4150 4151 #define ADC_OFSGNUSR_OFFSET_USER_MASK (0xFFU) 4152 #define ADC_OFSGNUSR_OFFSET_USER_SHIFT (0U) 4153 #define ADC_OFSGNUSR_OFFSET_USER_WIDTH (8U) 4154 #define ADC_OFSGNUSR_OFFSET_USER(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSGNUSR_OFFSET_USER_SHIFT)) & ADC_OFSGNUSR_OFFSET_USER_MASK) 4155 4156 #define ADC_OFSGNUSR_GAIN_USER_MASK (0x3FF0000U) 4157 #define ADC_OFSGNUSR_GAIN_USER_SHIFT (16U) 4158 #define ADC_OFSGNUSR_GAIN_USER_WIDTH (10U) 4159 #define ADC_OFSGNUSR_GAIN_USER(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSGNUSR_GAIN_USER_SHIFT)) & ADC_OFSGNUSR_GAIN_USER_MASK) 4160 /*! @} */ 4161 4162 /*! @name CAL2 - Calibration Value 2 */ 4163 /*! @{ */ 4164 4165 #define ADC_CAL2_ENX_MASK (0x8000U) 4166 #define ADC_CAL2_ENX_SHIFT (15U) 4167 #define ADC_CAL2_ENX_WIDTH (1U) 4168 #define ADC_CAL2_ENX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL2_ENX_SHIFT)) & ADC_CAL2_ENX_MASK) 4169 /*! @} */ 4170 4171 /*! 4172 * @} 4173 */ /* end of group ADC_Register_Masks */ 4174 4175 /*! 4176 * @} 4177 */ /* end of group ADC_Peripheral_Access_Layer */ 4178 4179 #endif /* #if !defined(S32K344_ADC_H_) */ 4180