Searched refs:sysclkDiv (Results 1 – 2 of 2) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/components/codec/wm8960/ |
| D | fsl_wm8960.c | 53 …uint32_t pllF2 = outputClk * 4U, pllPrescale = 0U, sysclkDiv = 1U, pllR = 0, pllN = 0, pllK = 0U, … in WM8960_SetInternalPllConfig() local
67 sysclkDiv = 2U; in WM8960_SetInternalPllConfig()
68 pllN = (pllF2 * sysclkDiv) / inputMclk; in WM8960_SetInternalPllConfig()
77 pllR = (uint32_t)(((uint64_t)pllF2 * sysclkDiv * 1000U) / (inputMclk / 1000U)); in WM8960_SetInternalPllConfig()
93 …ET(WM8960_ModifyReg(handle, WM8960_CLOCK1, 7U, (uint16_t)(((sysclkDiv == 1U ? 0U : sysclkDiv) << 1… in WM8960_SetInternalPllConfig()
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/components/codec/wm8904/ |
| D | fsl_wm8904.c | 523 uint16_t sysclkDiv = 0U; in WM8904_SetMasterClock() local
525 result = WM8904_ReadRegister(handle, WM8904_CLK_RATES_0, &sysclkDiv); in WM8904_SetMasterClock()
526 sysclk = sysclk >> (sysclkDiv & 0x1U); in WM8904_SetMasterClock()
|
