Home
last modified time | relevance | path

Searched refs:regBase (Results 1 – 25 of 38) sorted by relevance

12

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/llwu/
Dfsl_llwu.c30 volatile uint32_t *regBase; in LLWU_SetExternalWakeupPinMode() local
37 regBase = &base->PE1; in LLWU_SetExternalWakeupPinMode()
41 regBase = &base->PE2; in LLWU_SetExternalWakeupPinMode()
45 regBase = NULL; in LLWU_SetExternalWakeupPinMode()
49 if (NULL != regBase) in LLWU_SetExternalWakeupPinMode()
51 reg = *regBase; in LLWU_SetExternalWakeupPinMode()
55 *regBase = reg; in LLWU_SetExternalWakeupPinMode()
58 volatile uint8_t *regBase; in LLWU_SetExternalWakeupPinMode()
64 regBase = &base->PE1; in LLWU_SetExternalWakeupPinMode()
67 regBase = &base->PE2; in LLWU_SetExternalWakeupPinMode()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
Dfsl_clock.h518 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
Dfsl_clock.h518 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
Dfsl_clock.h518 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.c208 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
210 if (regBase != NULL) in CLOCK_SetLpcgGate()
214 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
218 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
223 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
227 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
241 volatile uint32_t *regBase; in CLOCK_ConfigLPCG() local
243 regBase = LPCG_TUPLE_REG_BASE(name); in CLOCK_ConfigLPCG()
246 if (regBase == NULL) in CLOCK_ConfigLPCG()
257 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCG()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_clock.c241 void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask) in CLOCK_SetLpcgGate() argument
243 if (regBase != NULL) in CLOCK_SetLpcgGate()
247 *regBase |= bitsMask & LPCG_CLK_SWEN_MASK; in CLOCK_SetLpcgGate()
251 *regBase &= ~(bitsMask & LPCG_CLK_SWEN_MASK); in CLOCK_SetLpcgGate()
256 *regBase |= bitsMask & LPCG_CLK_HWEN_MASK; in CLOCK_SetLpcgGate()
260 *regBase &= ~(bitsMask & LPCG_CLK_HWEN_MASK); in CLOCK_SetLpcgGate()
287 volatile uint32_t *regBase; in CLOCK_ConfigLPCGMapped() local
289 regBase = lpcgBase; in CLOCK_ConfigLPCGMapped()
292 if (regBase == NULL) in CLOCK_ConfigLPCGMapped()
303 CLOCK_SetLpcgGate(regBase, swGate, hwGate, 0xBBAAABU); in CLOCK_ConfigLPCGMapped()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flash_ftmr/
Dfsl_flash.c1839 FTMRx_REG32_ACCESS_TYPE regBase; in FLASH_PflashSetPrefetchSpeculation() local
1841 regBase = (FTMRx_REG32_ACCESS_TYPE)&MCM->PLACR; in FLASH_PflashSetPrefetchSpeculation()
1843 regBase = (FTMRx_REG32_ACCESS_TYPE)&MCM0->PLACR; in FLASH_PflashSetPrefetchSpeculation()
1853 *regBase |= MCM_PLACR_DFCS_MASK; in FLASH_PflashSetPrefetchSpeculation()
1858 *regBase &= ~MCM_PLACR_DFCS_MASK; in FLASH_PflashSetPrefetchSpeculation()
1861 *regBase |= MCM_PLACR_EFDS_MASK; in FLASH_PflashSetPrefetchSpeculation()
1865 *regBase &= ~MCM_PLACR_EFDS_MASK; in FLASH_PflashSetPrefetchSpeculation()
1871 FTMRx_REG32_ACCESS_TYPE regBase; in FLASH_PflashSetPrefetchSpeculation()
1874 regBase = (FTMRx_REG32_ACCESS_TYPE)&FMC->PFB01CR; in FLASH_PflashSetPrefetchSpeculation()
1878 regBase = (FTMRx_REG32_ACCESS_TYPE)&FMC->PFB0CR; in FLASH_PflashSetPrefetchSpeculation()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/wdog32/
Dfsl_wdog32.c88 register WDOG_Type *regBase = base; in WDOG32_Init() local
103 regBase->WIN = regConfig->windowValue; in WDOG32_Init()
104 regBase->TOVAL = regConfig->timeoutValue; in WDOG32_Init()
105 regBase->CS = value; in WDOG32_Init()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flash/
Dfsl_ftfx_cache.c391 FTFx_REG32_ACCESS_TYPE regBase; in mcm_flash_cache_clear() local
394 regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; in mcm_flash_cache_clear()
396 regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; in mcm_flash_cache_clear()
401 …ftfx_common_bit_operation_command_sequence(config, regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_… in mcm_flash_cache_clear()
404 *regBase |= MCM_CACHE_CLEAR_MASK; in mcm_flash_cache_clear()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.c36 void CLOCK_Init(CCM_Type *regBase) in CLOCK_Init() argument
38 ccm_base = regBase; in CLOCK_Init()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/pca9420/
Dfsl_pca9420.c405 bool PCA9420_WriteRegs(pca9420_handle_t *handle, uint8_t regBase, uint8_t *val, uint32_t size) in PCA9420_WriteRegs() argument
411 …return (kStatus_Success == handle->I2C_SendFunc(handle->slaveAddress, regBase, 1U, val, size)) ? t… in PCA9420_WriteRegs()
414 bool PCA9420_ReadRegs(pca9420_handle_t *handle, uint8_t regBase, uint8_t *val, uint32_t size) in PCA9420_ReadRegs() argument
420 …return (kStatus_Success == handle->I2C_ReceiveFunc(handle->slaveAddress, regBase, 1U, val, size)) … in PCA9420_ReadRegs()
Dfsl_pca9420.h779 bool PCA9420_WriteRegs(pca9420_handle_t *handle, uint8_t regBase, uint8_t *val, uint32_t size);
790 bool PCA9420_ReadRegs(pca9420_handle_t *handle, uint8_t regBase, uint8_t *val, uint32_t size);

12