1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __RDC_DEFS_IMX7D__ 32 #define __RDC_DEFS_IMX7D__ 33 34 /*! 35 * @addtogroup rdc_def_imx7d 36 * @{ 37 */ 38 39 /******************************************************************************* 40 * Definitions 41 ******************************************************************************/ 42 43 /*! @brief RDC master assignment. */ 44 enum _rdc_mda 45 { 46 rdcMdaA7 = 0U, /*!< ARM Cortex-A7 RDC Master. */ 47 rdcMdaM4 = 1U, /*!< ARM Cortex-M4 RDC Master. */ 48 rdcMdaPcie = 2U, /*!< PCIe RDC Master. */ 49 rdcMdaCsi = 3U, /*!< CSI RDC Master. */ 50 rdcMdaEpdc = 4U, /*!< EPDC RDC Master. */ 51 rdcMdaLcdif = 5U, /*!< LCDIF RDC Master. */ 52 rdcMdaDisplayPort = 6U, /*!< DISPLAY PORT RDC Master. */ 53 rdcMdaPxp = 7U, /*!< PXP RDC Master. */ 54 rdcMdaCoresight = 8U, /*!< CORESIGHT RDC Master. */ 55 rdcMdaDap = 9U, /*!< DAP RDC Master. */ 56 rdcMdaCaam = 10U, /*!< CAAM RDC Master. */ 57 rdcMdaSdmaPeriph = 11U, /*!< SDMA PERIPHERAL RDC Master. */ 58 rdcMdaSdmaBurst = 12U, /*!< SDMA BURST RDC Master. */ 59 rdcMdaApbhdma = 13U, /*!< APBH DMA RDC Master. */ 60 rdcMdaRawnand = 14U, /*!< RAW NAND RDC Master. */ 61 rdcMdaUsdhc1 = 15U, /*!< USDHC1 RDC Master. */ 62 rdcMdaUsdhc2 = 16U, /*!< USDHC2 RDC Master. */ 63 rdcMdaUsdhc3 = 17U, /*!< USDHC3 RDC Master. */ 64 rdcMdaNc1 = 18U, /*!< NC1 RDC Master. */ 65 rdcMdaUsb = 19U, /*!< USB RDC Master. */ 66 rdcMdaNc2 = 20U, /*!< NC2 RDC Master. */ 67 rdcMdaTest = 21U, /*!< TEST RDC Master. */ 68 rdcMdaEnet1Tx = 22U, /*!< Ethernet1 Tx RDC Master. */ 69 rdcMdaEnet1Rx = 23U, /*!< Ethernet1 Rx RDC Master. */ 70 rdcMdaEnet2Tx = 24U, /*!< Ethernet2 Tx RDC Master. */ 71 rdcMdaEnet2Rx = 25U, /*!< Ethernet2 Rx RDC Master. */ 72 rdcMdaSdmaPort = 26U, /*!< SDMA PORT RDC Master. */ 73 }; 74 75 /*! @brief RDC peripheral assignment. */ 76 enum _rdc_pdap 77 { 78 rdcPdapGpio1 = 0U, /*!< GPIO1 RDC Peripheral. */ 79 rdcPdapGpio2 = 1U, /*!< GPIO2 RDC Peripheral. */ 80 rdcPdapGpio3 = 2U, /*!< GPIO3 RDC Peripheral. */ 81 rdcPdapGpio4 = 3U, /*!< GPIO4 RDC Peripheral. */ 82 rdcPdapGpio5 = 4U, /*!< GPIO5 RDC Peripheral. */ 83 rdcPdapGpio6 = 5U, /*!< GPIO6 RDC Peripheral. */ 84 rdcPdapGpio7 = 6U, /*!< GPIO7 RDC Peripheral. */ 85 rdcPdapIomuxcLpsrGpr = 7U, /*!< IOMXUC LPSR GPR RDC Peripheral. */ 86 rdcPdapWdog1 = 8U, /*!< WDOG1 RDC Peripheral. */ 87 rdcPdapWdog2 = 9U, /*!< WDOG2 RDC Peripheral. */ 88 rdcPdapWdog3 = 10U, /*!< WDOG3 RDC Peripheral. */ 89 rdcPdapWdog4 = 11U, /*!< WDOG4 RDC Peripheral. */ 90 rdcPdapIomuxcLpsr = 12U, /*!< IOMUXC LPSR RDC Peripheral. */ 91 rdcPdapGpt1 = 13U, /*!< GPT1 RDC Peripheral. */ 92 rdcPdapGpt2 = 14U, /*!< GPT2 RDC Peripheral. */ 93 rdcPdapGpt3 = 15U, /*!< GPT3 RDC Peripheral. */ 94 rdcPdapGpt4 = 16U, /*!< GPT4 RDC Peripheral. */ 95 rdcPdapRomcp = 17U, /*!< ROMCP RDC Peripheral. */ 96 rdcPdapKpp = 18U, /*!< KPP RDC Peripheral. */ 97 rdcPdapIomuxc = 19U, /*!< IOMUXC RDC Peripheral. */ 98 rdcPdapIomuxcGpr = 20U, /*!< IOMUXC GPR RDC Peripheral. */ 99 rdcPdapOcotpCtrl = 21U, /*!< OCOTP CTRL RDC Peripheral. */ 100 rdcPdapAnatopDig = 22U, /*!< ANATOPDIG RDC Peripheral. */ 101 rdcPdapSnvs = 23U, /*!< SNVS RDC Peripheral. */ 102 rdcPdapCcm = 24U, /*!< CCM RDC Peripheral. */ 103 rdcPdapSrc = 25U, /*!< SRC RDC Peripheral. */ 104 rdcPdapGpc = 26U, /*!< GPC RDC Peripheral. */ 105 rdcPdapSemaphore1 = 27U, /*!< SEMAPHORE1 RDC Peripheral. */ 106 rdcPdapSemaphore2 = 28U, /*!< SEMAPHORE2 RDC Peripheral. */ 107 rdcPdapRdc = 29U, /*!< RDC RDC Peripheral. */ 108 rdcPdapCsu = 30U, /*!< CSU RDC Peripheral. */ 109 rdcPdapReserved1 = 31U, /*!< Reserved1 RDC Peripheral. */ 110 rdcPdapReserved2 = 32U, /*!< Reserved2 RDC Peripheral. */ 111 rdcPdapAdc1 = 33U, /*!< ADC1 RDC Peripheral. */ 112 rdcPdapAdc2 = 34U, /*!< ADC2 RDC Peripheral. */ 113 rdcPdapEcspi4 = 35U, /*!< ECSPI4 RDC Peripheral. */ 114 rdcPdapFlexTimer1 = 36U, /*!< FTM1 RDC Peripheral. */ 115 rdcPdapFlexTimer2 = 37U, /*!< FTM2 RDC Peripheral. */ 116 rdcPdapPwm1 = 38U, /*!< PWM1 RDC Peripheral. */ 117 rdcPdapPwm2 = 39U, /*!< PWM2 RDC Peripheral. */ 118 rdcPdapPwm3 = 40U, /*!< PWM3 RDC Peripheral. */ 119 rdcPdapPwm4 = 41U, /*!< PWM4 RDC Peripheral. */ 120 rdcPdapSystemCounterRead = 42U, /*!< System Counter Read RDC Peripheral. */ 121 rdcPdapSystemCounterCompare = 43U, /*!< System Counter Compare RDC Peripheral. */ 122 rdcPdapSystemCounterControl = 44U, /*!< System Counter Control RDC Peripheral. */ 123 rdcPdapPcie = 45U, /*!< PCIE RDC Peripheral. */ 124 rdcPdapReserved3 = 46U, /*!< Reserved3 RDC Peripheral. */ 125 rdcPdapEpdc = 47U, /*!< EPDC RDC Peripheral. */ 126 rdcPdapPxp = 48U, /*!< PXP RDC Peripheral. */ 127 rdcPdapCsi = 49U, /*!< CSI RDC Peripheral. */ 128 rdcPdapReserved4 = 50U, /*!< Reserved4 RDC Peripheral. */ 129 rdcPdapLcdif = 51U, /*!< LCDIF RDC Peripheral. */ 130 rdcPdapReserved5 = 52U, /*!< Reserved5 RDC Peripheral. */ 131 rdcPdapMipiCsi = 53U, /*!< MIPI CSI RDC Peripheral. */ 132 rdcPdapMipiDsi = 54U, /*!< MIPI DSI RDC Peripheral. */ 133 rdcPdapReserved6 = 55U, /*!< Reserved6 RDC Peripheral. */ 134 rdcPdapTzasc = 56U, /*!< TZASC RDC Peripheral. */ 135 rdcPdapDdrPhy = 57U, /*!< DDR PHY RDC Peripheral. */ 136 rdcPdapDdrc = 58U, /*!< DDRC RDC Peripheral. */ 137 rdcPdapReserved7 = 59U, /*!< Reserved7 RDC Peripheral. */ 138 rdcPdapPerfMon1 = 60U, /*!< PerfMon1 RDC Peripheral. */ 139 rdcPdapPerfMon2 = 61U, /*!< PerfMon2 RDC Peripheral. */ 140 rdcPdapAxi = 62U, /*!< AXI RDC Peripheral. */ 141 rdcPdapQosc = 63U, /*!< QOSC RDC Peripheral. */ 142 rdcPdapFlexCan1 = 64U, /*!< FLEXCAN1 RDC Peripheral. */ 143 rdcPdapFlexCan2 = 65U, /*!< FLEXCAN2 RDC Peripheral. */ 144 rdcPdapI2c1 = 66U, /*!< I2C1 RDC Peripheral. */ 145 rdcPdapI2c2 = 67U, /*!< I2C2 RDC Peripheral. */ 146 rdcPdapI2c3 = 68U, /*!< I2C3 RDC Peripheral. */ 147 rdcPdapI2c4 = 69U, /*!< I2C4 RDC Peripheral. */ 148 rdcPdapUart4 = 70U, /*!< UART4 RDC Peripheral. */ 149 rdcPdapUart5 = 71U, /*!< UART5 RDC Peripheral. */ 150 rdcPdapUart6 = 72U, /*!< UART6 RDC Peripheral. */ 151 rdcPdapUart7 = 73U, /*!< UART7 RDC Peripheral. */ 152 rdcPdapMuA = 74U, /*!< MUA RDC Peripheral. */ 153 rdcPdapMuB = 75U, /*!< MUB RDC Peripheral. */ 154 rdcPdapSemaphoreHs = 76U, /*!< SEMAPHORE HS RDC Peripheral. */ 155 rdcPdapUsbPl301 = 77U, /*!< USB PL301 RDC Peripheral. */ 156 rdcPdapReserved8 = 78U, /*!< Reserved8 RDC Peripheral. */ 157 rdcPdapReserved9 = 79U, /*!< Reserved9 RDC Peripheral. */ 158 rdcPdapReserved10 = 80U, /*!< Reserved10 RDC Peripheral. */ 159 rdcPdapUSB1Otg1 = 81U, /*!< USB2 OTG1 RDC Peripheral. */ 160 rdcPdapUSB2Otg2 = 82U, /*!< USB2 OTG2 RDC Peripheral. */ 161 rdcPdapUSB3Host = 83U, /*!< USB3 HOST RDC Peripheral. */ 162 rdcPdapUsdhc1 = 84U, /*!< USDHC1 RDC Peripheral. */ 163 rdcPdapUsdhc2 = 85U, /*!< USDHC2 RDC Peripheral. */ 164 rdcPdapUsdhc3 = 86U, /*!< USDHC3 RDC Peripheral. */ 165 rdcPdapReserved11 = 87U, /*!< Reserved11 RDC Peripheral. */ 166 rdcPdapReserved12 = 88U, /*!< Reserved12 RDC Peripheral. */ 167 rdcPdapSim1 = 89U, /*!< SIM1 RDC Peripheral. */ 168 rdcPdapSim2 = 90U, /*!< SIM2 RDC Peripheral. */ 169 rdcPdapQspi = 91U, /*!< QSPI RDC Peripheral. */ 170 rdcPdapWeim = 92U, /*!< WEIM RDC Peripheral. */ 171 rdcPdapSdma = 93U, /*!< SDMA RDC Peripheral. */ 172 rdcPdapEnet1 = 94U, /*!< Eneternet1 RDC Peripheral. */ 173 rdcPdapEnet2 = 95U, /*!< Eneternet2 RDC Peripheral. */ 174 rdcPdapReserved13 = 96U, /*!< Reserved13 RDC Peripheral. */ 175 rdcPdapReserved14 = 97U, /*!< Reserved14 RDC Peripheral. */ 176 rdcPdapEcspi1 = 98U, /*!< ECSPI1 RDC Peripheral. */ 177 rdcPdapEcspi2 = 99U, /*!< ECSPI2 RDC Peripheral. */ 178 rdcPdapEcspi3 = 100U, /*!< ECSPI3 RDC Peripheral. */ 179 rdcPdapReserved15 = 101U, /*!< Reserved15 RDC Peripheral. */ 180 rdcPdapUart1 = 102U, /*!< UART1 RDC Peripheral. */ 181 rdcPdapReserved16 = 103U, /*!< Reserved16 RDC Peripheral. */ 182 rdcPdapUart3 = 104U, /*!< UART3 RDC Peripheral. */ 183 rdcPdapUart2 = 105U, /*!< UART2 RDC Peripheral. */ 184 rdcPdapSai1 = 106U, /*!< SAI1 RDC Peripheral. */ 185 rdcPdapSai2 = 107U, /*!< SAI2 RDC Peripheral. */ 186 rdcPdapSai3 = 108U, /*!< SAI3 RDC Peripheral. */ 187 rdcPdapReserved17 = 109U, /*!< Reserved17 RDC Peripheral. */ 188 rdcPdapReserved18 = 110U, /*!< Reserved18 RDC Peripheral. */ 189 rdcPdapSpba = 111U, /*!< SPBA RDC Peripheral. */ 190 rdcPdapDap = 112U, /*!< DAP RDC Peripheral. */ 191 rdcPdapReserved19 = 113U, /*!< Reserved19 RDC Peripheral. */ 192 rdcPdapReserved20 = 114U, /*!< Reserved20 RDC Peripheral. */ 193 rdcPdapReserved21 = 115U, /*!< Reserved21 RDC Peripheral. */ 194 rdcPdapCaam = 116U, /*!< CAAM RDC Peripheral. */ 195 rdcPdapReserved22 = 117U, /*!< Reserved22 RDC Peripheral. */ 196 }; 197 198 /*! @brief RDC memory region. */ 199 enum _rdc_mr 200 { 201 rdcMrMmdc = 0U, /*!< alignment 4096 */ 202 rdcMrMmdcLast = 7U, /*!< alignment 4096 */ 203 rdcMrQspi = 8U, /*!< alignment 4096 */ 204 rdcMrQspiLast = 15U, /*!< alignment 4096 */ 205 rdcMrWeim = 16U, /*!< alignment 4096 */ 206 rdcMrWeimLast = 23U, /*!< alignment 4096 */ 207 rdcMrPcie = 24U, /*!< alignment 4096 */ 208 rdcMrPcieLast = 31U, /*!< alignment 4096 */ 209 rdcMrOcram = 32U, /*!< alignment 128 */ 210 rdcMrOcramLast = 36U, /*!< alignment 128 */ 211 rdcMrOcramS = 37U, /*!< alignment 128 */ 212 rdcMrOcramSLast = 41U, /*!< alignment 128 */ 213 rdcMrOcramEpdc = 42U, /*!< alignment 128 */ 214 rdcMrOcramEpdcLast = 46U, /*!< alignment 128 */ 215 rdcMrOcramPxp = 47U, /*!< alignment 128 */ 216 rdcMrOcramPxpLast = 51U, /*!< alignment 128 */ 217 }; 218 219 #endif /* __RDC_DEFS_IMX7D__ */ 220 /******************************************************************************* 221 * EOF 222 ******************************************************************************/ 223
