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Searched refs:pConfig (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Sfdp.c941 static void Qspi_Ip_SfdpLutInitEnterLegacySPI(const Qspi_Ip_MemoryConfigType *pConfig);
989 const Qspi_Ip_MemoryConfigType *pConfig
998 const Qspi_Ip_MemoryConfigType *pConfig
1001 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_01(const Qspi_Ip_MemoryConfigType * pConfig);
1002 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_02(const Qspi_Ip_MemoryConfigType * pConfig);
1003 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_08(const Qspi_Ip_MemoryConfigType * pConfig);
1004 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_16(const Qspi_Ip_MemoryConfigType * pConfig);
1007 const Qspi_Ip_MemoryConfigType *pConfig
1011 const Qspi_Ip_MemoryConfigType *pConfig
1015 const Qspi_Ip_MemoryConfigType *pConfig
[all …]
DQspi_Ip.c1772 const Qspi_Ip_MemoryConfigType * pConfig, in Qspi_Ip_Init() argument
1780 DEV_ASSERT_QSPI(pConfig != NULL_PTR); in Qspi_Ip_Init()
1785 state->configuration = pConfig; in Qspi_Ip_Init()
1787 state->activeReadLut = pConfig->readLut; /* 0-X-X mode disabled by default */ in Qspi_Ip_Init()
1792 if (pConfig->ctrlAutoCfgPtr != NULL_PTR) in Qspi_Ip_Init()
1794 status = Qspi_Ip_ControllerInit(pConnect->qspiInstance, pConfig->ctrlAutoCfgPtr); in Qspi_Ip_Init()
1799 …status = Qspi_Ip_InitReset(instance, pConfig->initResetSettings.resetCmdLut, pConfig->initResetSet… in Qspi_Ip_Init()
1808 if ((STATUS_QSPI_IP_SUCCESS == status) && (NULL_PTR != pConfig->initCallout)) in Qspi_Ip_Init()
1810 status = pConfig->initCallout(instance); in Qspi_Ip_Init()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c831 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) in FLEXCAN_Init() argument
834 assert(NULL != pConfig); in FLEXCAN_Init()
835 assert((pConfig->maxMbNum > 0U) && in FLEXCAN_Init()
836 … (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); in FLEXCAN_Init()
843 flexcan_timing_config_t timingCfg = pConfig->timingConfig; in FLEXCAN_Init()
849 uint32_t tqFre = pConfig->bitRate * quantum; in FLEXCAN_Init()
853 assert((pConfig->bitRate != 0U) && (pConfig->bitRate <= 1000000U) && (tqFre <= sourceClock_Hz)); in FLEXCAN_Init()
903 … base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : in FLEXCAN_Init()
920 base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : in FLEXCAN_Init()
924 …base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MAS… in FLEXCAN_Init()
[all …]
Dfsl_flexcan.h1114 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz);
1168 …CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSi…
1202 void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
1222 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1253 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1399 …nhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable);
1411 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c1954 const Adc_Sar_Ip_ConfigType * const pConfig) in Adc_Sar_Ip_Init() argument
1977 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
1981 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2032 *MCRAddr = Adc_Sar_CollectMcrMasks(u32Instance, pConfig, *MCRAddr); in Adc_Sar_Ip_Init()
2034 Adc_Sar_Ip_axAdcSarState[u32Instance].DataAlign = pConfig->DataAlign; in Adc_Sar_Ip_Init()
2039 if (ADC_SAR_IP_CTU_MODE_TRIGGER == pConfig->CtuMode) in Adc_Sar_Ip_Init()
2046 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn); in Adc_Sar_Ip_Init()
2051 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr); in Adc_Sar_Ip_Init()
2054 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay); in Adc_Sar_Ip_Init()
2058 Adc_Sar_EnableClkDiv(u32Instance, pConfig->ClkDivEnable); in Adc_Sar_Ip_Init()
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/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip.h104 const Qspi_Ip_MemoryConfigType * pConfig,
438 Qspi_Ip_StatusType Qspi_Ip_ReadSfdp(Qspi_Ip_MemoryConfigType * pConfig,
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/algorithms/pedometer/source/
Dpedometer.c111 void pedometer_configure(pedometer_t *pPedometer, const pedometer_config_t *pConfig) in pedometer_configure() argument
113 pPedometer->config = *pConfig; in pedometer_configure()
/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip.h189 const Adc_Sar_Ip_ConfigType * const pConfig);
488 const Adc_Sar_Ip_ClockConfigType * const pConfig);
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/algorithms/pedometer/include/
Dpedometer.h135 void pedometer_configure(pedometer_t *pPedometer, const pedometer_config_t *pConfig);