1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2019 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _FSL_PMU_H_
9 #define _FSL_PMU_H_
10 
11 #include "fsl_common.h"
12 
13 /*! @addtogroup pmu */
14 /*! @{ */
15 
16 /*******************************************************************************
17  * Definitions
18  ******************************************************************************/
19 
20 /*! @name Driver version */
21 /*@{*/
22 /*! @brief PMU driver version */
23 #define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
24                                                        /*@}*/
25 
26 /*!
27  * @brief PMU Status flags.
28  */
29 enum
30 {
31     kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output
32                                                         is ok. 1 = regulator output > brownout target. */
33     kPMU_1P1BrownoutOnOutput = (1U << 1U),  /*!< Status bit that signals when a 1p1 brownout is detected
34                                                         on the regulator output. */
35     kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output
36                                                         is ok. 1 = regulator output > brownout target. */
37     kPMU_3P0BrownoutOnOutput = (1U << 3U),  /*!< Status bit that signals when a 3p0 brownout is detected
38                                                         on the regulator output. */
39     kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output
40                                                         is ok. 1 = regulator output > brownout target. */
41     kPMU_2P5BrownoutOnOutput = (1U << 5U),  /*!< Status bit that signals when a 2p5 brownout is detected
42                                                         on the regulator output. */
43 };
44 
45 /*!
46  * @brief The source for the reference voltage of the weak 1P1 regulator.
47  */
48 typedef enum _pmu_1p1_weak_reference_source
49 {
50     kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */
51     kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */
52 } pmu_1p1_weak_reference_source_t;
53 
54 /*!
55  * @brief Input voltage source for LDO_3P0 from USB VBus.
56  */
57 typedef enum _pmu_3p0_vbus_voltage_source
58 {
59     kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */
60     kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */
61 } pmu_3p0_vbus_voltage_source_t;
62 
63 /*!
64  * @brief Regulator voltage ramp rate.
65  */
66 typedef enum _pmu_core_reg_voltage_ramp_rate
67 {
68     kPMU_CoreRegVoltageRampRateFast       = 0U, /*!< Fast. */
69     kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */
70     kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */
71     kPMU_CoreRegVoltageRampRateSlow       = 0U, /*!< Slow. */
72 } pmu_core_reg_voltage_ramp_rate_t;
73 
74 #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
75 /*!
76  * @brief Mask values of power gate.
77  */
78 enum _pmu_power_gate
79 {
80     kPMU_PowerGateDisplay      = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK,      /*!< Display power gate control. */
81     kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK,  /*!< Display logic power gate control. */
82     kPMU_PowerGateL2           = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK,       /*!< L2 power gate control. */
83     kPMU_PowerGateL1           = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK,       /*!< L1 power gate control. */
84     kPMU_PowerGateRefTopIBias  = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */
85 };
86 #endif /*  FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
87 
88 /*!
89  * @brief Bandgap select.
90  */
91 typedef enum _pmu_power_bandgap
92 {
93     kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */
94     kPMU_LowPowerBandgap    = 1U, /*!< Low power bandgap. */
95 } pmu_power_bandgap_t;
96 
97 /*******************************************************************************
98  * API
99  ******************************************************************************/
100 
101 #if defined(__cplusplus)
102 extern "C" {
103 #endif /* __cplusplus*/
104 
105 /*!
106  * @name Status.
107  * @{
108  */
109 
110 /*!
111  * @brief Get PMU status flags.
112  *
113  * @param base PMU peripheral base address.
114  * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok
115  * and brownout output of 1P1,3P0 and 2P5 is detected.
116  */
117 uint32_t PMU_GetStatusFlags(PMU_Type *base);
118 
119 /*@}*/
120 
121 /*!
122  * @name 1P1 Regular
123  * @{
124  */
125 
126 /*!
127  * @brief Selects the source for the reference voltage of the weak 1P1 regulator.
128  *
129  * @param base PMU peripheral base address.
130  * @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t.
131  */
PMU_1P1SetWeakReferenceSource(PMU_Type * base,pmu_1p1_weak_reference_source_t option)132 static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option)
133 {
134     base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option);
135 }
136 
137 /*!
138  * @brief Enables the weak 1P1 regulator.
139  *
140  * This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions.
141  *
142  * @param base PMU peripheral base address.
143  * @param enable Enable the feature or not.
144  */
PMU_1P1EnableWeakRegulator(PMU_Type * base,bool enable)145 static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable)
146 {
147     if (enable)
148     {
149         base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
150     }
151     else
152     {
153         base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
154     }
155 }
156 
157 /*!
158  * @brief Adjust the 1P1 regulator output voltage.
159  *
160  * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
161  * may be interpolated from these examples. Choices must be in this range:
162  * - 0x1b(1.375V) >= output_trg >= 0x04(0.8V)
163  * - 0x04 : 0.8V
164  * - 0x10 : 1.1V (typical)
165  * - 0x1b : 1.375V
166  * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
167  *
168  * @param base PMU peripheral base address.
169  * @param value Setting value for the output.
170  */
PMU_1P1SetRegulatorOutputVoltage(PMU_Type * base,uint32_t value)171 static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
172 {
173     base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value);
174 }
175 
176 /*!
177  * @brief Adjust the 1P1 regulator brownout offset voltage.
178  *
179  * Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset
180  * brown-offset is 175mV below the programmed target code.
181  * Brownout target = OUTPUT_TRG - BO_OFFSET.
182  * Some steps may be irrelevant because of input supply limitations or load operation.
183  *
184  * @param base PMU peripheral base address.
185  * @param value Setting value for the brownout offset. The available range is in 3-bit.
186  */
PMU_1P1SetBrownoutOffsetVoltage(PMU_Type * base,uint32_t value)187 static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
188 {
189     base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value);
190 }
191 
192 /*!
193  * @brief Enable the pull-down circuitry in the regulator.
194  *
195  * @param base PMU peripheral base address.
196  * @param enable Enable the feature or not.
197  */
PMU_1P1EnablePullDown(PMU_Type * base,bool enable)198 static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable)
199 {
200     if (enable)
201     {
202         base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
203     }
204     else
205     {
206         base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
207     }
208 }
209 
210 /*!
211  * @brief Enable the current-limit circuitry in the regulator.
212  *
213  * @param base PMU peripheral base address.
214  * @param enable Enable the feature or not.
215  */
PMU_1P1EnableCurrentLimit(PMU_Type * base,bool enable)216 static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable)
217 {
218     if (enable)
219     {
220         base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK;
221     }
222     else
223     {
224         base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK;
225     }
226 }
227 
228 /*!
229  * @brief Enable the brownout circuitry in the regulator.
230  *
231  * @param base PMU peripheral base address.
232  * @param enable Enable the feature or not.
233  */
PMU_1P1EnableBrownout(PMU_Type * base,bool enable)234 static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable)
235 {
236     if (enable)
237     {
238         base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK;
239     }
240     else
241     {
242         base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK;
243     }
244 }
245 
246 /*!
247  * @brief Enable the regulator output.
248  *
249  * @param base PMU peripheral base address.
250  * @param enable Enable the feature or not.
251  */
PMU_1P1EnableOutput(PMU_Type * base,bool enable)252 static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable)
253 {
254     if (enable)
255     {
256         base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK;
257     }
258     else
259     {
260         base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK;
261     }
262 }
263 
264 /*@}*/
265 
266 /*!
267  * @name 3P0 Regular
268  * @{
269  */
270 
271 /*!
272  * @brief Adjust the 3P0 regulator output voltage.
273  *
274  * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
275  * may be interpolated from these examples. Choices must be in this range:
276  * - 0x00(2.625V) >= output_trg >= 0x1f(3.4V)
277  * - 0x00 : 2.625V
278  * - 0x0f : 3.0V (typical)
279  * - 0x1f : 3.4V
280  *
281  * @param base PMU peripheral base address.
282  * @param value Setting value for the output.
283  */
PMU_3P0SetRegulatorOutputVoltage(PMU_Type * base,uint32_t value)284 static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
285 {
286     base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value);
287 }
288 
289 /*!
290  * @brief Select input voltage source for LDO_3P0.
291  *
292  * Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only
293  * one of the two VBUS voltages is present, it is automatically selected.
294  *
295  * @param base PMU peripheral base address.
296  * @param option User-defined input voltage source for LDO_3P0.
297  */
PMU_3P0SetVBusVoltageSource(PMU_Type * base,pmu_3p0_vbus_voltage_source_t option)298 static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option)
299 {
300     base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option);
301 }
302 
303 /*!
304  * @brief Adjust the 3P0 regulator brownout offset voltage.
305  *
306  * Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset
307  * brown-offset is 175mV below the programmed target code.
308  * Brownout target = OUTPUT_TRG - BO_OFFSET.
309  * Some steps may be irrelevant because of input supply limitations or load operation.
310  *
311  * @param base PMU peripheral base address.
312  * @param value Setting value for the brownout offset. The available range is in 3-bit.
313  */
PMU_3P0SetBrownoutOffsetVoltage(PMU_Type * base,uint32_t value)314 static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
315 {
316     base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value);
317 }
318 
319 /*!
320  * @brief Enable the current-limit circuitry in the 3P0 regulator.
321  *
322  * @param base PMU peripheral base address.
323  * @param enable Enable the feature or not.
324  */
PMU_3P0EnableCurrentLimit(PMU_Type * base,bool enable)325 static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable)
326 {
327     if (enable)
328     {
329         base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK;
330     }
331     else
332     {
333         base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK;
334     }
335 }
336 
337 /*!
338  * @brief Enable the brownout circuitry in the 3P0 regulator.
339  *
340  * @param base PMU peripheral base address.
341  * @param enable Enable the feature or not.
342  */
PMU_3P0EnableBrownout(PMU_Type * base,bool enable)343 static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable)
344 {
345     if (enable)
346     {
347         base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK;
348     }
349     else
350     {
351         base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK;
352     }
353 }
354 
355 /*!
356  * @brief Enable the 3P0 regulator output.
357  *
358  * @param base PMU peripheral base address.
359  * @param enable Enable the feature or not.
360  */
PMU_3P0EnableOutput(PMU_Type * base,bool enable)361 static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable)
362 {
363     if (enable)
364     {
365         base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK;
366     }
367     else
368     {
369         base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK;
370     }
371 }
372 
373 /* @} */
374 
375 /*!
376  * @name 2P5 Regulator
377  * @{
378  */
379 
380 /*!
381  * @brief Enables the weak 2P5 regulator.
382  *
383  * This low power regulator is used when the main 2P5 regulator is disabled
384  * to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN.
385  *
386  * @param base PMU peripheral base address.
387  * @param enable Enable the feature or not.
388  */
PMU_2P5EnableWeakRegulator(PMU_Type * base,bool enable)389 static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable)
390 {
391     if (enable)
392     {
393         base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
394     }
395     else
396     {
397         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
398     }
399 }
400 
401 /*!
402  * @brief Adjust the 1P1 regulator output voltage.
403  *
404  * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
405  * may be interpolated from these examples. Choices must be in this range:
406  * - 0x00(2.1V) >= output_trg >= 0x1f(2.875V)
407  * - 0x00 : 2.1V
408  * - 0x10 : 2.5V (typical)
409  * - 0x1f : 2.875V
410  * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
411  *
412  * @param base PMU peripheral base address.
413  * @param value Setting value for the output.
414  */
PMU_2P5SetRegulatorOutputVoltage(PMU_Type * base,uint32_t value)415 static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
416 {
417     base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value);
418 }
419 
420 /*!
421  * @brief Adjust the 2P5 regulator brownout offset voltage.
422  *
423  * Adjust the regulator brownout offset voltage in 25mV steps. The reset
424  * brown-offset is 175mV below the programmed target code.
425  * Brownout target = OUTPUT_TRG - BO_OFFSET.
426  * Some steps may be irrelevant because of input supply limitations or load operation.
427  *
428  * @param base PMU peripheral base address.
429  * @param value Setting value for the brownout offset. The available range is in 3-bit.
430  */
PMU_2P5SetBrownoutOffsetVoltage(PMU_Type * base,uint32_t value)431 static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
432 {
433     base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value);
434 }
435 
436 /*!
437  * @brief Enable the pull-down circuitry in the 2P5 regulator.
438  *
439  * @param base PMU peripheral base address.
440  * @param enable Enable the feature or not.
441  */
PMU_2P5EnablePullDown(PMU_Type * base,bool enable)442 static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable)
443 {
444     if (enable)
445     {
446         base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
447     }
448     else
449     {
450         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
451     }
452 }
453 
454 /*!
455  * @brief Enable the pull-down circuitry in the 2P5 regulator.
456  * @deprecated Do not use this function.  It has been superceded by @ref PMU_2P5EnablePullDown.
457  */
PMU_2P1EnablePullDown(PMU_Type * base,bool enable)458 static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable)
459 {
460     if (enable)
461     {
462         base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
463     }
464     else
465     {
466         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
467     }
468 }
469 
470 /*!
471  * @brief Enable the current-limit circuitry in the 2P5 regulator.
472  *
473  * @param base PMU peripheral base address.
474  * @param enable Enable the feature or not.
475  */
PMU_2P5EnableCurrentLimit(PMU_Type * base,bool enable)476 static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable)
477 {
478     if (enable)
479     {
480         base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK;
481     }
482     else
483     {
484         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK;
485     }
486 }
487 
488 /*!
489  * @brief Enable the brownout circuitry in the 2P5 regulator.
490  *
491  * @param base PMU peripheral base address.
492  * @param enable Enable the feature or not.
493  */
PMU_2P5nableBrownout(PMU_Type * base,bool enable)494 static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable)
495 {
496     if (enable)
497     {
498         base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK;
499     }
500     else
501     {
502         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK;
503     }
504 }
505 
506 /*!
507  * @brief Enable the 2P5 regulator output.
508  *
509  * @param base PMU peripheral base address.
510  * @param enable Enable the feature or not.
511  */
PMU_2P5EnableOutput(PMU_Type * base,bool enable)512 static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable)
513 {
514     if (enable)
515     {
516         base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK;
517     }
518     else
519     {
520         base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK;
521     }
522 }
523 
524 /* @} */
525 
526 /*!
527  * @name Core Regulator
528  * @{
529  */
530 
531 /*!
532  * @brief Increase the gate drive on power gating FETs.
533  *
534  * If set, increases the gate drive on power gating FETs to reduce leakage in the off state.
535  * Care must be taken to apply this bit only when the input supply voltage to the power FET
536  * is less than 1.1V.
537  * NOTE: This bit should only be used in low-power modes where the external input supply voltage
538  * is nominally 0.9V.
539  *
540  * @param base PMU peripheral base address.
541  * @param enable Enable the feature or not.
542  */
PMU_CoreEnableIncreaseGateDrive(PMU_Type * base,bool enable)543 static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable)
544 {
545     if (enable)
546     {
547         base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK;
548     }
549     else
550     {
551         base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK;
552     }
553 }
554 
555 /*!
556  * @brief Set the CORE regulator voltage ramp rate.
557  *
558  * @param base PMU peripheral base address.
559  * @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t.
560  */
PMU_CoreSetRegulatorVoltageRampRate(PMU_Type * base,pmu_core_reg_voltage_ramp_rate_t option)561 static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option)
562 {
563     base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option);
564 }
565 
566 /*!
567  * @brief Define the target voltage for the SOC power domain.
568  *
569  * Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core
570  * voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
571  * - 0x00 : Power gated off.
572  * - 0x01 : Target core voltage = 0.725V
573  * - 0x02 : Target core voltage = 0.750V
574  * - ...
575  * - 0x10 : Target core voltage = 1.100V
576  * - ...
577  * - 0x1e : Target core voltage = 1.450V
578  * - 0x1F : Power FET switched full on. No regulation.
579  * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
580  * datasheet Operating Ranges table for the allowed voltages.
581  *
582  * @param base PMU peripheral base address.
583  * @param value Setting value for target voltage. 5-bit available
584  */
PMU_CoreSetSOCDomainVoltage(PMU_Type * base,uint32_t value)585 static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value)
586 {
587     base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value);
588 }
589 
590 /*!
591  * @brief Define the target voltage for the ARM Core power domain.
592  *
593  * Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core
594  * voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
595  * - 0x00 : Power gated off.
596  * - 0x01 : Target core voltage = 0.725V
597  * - 0x02 : Target core voltage = 0.750V
598  * - ...
599  * - 0x10 : Target core voltage = 1.100V
600  * - ...
601  * - 0x1e : Target core voltage = 1.450V
602  * - 0x1F : Power FET switched full on. No regulation.
603  * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
604  * datasheet Operating Ranges table for the allowed voltages.
605  *
606  * @param base PMU peripheral base address.
607  * @param value Setting value for target voltage. 5-bit available
608  */
PMU_CoreSetARMCoreDomainVoltage(PMU_Type * base,uint32_t value)609 static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value)
610 {
611     base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value);
612 }
613 
614 /* @} */
615 
616 #if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
617 /*!
618  * @name Power Gate Controller & other
619  * @{
620  */
621 
622 /*!
623  * @brief Gate the power to modules.
624  *
625  * @param base PMU peripheral base address.
626  * @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
627  */
PMU_GatePower(PMU_Type * base,uint32_t gates)628 static inline void PMU_GatePower(PMU_Type *base, uint32_t gates)
629 {
630     base->LOWPWR_CTRL_SET = gates;
631 }
632 
633 /*!
634  * @brief Ungate the power to modules.
635  *
636  * @param base PMU peripheral base address.
637  * @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
638  */
PMU_UngatePower(PMU_Type * base,uint32_t gates)639 static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates)
640 {
641     base->LOWPWR_CTRL_CLR = gates;
642 }
643 
644 /*!
645  * @brief Enable the low power bandgap.
646  *
647  * @param base PMU peripheral base address.
648  * @param enable Enable the low power bandgap or use the normal power bandgap.
649  * @
650  */
PMU_EnableLowPowerBandgap(PMU_Type * base,bool enable)651 static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable)
652 {
653     if (enable)
654     {
655         base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */
656     }
657     else
658     {
659         base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */
660     }
661 }
662 #endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
663 /* @} */
664 
665 #if defined(__cplusplus)
666 }
667 #endif /* __cplusplus*/
668 
669 /*! @}*/
670 
671 #endif /* _FSL_PMU_H_*/
672