Searched refs:kDSPI_MasterCtar0 (Results 1 – 3 of 3) sorted by relevance
442 …(dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SH… in DSPI_EdmaSend()453 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL; in DSPI_EdmaSend()459 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL; in DSPI_EdmaSend()465 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL; in DSPI_EdmaSend()509 …(dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SH… in DSPI_EdmaReceive()520 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL; in DSPI_EdmaReceive()526 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI1_MASTER_PCS_PIN_SEL; in DSPI_EdmaReceive()532 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI2_MASTER_PCS_PIN_SEL; in DSPI_EdmaReceive()579 …(dspi->resource->base->CTAR[kDSPI_MasterCtar0] & (uint32_t)SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SH… in DSPI_EdmaTransfer()590 xfer.configFlags = (uint32_t)kDSPI_MasterCtar0 | (uint32_t)RTE_SPI0_MASTER_PCS_PIN_SEL; in DSPI_EdmaTransfer()[all …]
211 … (uint32_t)kDSPI_MasterCtar0 | (uint32_t)kDSPI_MasterPcs0 | (uint32_t)kDSPI_MasterPcsContinuous; in HAL_SpiMasterTransferBlocking()229 … (uint32_t)kDSPI_MasterCtar0 | (uint32_t)kDSPI_MasterPcs0 | (uint32_t)kDSPI_MasterPcsContinuous; in HAL_SpiMasterTransferNonBlocking()285 … (uint32_t)kDSPI_MasterCtar0 | (uint32_t)kDSPI_MasterPcs0 | (uint32_t)kDSPI_MasterPcsContinuous; in HAL_SpiSlaveTransferNonBlocking()
183 … kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ enumerator
