1 /* 2 * Copyright 2017, 2019-2020 NXP 3 * All rights reserved. 4 * 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_DPU_H_ 10 #define _FSL_DPU_H_ 11 12 #include "fsl_common.h" 13 14 /*! 15 * @addtogroup dpu 16 * @{ 17 */ 18 19 /******************************************************************************* 20 * Definitions 21 ******************************************************************************/ 22 23 /*! @name Driver version */ 24 /*@{*/ 25 /*! @brief Driver version. */ 26 #define FSL_DPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) 27 /*@}*/ 28 29 /*! @brief DPU palette entery number. */ 30 #define DPU_PALETTE_ENTRY_NUM (256U) 31 32 /*! @brief DPU fetch unit burst length, should be less than 16. */ 33 #ifndef DPU_FETCH_UNIT_BURST_LENGTH 34 #define DPU_FETCH_UNIT_BURST_LENGTH (16U) 35 #endif 36 37 /*! @brief DPU fetch unit burst size. 38 * 39 * If prefetch is used, the frame buffer stride and base address should be 40 * aligned to the burst size. 41 */ 42 #define DPU_FETCH_UNIT_BURST_SIZE (8U * DPU_FETCH_UNIT_BURST_LENGTH) 43 44 #define DPU_USE_GENERATE_HEADER 0 45 46 /*! 47 * @name Macros for the DPU unit input source. 48 * 49 * The DPU unit input source is controlled by the register pixencfg_\<unit\>_dynamic, 50 * the macros @ref DPU_MAKE_SRC_REG1, @ref DPU_MAKE_SRC_REG2, and @ref DPU_MAKE_SRC_REG3 51 * are used to define the register value of pixencfg_\<unit\>_dynamic. @ref DPU_MAKE_SRC_REG1 52 * defines register for DPU unit that has one input source. Accordingly, 53 * @ref DPU_MAKE_SRC_REG2 and @ref DPU_MAKE_SRC_REG3 are used to define the register for 54 * units that have two and three input source. See @ref _dpu_unit_source for the 55 * input source details. 56 * @{ 57 */ 58 /*! Macro for one input source unit. */ 59 #define DPU_MAKE_SRC_REG1(src) (((uint32_t)(src)) & 0x3FU) 60 /*! Macro for two input source unit. */ 61 #define DPU_MAKE_SRC_REG2(primSrc, secSrc) \ 62 ((((uint32_t)(primSrc)) & 0x3FU) | (((((uint32_t)(secSrc)) & 0x3FU) << 0x8U))) 63 /*! Macro for three input source unit. */ 64 #define DPU_MAKE_SRC_REG3(primSrc, secSrc, tertSrc) \ 65 ((((uint32_t)(primSrc)) & 0x3FU) | ((((uint32_t)(secSrc)) & 0x3FU) << 0x8U) | \ 66 (((((uint32_t)(tertSrc)) & 0x3FU) << 0x10U))) 67 /*!@}*/ 68 69 /*! @brief Define the const value that write to \<unit\>_ConstantColor. */ 70 #define DPU_MAKE_CONST_COLOR(red, green, blue, alpha) \ 71 ((((uint32_t)(red)) << 24U) | (((uint32_t)(green)) << 16U) | (((uint32_t)(blue)) << 8U) | ((uint32_t)(alpha))) 72 73 /*! 74 * @name Macros define the FrameGen interrupt mode. 75 * 76 * These macros are used by the function @ref DPU_SetFrameGenInterruptConfig 77 * to set the FrameGen interrupt mode. 78 * @{ 79 */ 80 /*! Disable FrameGen interrupt. */ 81 #define DPU_FRAME_GEN_INT_DISABLE 0U 82 /*! Generate FrameGen interrupt every line at the colnum @p colNum. */ 83 #define DPU_FRAME_GEN_INT_PER_LINE(colNum) ((1U << 31U) | (1U << 15U) | (((uint32_t)colNum) & (0x3FFFU))) 84 /*! Generate FrameGen interrupt every frame at the row @p rowNum. */ 85 #define DPU_FRAME_GEN_INT_PER_FRAME(rowNum) ((1U << 31U) | (((uint32_t)rowNum) & 0x3FFF0000U)) 86 /*!@}*/ 87 88 /* 89 * Macros to define the DPU unit, these are internal macros and should not be 90 * used by upper layer. 91 * 92 * type: Type of the unit, see _dpu_unit_type. 93 * attr: Unit attribute, OR'ed value of _dpu_unit_attr. 94 * offset: Control block register offset in DPU memory map. 95 */ 96 #define DPU_UNIT_TYPE_SHIFT (24U) 97 #define DPU_UNIT_TYPE_MASK (0xFF000000U) 98 #define DPU_UNIT_ATTR_SHIFT (20U) 99 #define DPU_UNIT_ATTR_MASK (0x00F00000U) 100 #define DPU_UNIT_OFFSET_SHIFT (0U) 101 #define DPU_UNIT_OFFSET_MASK (0x0001FFFFU) 102 103 #define DPU_MAKE_UNIT_TYPE(type) (((uint32_t)(type)) << DPU_UNIT_TYPE_SHIFT) 104 #define DPU_MAKE_UNIT_ATTR(attr) (((uint32_t)(attr)) << DPU_UNIT_ATTR_SHIFT) 105 #define DPU_MAKE_UNIT_OFFSET(offset) (((uint32_t)(offset)) << DPU_UNIT_OFFSET_SHIFT) 106 107 #define DPU_GET_UNIT_TYPE(unit) ((((uint32_t)(unit)) & DPU_UNIT_TYPE_MASK) >> DPU_UNIT_TYPE_SHIFT) 108 #define DPU_GET_UNIT_ATTR(unit) ((((uint32_t)(unit)) & DPU_UNIT_ATTR_MASK) >> DPU_UNIT_ATTR_SHIFT) 109 #define DPU_GET_UNIT_OFFSET(unit) ((((uint32_t)(unit)) & DPU_UNIT_OFFSET_MASK) >> DPU_UNIT_OFFSET_SHIFT) 110 111 #define DPU_MAKE_UNIT(type, attr, offset) \ 112 (DPU_MAKE_UNIT_TYPE(type) | DPU_MAKE_UNIT_ATTR(attr) | DPU_MAKE_UNIT_OFFSET(offset)) 113 114 /* DPU init offset definitions, these offset are for driver internal use only. */ 115 #define DPU_UNIT_OFFSET(unit) (uint32_t)(&((IRIS_MVPL_Type *)0)->unit) 116 #if DPU_USE_GENERATE_HEADER 117 #define DPU_FETCH_ECO9_OFFSET DPU_UNIT_OFFSET(FETCHECO9) 118 #define DPU_FETCH_DECODE9_OFFSET DPU_UNIT_OFFSET(FETCHDECODE9) 119 #define DPU_FETCH_WARP9_OFFSET DPU_UNIT_OFFSET(FETCHWARP9) 120 #define DPU_BLITBLEND9_OFFSET DPU_UNIT_OFFSET(BLITBLEND9) 121 #define DPU_ROP9_OFFSET DPU_UNIT_OFFSET(ROP9) 122 #define DPU_STORE9_OFFSET DPU_UNIT_OFFSET(STORE9) 123 #define DPU_H_SCALER9_OFFSET DPU_UNIT_OFFSET(H_SCALER9) 124 #define DPU_V_SCALER9_OFFSET DPU_UNIT_OFFSET(V_SCALER9) 125 #define DPU_CONST_FRAME0_OFFSET DPU_UNIT_OFFSET(CONSTFRAME0) 126 #define DPU_EXT_DST0_OFFSET DPU_UNIT_OFFSET(EXTDST0) 127 #define DPU_CONST_FRAME4_OFFSET DPU_UNIT_OFFSET(CONSTFRAME4) 128 #define DPU_EXT_DST4_OFFSET DPU_UNIT_OFFSET(EXTDST4) 129 #define DPU_CONST_FRAME1_OFFSET DPU_UNIT_OFFSET(CONSTFRAME1) 130 #define DPU_EXT_DST1_OFFSET DPU_UNIT_OFFSET(EXTDST1) 131 #define DPU_CONST_FRAME5_OFFSET DPU_UNIT_OFFSET(CONSTFRAME5) 132 #define DPU_EXT_DST5_OFFSET DPU_UNIT_OFFSET(EXTDST5) 133 #define DPU_FETCH_WARP2_OFFSET DPU_UNIT_OFFSET(FETCHWARP2) 134 #define DPU_FETCH_ECO2_OFFSET DPU_UNIT_OFFSET(FETCHECO2) 135 #define DPU_FETCH_DECODE0_OFFSET DPU_UNIT_OFFSET(FETCHDECODE0) 136 #define DPU_FETCH_ECO0_OFFSET DPU_UNIT_OFFSET(FETCHECO0) 137 #define DPU_FETCH_DECODE1_OFFSET DPU_UNIT_OFFSET(FETCHDECODE1) 138 #define DPU_FETCH_ECO1_OFFSET DPU_UNIT_OFFSET(FETCHECO1) 139 #define DPU_FETCH_LAYER0_OFFSET DPU_UNIT_OFFSET(FETCHLAYER0) 140 #define DPU_H_SCALER4_OFFSET DPU_UNIT_OFFSET(H_SCALER4) 141 #define DPU_V_SCALER4_OFFSET DPU_UNIT_OFFSET(V_SCALER4) 142 #define DPU_H_SCALER5_OFFSET DPU_UNIT_OFFSET(HSCALER5) 143 #define DPU_V_SCALER5_OFFSET DPU_UNIT_OFFSET(V_SCALER5) 144 #define DPU_LAYER_BLEND0_OFFSET DPU_UNIT_OFFSET(LAYERBLEND0) 145 #define DPU_LAYER_BLEND1_OFFSET DPU_UNIT_OFFSET(LAYERBLEND1) 146 #define DPU_LAYER_BLEND2_OFFSET DPU_UNIT_OFFSET(LAYERBLEND2) 147 #define DPU_LAYER_BLEND3_OFFSET DPU_UNIT_OFFSET(LAYERBLEND3) 148 #define DPU_FRAME_GEN0_OFFSET DPU_UNIT_OFFSET(FRAMEGEN0) 149 #define DPU_TCON0_OFFSET DPU_UNIT_OFFSET(TCON0) 150 #define DPU_SIG0_OFFSET DPU_UNIT_OFFSET(SIG0) 151 #define DPU_FRAME_GEN1_OFFSET DPU_UNIT_OFFSET(FRAMEGEN1) 152 #define DPU_TCON1_OFFSET DPU_UNIT_OFFSET(TCON1) 153 #define DPU_SIG1_OFFSET DPU_UNIT_OFFSET(SIG1) 154 #define DPU_PIPELINE_EXTDST0_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST0_LOCKUNLOCK) 155 #define DPU_PIPELINE_EXTDST1_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST1_LOCKUNLOCK) 156 #define DPU_PIPELINE_EXTDST4_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST4_LOCKUNLOCK) 157 #define DPU_PIPELINE_EXTDST5_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST5_LOCKUNLOCK) 158 #define DPU_PIPELINE_STORE9_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.STORE9_LOCKUNLOCK) 159 #else 160 #define DPU_COMCTRL_OFFSET 0x0000U 161 #define DPU_FETCH_DECODE9_OFFSET 0x1000U 162 #define DPU_FETCH_WARP9_OFFSET 0x1800U 163 #define DPU_FETCH_ECO9_OFFSET 0x1C00U 164 #define DPU_ROP9_OFFSET 0x2000U 165 #define DPU_H_SCALER9_OFFSET 0x3000U 166 #define DPU_V_SCALER9_OFFSET 0x3400U 167 #define DPU_BLITBLEND9_OFFSET 0x3C00U 168 #define DPU_STORE9_OFFSET 0x4000U 169 #define DPU_CONST_FRAME0_OFFSET 0x4400U 170 #define DPU_EXT_DST0_OFFSET 0x4800U 171 #define DPU_CONST_FRAME4_OFFSET 0x4c00U 172 #define DPU_EXT_DST4_OFFSET 0x5000U 173 #define DPU_CONST_FRAME1_OFFSET 0x5400U 174 #define DPU_EXT_DST1_OFFSET 0x5800U 175 #define DPU_CONST_FRAME5_OFFSET 0x5c00U 176 #define DPU_EXT_DST5_OFFSET 0x6000U 177 #define DPU_FETCH_WARP2_OFFSET 0x6400U 178 #define DPU_FETCH_ECO2_OFFSET 0x6800U 179 #define DPU_FETCH_DECODE0_OFFSET 0x6c00U 180 #define DPU_FETCH_ECO0_OFFSET 0x7400U 181 #define DPU_FETCH_DECODE1_OFFSET 0x7800U 182 #define DPU_FETCH_ECO1_OFFSET 0x8000U 183 #define DPU_FETCH_LAYER0_OFFSET 0x8400U 184 #define DPU_H_SCALER4_OFFSET 0x9000U 185 #define DPU_V_SCALER4_OFFSET 0x9400U 186 #define DPU_H_SCALER5_OFFSET 0x9c00U 187 #define DPU_V_SCALER5_OFFSET 0xa000U 188 #define DPU_LAYER_BLEND0_OFFSET 0xa400U 189 #define DPU_LAYER_BLEND1_OFFSET 0xa800U 190 #define DPU_LAYER_BLEND2_OFFSET 0xac00U 191 #define DPU_LAYER_BLEND3_OFFSET 0xb000U 192 #define DPU_DISENGCONF_OFFSET 0xb400U 193 #define DPU_FRAME_GEN0_OFFSET 0xb800U 194 #define DPU_TCON0_OFFSET 0xc800U 195 #define DPU_SIG0_OFFSET 0xd000U 196 #define DPU_FRAME_GEN1_OFFSET 0xd400U 197 #define DPU_TCON1_OFFSET 0xe400U 198 #define DPU_SIG1_OFFSET 0xec00U 199 #define DPU_PIPELINE_EXTDST0_OFFSET 0x0980U 200 #define DPU_PIPELINE_EXTDST1_OFFSET 0x0a00U 201 #define DPU_PIPELINE_EXTDST4_OFFSET 0x09C0U 202 #define DPU_PIPELINE_EXTDST5_OFFSET 0x0a40U 203 #define DPU_PIPELINE_STORE9_OFFSET 0x0940U 204 205 #define DPU_ROP_CONTROL_Mode_MASK (1U << 0U) 206 #define DPU_ROP_CONTROL_RedMode_MASK (1U << 7U) 207 #define DPU_ROP_CONTROL_GreenMode_MASK (1U << 6U) 208 #define DPU_ROP_CONTROL_BlueMode_MASK (1U << 5U) 209 #define DPU_ROP_CONTROL_AlphaMode_MASK (1U << 4U) 210 #define DPU_ROP_CONTROL_TertDiv2_MASK (1U << 10U) 211 #define DPU_ROP_CONTROL_SecDiv2_MASK (1U << 9U) 212 #define DPU_ROP_CONTROL_PrimDiv2_MASK (1U << 8U) 213 214 #define DPU_DISENGCONF_POLARITYCTRL_PixInv_MASK (1U << 3U) 215 #define DPU_DISENGCONF_POLARITYCTRL_PolEn_MASK (1U << 2U) 216 #define DPU_DISENGCONF_POLARITYCTRL_PolVs_MASK (1U << 1U) 217 #define DPU_DISENGCONF_POLARITYCTRL_PolHs_MASK (1U << 0U) 218 219 #define DPU_SIG_EVALCONTROL_EnGlobalPanic_MASK (1U << 17U) 220 #define DPU_SIG_EVALCONTROL_EnLocalPanic_MASK (1U << 16U) 221 #define DPU_SIG_EVALCONTROL_AlphaInv_MASK (1U << 9U) 222 #define DPU_SIG_EVALCONTROL_AlphaMask_MASK (1U << 8U) 223 #define DPU_SIG_EVALCONTROL_EnCRC_MASK (1U << 1U) 224 #define DPU_SIG_EVALCONTROL_EnEvalWin_MASK (1U << 0U) 225 226 #define DPU_SIG_STATUS_StsSigIdle_MASK (1U << 20U) 227 #define DPU_SIG_STATUS_StsSigValid_MASK (1U << 16U) 228 #define DPU_SIG_STATUS_StsSigError_MASK (0xFU << 0U) 229 230 #define DPU_SIG_EVALUPPERLEFT_XEvalUpperLeft_SHIFT (0U) 231 #define DPU_SIG_EVALUPPERLEFT_YEvalUpperLeft_SHIFT (16U) 232 #define DPU_SIG_EVALLOWERRIGHT_XEvalLowerRight_SHIFT (0U) 233 #define DPU_SIG0_EVALLOWERRIGHT_YEvalLowerRight_SHIFT (16U) 234 235 #define DPU_SIG_SHADOWLOAD_ShdLdReq_MASK (0xFFU) 236 #endif 237 238 /* DPU unit type, internal used for DPU_MAKE_UNIT, _dpu_unit_type. */ 239 enum 240 { 241 kDPU_Pipeline, 242 kDPU_BlitBlend, 243 kDPU_Rop, 244 kDPU_FetchDecode, 245 kDPU_FetchWarp, 246 kDPU_FetchEco, 247 kDPU_FetchLayer, 248 kDPU_HScaler, 249 kDPU_VScaler, 250 kDPU_ConstFrame, 251 kDPU_ExtDst, 252 kDPU_LayerBlend, 253 kDPU_Store, 254 }; 255 256 /* DPU unit attribute, internal used for DPU_MAKE_UNIT, _dpu_unit_attr. */ 257 enum 258 { 259 kDPU_UnitAttrIsFetch = (1U << 0U), /* Is fetch unit. */ 260 kDPU_UnitAttrHasSrc = (1U << 1U), /* Has input source selection. */ 261 kDPU_UnitAttrNoShdow = (1U << 2U), /* Does not support shadow load. */ 262 kDPU_UnitAttrSubLayer = (1U << 3U) /* Has sub layer. */ 263 }; 264 265 /*! @brief DPU units. */ 266 typedef enum _dpu_unit 267 { 268 /* 269 * In DPU driver, the pipeline is also treated as a unit. For example, the 270 * kDPU_PipelineExtDst4 means the pipeline with ExtDst4 as its endpoint. 271 * The driver uses the endpoint control registers in "Pixel Engine Top Level" 272 * as the pipeline's control block. 273 */ 274 kDPU_PipelineStore9 = DPU_MAKE_UNIT(kDPU_Pipeline, 0U, DPU_PIPELINE_STORE9_OFFSET), 275 kDPU_FetchWarp9 = DPU_MAKE_UNIT( 276 kDPU_FetchWarp, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc | kDPU_UnitAttrSubLayer, DPU_FETCH_WARP9_OFFSET), 277 kDPU_FetchDecode9 = 278 DPU_MAKE_UNIT(kDPU_FetchDecode, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_DECODE9_OFFSET), 279 kDPU_FetchEco9 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO9_OFFSET), 280 kDPU_Hscaler9 = DPU_MAKE_UNIT(kDPU_HScaler, kDPU_UnitAttrHasSrc, DPU_H_SCALER9_OFFSET), 281 kDPU_Vscaler9 = DPU_MAKE_UNIT(kDPU_VScaler, kDPU_UnitAttrHasSrc, DPU_V_SCALER9_OFFSET), 282 283 kDPU_Rop9 = DPU_MAKE_UNIT(kDPU_Rop, kDPU_UnitAttrHasSrc, DPU_ROP9_OFFSET), 284 kDPU_BlitBlend9 = DPU_MAKE_UNIT(kDPU_BlitBlend, kDPU_UnitAttrHasSrc, DPU_BLITBLEND9_OFFSET), 285 kDPU_Store9 = DPU_MAKE_UNIT(kDPU_Store, kDPU_UnitAttrHasSrc, DPU_STORE9_OFFSET), 286 287 kDPU_PipelineExtDst0 = DPU_MAKE_UNIT(kDPU_Pipeline, 0U, DPU_PIPELINE_EXTDST0_OFFSET), 288 kDPU_PipelineExtDst1 = DPU_MAKE_UNIT(kDPU_Pipeline, 0U, DPU_PIPELINE_EXTDST1_OFFSET), 289 kDPU_PipelineExtDst4 = DPU_MAKE_UNIT(kDPU_Pipeline, 0U, DPU_PIPELINE_EXTDST4_OFFSET), 290 kDPU_PipelineExtDst5 = DPU_MAKE_UNIT(kDPU_Pipeline, 0U, DPU_PIPELINE_EXTDST5_OFFSET), 291 kDPU_ConstFrame0 = DPU_MAKE_UNIT(kDPU_ConstFrame, 0U, DPU_CONST_FRAME0_OFFSET), 292 kDPU_ExtDst0 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST0_OFFSET), 293 kDPU_ConstFrame4 = DPU_MAKE_UNIT(kDPU_ConstFrame, 0U, DPU_CONST_FRAME4_OFFSET), 294 kDPU_ExtDst4 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST4_OFFSET), 295 kDPU_ConstFrame1 = DPU_MAKE_UNIT(kDPU_ConstFrame, 0U, DPU_CONST_FRAME1_OFFSET), 296 kDPU_ExtDst1 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST1_OFFSET), 297 kDPU_ConstFrame5 = DPU_MAKE_UNIT(kDPU_ConstFrame, 0U, DPU_CONST_FRAME5_OFFSET), 298 kDPU_ExtDst5 = DPU_MAKE_UNIT(kDPU_ExtDst, kDPU_UnitAttrHasSrc, DPU_EXT_DST5_OFFSET), 299 kDPU_FetchWarp2 = DPU_MAKE_UNIT( 300 kDPU_FetchWarp, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc | kDPU_UnitAttrSubLayer, DPU_FETCH_WARP2_OFFSET), 301 kDPU_FetchEco2 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO2_OFFSET), 302 kDPU_FetchDecode0 = 303 DPU_MAKE_UNIT(kDPU_FetchDecode, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_DECODE0_OFFSET), 304 kDPU_FetchEco0 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO0_OFFSET), 305 kDPU_FetchDecode1 = 306 DPU_MAKE_UNIT(kDPU_FetchDecode, kDPU_UnitAttrIsFetch | kDPU_UnitAttrHasSrc, DPU_FETCH_DECODE1_OFFSET), 307 kDPU_FetchEco1 = DPU_MAKE_UNIT(kDPU_FetchEco, kDPU_UnitAttrIsFetch, DPU_FETCH_ECO1_OFFSET), 308 kDPU_FetchLayer0 = 309 DPU_MAKE_UNIT(kDPU_FetchLayer, kDPU_UnitAttrIsFetch | kDPU_UnitAttrSubLayer, DPU_FETCH_LAYER0_OFFSET), 310 kDPU_Hscaler4 = DPU_MAKE_UNIT(kDPU_HScaler, kDPU_UnitAttrHasSrc, DPU_H_SCALER4_OFFSET), 311 kDPU_Vscaler4 = DPU_MAKE_UNIT(kDPU_VScaler, kDPU_UnitAttrHasSrc, DPU_V_SCALER4_OFFSET), 312 kDPU_Hscaler5 = DPU_MAKE_UNIT(kDPU_HScaler, kDPU_UnitAttrHasSrc, DPU_H_SCALER5_OFFSET), 313 kDPU_Vscaler5 = DPU_MAKE_UNIT(kDPU_VScaler, kDPU_UnitAttrHasSrc, DPU_V_SCALER5_OFFSET), 314 kDPU_LayerBlend0 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND0_OFFSET), 315 kDPU_LayerBlend1 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND1_OFFSET), 316 kDPU_LayerBlend2 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND2_OFFSET), 317 kDPU_LayerBlend3 = DPU_MAKE_UNIT(kDPU_LayerBlend, kDPU_UnitAttrHasSrc, DPU_LAYER_BLEND3_OFFSET), 318 } dpu_unit_t; 319 320 /*! @brief DPU interrupt. */ 321 enum _dpu_interrupt 322 { 323 kDPU_Group0Store9ShadowLoadInterrupt = (1U << 0U), /*!< Store9 shadow load interrupt. */ 324 kDPU_Group0Store9FrameCompleteInterrupt = (1U << 1U), /*!< Store9 frame complete interrupt. */ 325 kDPU_Group0Store9SeqCompleteInterrupt = (1U << 2U), /*!< Store9 sequence complete interrupt. */ 326 kDPU_Group0ExtDst0ShadowLoadInterrupt = (1U << 3U), /*!< ExtDst0 shadow load interrupt. */ 327 kDPU_Group0ExtDst0FrameCompleteInterrupt = (1U << 4U), /*!< ExtDst0 frame complete interrupt. */ 328 kDPU_Group0ExtDst0SeqCompleteInterrupt = (1U << 5U), /*!< ExtDst0 sequence complete interrupt. */ 329 kDPU_Group0ExtDst4ShadowLoadInterrupt = (1U << 6U), /*!< ExtDst4 shadow load interrupt. */ 330 kDPU_Group0ExtDst4FrameCompleteInterrupt = (1U << 7U), /*!< ExtDst4 frame complete interrupt. */ 331 kDPU_Group0ExtDst4SeqCompleteInterrupt = (1U << 8U), /*!< ExtDst4 sequence complete interrupt. */ 332 kDPU_Group0ExtDst1ShadowLoadInterrupt = (1U << 9U), /*!< ExtDst1 shadow load interrupt. */ 333 kDPU_Group0ExtDst1FrameCompleteInterrupt = (1U << 10U), /*!< ExtDst1 frame complete interrupt. */ 334 kDPU_Group0ExtDst1SeqCompleteInterrupt = (1U << 11U), /*!< ExtDst1 sequence complete interrupt. */ 335 kDPU_Group0ExtDst5ShadowLoadInterrupt = (1U << 12U), /*!< ExtDst5 shadow load interrupt. */ 336 kDPU_Group0ExtDst5FrameCompleteInterrupt = (1U << 13U), /*!< ExtDst5 frame complete interrupt. */ 337 kDPU_Group0ExtDst5SeqCompleteInterrupt = (1U << 14U), /*!< ExtDst5 sequence complete interrupt. */ 338 kDPU_Group0Display0ShadowLoadInterrupt = (1U << 15U), /*!< Display stream 0 shadow load interrupt. */ 339 kDPU_Group0Display0FrameCompleteInterrupt = (1U << 16U), /*!< Display stream 0 frame complete interrupt. */ 340 kDPU_Group0Display0SeqCompleteInterrupt = (1U << 17U), /*!< Display stream 0 sequence complete interrupt. */ 341 kDPU_Group0FrameGen0Int0Interrupt = (1U << 18U), /*!< FrameGen 0 interrupt 0. */ 342 kDPU_Group0FrameGen0Int1Interrupt = (1U << 19U), /*!< FrameGen 0 interrupt 1. */ 343 kDPU_Group0FrameGen0Int2Interrupt = (1U << 20U), /*!< FrameGen 0 interrupt 2. */ 344 kDPU_Group0FrameGen0Int3Interrupt = (1U << 21U), /*!< FrameGen 0 interrupt 3. */ 345 kDPU_Group0Sig0ShadowLoadInterrupt = (1U << 22U), /*!< Sig0 shadow load interrupt. */ 346 kDPU_Group0Sig0ValidInterrupt = (1U << 23U), /*!< Sig0 measurement valid interrupt. */ 347 kDPU_Group0Sig0ErrorInterrupt = (1U << 24U), /*!< Sig0 error interrupt. */ 348 kDPU_Group0Display1ShadowLoadInterrupt = (1U << 25U), /*!< Display stream 1 shadow load interrupt. */ 349 kDPU_Group0Display1FrameCompleteInterrupt = (1U << 26U), /*!< Display stream 1 frame complete interrupt. */ 350 kDPU_Group0Display1SeqCompleteInterrupt = (1U << 27U), /*!< Display stream 1 sequence complete interrupt. */ 351 kDPU_Group0FrameGen1Int0Interrupt = (1U << 28U), /*!< FrameGen 1 interrupt 0. */ 352 kDPU_Group0FrameGen1Int1Interrupt = (1U << 29U), /*!< FrameGen 1 interrupt 1. */ 353 kDPU_Group0FrameGen1Int2Interrupt = (1U << 30U), /*!< FrameGen 1 interrupt 2. */ 354 kDPU_Group0FrameGen1Int3Interrupt = (1U << 31U), /*!< FrameGen 1 interrupt 3. */ 355 kDPU_Group1Sig1ShadowLoadInterrupt = (1U << 0U), /*!< Sig1 shadow load interrupt. */ 356 kDPU_Group1Sig1ValidInterrupt = (1U << 1U), /*!< Sig1 measurement valid interrupt. */ 357 kDPU_Group1Sig1ErrorInterrupt = (1U << 2U), /*!< Sig1 error interrupt. */ 358 kDPU_Group1CmdSeqErrorInterrupt = (1U << 4U), /*!< Command sequencer error interrupt. */ 359 kDPU_Group1SoftwareInt0Interrupt = (1U << 5U), /*!< Common software interrupt 0. */ 360 kDPU_Group1SoftwareInt1Interrupt = (1U << 6U), /*!< Common software interrupt 1. */ 361 kDPU_Group1SoftwareInt2Interrupt = (1U << 7U), /*!< Common software interrupt 2. */ 362 kDPU_Group1SoftwareInt3Interrupt = (1U << 8U), /*!< Common software interrupt 3. */ 363 kDPU_Group1FrameGen0PrimSyncOnInterrupt = (1U << 9U), /*!< Safety stream 0 synchronized interrupt. */ 364 kDPU_Group1FrameGen0PrimSyncOffInterrupt = (1U << 10U), /*!< Safety stream 0 loss synchronization interrupt. */ 365 kDPU_Group1FrameGen0SecSyncOnInterrupt = (1U << 11U), /*!< Content stream 0 synchronized interrupt. */ 366 kDPU_Group1FrameGen0SecSyncOffInterrupt = (1U << 12U), /*!< Content stream 0 loss synchronization interrupt. */ 367 kDPU_Group1FrameGen1PrimSyncOnInterrupt = (1U << 13U), /*!< Safety stream 1 synchronized interrupt. */ 368 kDPU_Group1FrameGen1PrimSyncOffInterrupt = (1U << 14U), /*!< Safety stream 1 loss synchronization interrupt. */ 369 kDPU_Group1FrameGen1SecSyncOnInterrupt = (1U << 15U), /*!< Content stream 1 synchronized interrupt. */ 370 kDPU_Group1FrameGen1SecSyncOffInterrupt = (1U << 16U), /*!< Content stream 1 loss synchronization interrupt. */ 371 }; 372 373 /*! @brief DPU unit input source. */ 374 enum _dpu_unit_source 375 { 376 kDPU_UnitSrcNone = 0, /*!< Disable the input source. */ 377 kDPU_UnitSrcFetchDecode9 = 1U, /*!< The input source is fetch decode 9. */ 378 kDPU_UnitSrcFetchWarp9 = 2U, /*!< The input source is fetch warp 9. */ 379 kDPU_UnitSrcFetchEco9 = 3U, /*!< The input source is fetch eco 9. */ 380 kDPU_UnitSrcRop9 = 4U, /*!< The input source is rop 9. */ 381 kDPU_UnitSrcClut9 = 5U, /*!< The input source is CLUT 9 */ 382 kDPU_UnitSrcMatrix9 = 6U, /*!< The input source is matrix 9. */ 383 kDPU_UnitSrcHScaler9 = 7U, /*!< The input source is HScaler 9. */ 384 kDPU_UnitSrcVScaler9 = 8U, /*!< The input source is VScaler 9. */ 385 kDPU_UnitSrcFilter9 = 9U, /*!< The input source is Filter 9. */ 386 kDPU_UnitSrcBlitBlend9 = 10U, /*!< The input source is BlitBlend 9. */ 387 kDPU_UnitSrcStore9 = 11U, /*!< The input source is Store 9. */ 388 kDPU_UnitSrcConstFrame0 = 12U, /*!< The input source is ConstFrame 0. */ 389 kDPU_UnitSrcConstFrame1 = 16U, /*!< The input source is ConstFrame 1. */ 390 kDPU_UnitSrcConstFrame4 = 14U, /*!< The input source is ConstFrame 4. */ 391 kDPU_UnitSrcConstFrame5 = 18U, /*!< The input source is ConstFrame 5. */ 392 kDPU_UnitSrcFetchWarp2 = 20U, /*!< The input source is FetchWarp 2. */ 393 kDPU_UnitSrcFetchEco2 = 21U, /*!< The input source is FetchEco 2. */ 394 kDPU_UnitSrcFetchDecode0 = 22U, /*!< The input source is FetchDecode 0. */ 395 kDPU_UnitSrcFetchEco0 = 23U, /*!< The input source is FetchEco 0. */ 396 kDPU_UnitSrcFetchDecode1 = 24U, /*!< The input source is FetchDecode 1. */ 397 kDPU_UnitSrcFetchEco1 = 25U, /*!< The input source is FetchEco 1. */ 398 kDPU_UnitSrcFetchLayer0 = 26U, /*!< The input source is FetchLayer 0. */ 399 kDPU_UnitSrcMatrix4 = 27U, /*!< The input source is Matrix 4. */ 400 kDPU_UnitSrcHScaler4 = 28U, /*!< The input source is HScaler 4. */ 401 kDPU_UnitSrcVScaler4 = 29U, /*!< The input source is VScaler 4. */ 402 kDPU_UnitSrcMatrix5 = 30U, /*!< The input source is Matrix 5. */ 403 kDPU_UnitSrcHScaler5 = 31U, /*!< The input source is HScaler 5. */ 404 kDPU_UnitSrcVScaler5 = 32U, /*!< The input source is VScaler 5. */ 405 kDPU_UnitSrcLayerBlend0 = 33U, /*!< The input source is LayerBlend 0. */ 406 kDPU_UnitSrcLayerBlend1 = 34U, /*!< The input source is LayerBlend 1. */ 407 kDPU_UnitSrcLayerBlend2 = 35U, /*!< The input source is LayerBlend 2. */ 408 kDPU_UnitSrcLayerBlend3 = 36U, /*!< The input source is LayerBlend 3. */ 409 }; 410 411 /*! 412 * @brief DPU pixel format. 413 * 414 * To support more pixel format, enhance this enum and the array s_dpuColorComponentFormats. 415 */ 416 typedef enum _dpu_pixel_format 417 { 418 kDPU_PixelFormatGray8 = 0, /*!< 8-bit gray. */ 419 kDPU_PixelFormatRGB565 = 1, /*!< RGB565, 16-bit per pixel. */ 420 kDPU_PixelFormatARGB8888 = 2, /*!< ARGB8888, 32-bit per pixel. */ 421 kDPU_PixelFormatRGB888 = 3, /*!< RGB888, 24-bit per pixel. */ 422 kDPU_PixelFormatARGB1555 = 4, /*!< ARGB1555, 16-bit per pixel. */ 423 } dpu_pixel_format_t; 424 425 /*! @brief Configuration structure for fetch units. */ 426 typedef struct _dpu_fetch_unit_config 427 { 428 uint32_t srcReg; /*!< This value will be set to register pixengcfg_fetchX_dynamic 429 to set the unit input source, see @ref DPU_MAKE_SRC_REG1. */ 430 uint16_t frameHeight; /*!< Frame height. */ 431 uint16_t frameWidth; /*!< Frame width. */ 432 } dpu_fetch_unit_config_t; 433 434 /*! 435 * @brief Configuration structure for the arbitrary warping re-sampling coordinates. 436 * 437 * The coordinate layer supports: 438 * 439 * - 32 bpp: 2 x s12.4 (signed fix-point) 440 * - 24 bpp: 2 x s8. 441 * - 16 bpp: 2 x s4.4 442 * - 8 bpp: 2 x s0.4 443 * - 4 bpp: 2 x s(-2).4 (means total value size = 2 bits and lowest bit = 2^-4) 444 * - 2 bpp: 2 x s(-3).4 445 * - 1 bpp: 1 x s(-3).4 (x and y alternating) 446 */ 447 typedef struct _dpu_coordinates_config 448 { 449 uint8_t bitsPerPixel; /*!< Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 32. */ 450 uint16_t strideBytes; /*!< Source buffer stride in bytes. */ 451 uint32_t baseAddr; /*!< Source buffer base address. */ 452 uint16_t frameHeight; /*!< Frame height. */ 453 uint16_t frameWidth; /*!< Frame width. */ 454 } dpu_coordinates_config_t; 455 456 /*! @brief FetchWarp unit warp coordinate mode. */ 457 typedef enum _dpu_warp_coordinate_mode 458 { 459 kDPU_WarpCoordinateModePNT = 0U, /*!< Sample points positions are read from coordinate layer. */ 460 kDPU_WarpCoordinateModeDPNT = 1U, /*!< Sample points start position and delta are read from coordinate layer. */ 461 kDPU_WarpCoordinateModeDDPNT = 2U /*!< Sample points initial value and delta increase 462 value are read from coordinate layer. */ 463 } dpu_warp_coordinate_mode_t; 464 465 /*! @brief Warp configuration structure for FetchWarp unit. */ 466 typedef struct _dpu_warp_config 467 { 468 uint32_t srcReg; /*!< This value will be set to register pixengcfg_fetchX_dynamic 469 to set the unit input source, see @ref DPU_MAKE_SRC_REG1. */ 470 uint16_t frameHeight; /*!< Frame height. */ 471 uint16_t frameWidth; /*!< Frame width. */ 472 uint8_t warpBitsPerPixel; /*!< Pixel bits of the coordinate layer. */ 473 bool enableSymmetricOffset; /*!< Enables symmetric range for negative and positive coordinate 474 values by adding an offset of +0.03125 internally to all 475 coordinate input values. Recommended for small coordinate formats 476 in DD_PNT mode. */ 477 dpu_warp_coordinate_mode_t coordMode; /*!< Coordinate layer mode. */ 478 uint32_t arbStartX; /*!< X of start point position. Signed 16.5 fix-point. Used in D_PNT and DD_PNT. */ 479 uint32_t arbStartY; /*!< Y of start point position. Signed 16.5 fix-point. Used in D_PNT and DD_PNT. */ 480 uint8_t arbDeltaYY; /*!< Y of vector between start and first sample point. Signed 3.5 fix-point. Used in DD_PNT. */ 481 uint8_t arbDeltaYX; /*!< X of vector between start and first sample point. Signed 3.5 fix-point. Used in DD_PNT. */ 482 uint8_t arbDeltaXY; /*!< Y of vector between first and second sample point. Signed 3.5 fix-point. Used in DD_PNT. */ 483 uint8_t arbDeltaXX; /*!< X of vector between first and second sample point. Signed 3.5 fix-point. Used in DD_PNT. */ 484 } dpu_warp_config_t; 485 486 /*! 487 * @brief Fetch unit source buffer configuration structure. 488 * 489 * Base address and stride alignment restrictions: 490 * 32 bpp: Base address and stride must be a multiple of 4 bytes. 491 * 16 bpp: Base address and stride must be a multiple of 2 bytes. 492 * others: any byte alignment allowed 493 * 494 * Generally, the @ref bitsPerPixel and @ref pixelFormat specify the pixel format 495 * in frame buffer, they should match. But when the color palette is used, the 496 * @ref bitsPerPixel specify the format in framebuffer, the @ref pixelFormat 497 * specify the format in color palette entry. 498 */ 499 typedef struct _dpu_src_buffer_config 500 { 501 uint32_t baseAddr; /*!< Source buffer base address, see alignment restrictions. */ 502 uint16_t strideBytes; /*!< Source buffer stride in bytes, see alignment restrictions. */ 503 uint8_t bitsPerPixel; /*!< Bits per pixel in frame buffer. */ 504 dpu_pixel_format_t pixelFormat; /*!< Pixel format. */ 505 uint16_t bufferHeight; /*!< Buffer height. */ 506 uint16_t bufferWidth; /*!< Buffer width. */ 507 uint32_t constColor; /*!< Const color shown in the region out of frame buffer, see @ref DPU_MAKE_CONST_COLOR. */ 508 } dpu_src_buffer_config_t; 509 510 /*! @brief Fetch unit clip window configuration structure. */ 511 typedef struct _dpu_clip_window_config 512 { 513 uint16_t windowOffsetX; /*!< Horizontal offset of the clip window. */ 514 uint16_t windowOffsetY; /*!< Vertical offset of the clip window. */ 515 uint16_t windowHeight; /*!< Height of the clip window. */ 516 uint16_t windowWidth; /*!< Width of the clip window. */ 517 } dpu_clip_window_config_t; 518 519 /*! @brief Define the color to take for pixels that do not lie inside the clip window of any layer */ 520 typedef enum _dpu_clip_color_mode 521 { 522 kDPU_ClipColorNull, /*!< Use null color. */ 523 kDPU_ClipColorSublayer, /*!< Use color of sublayer. */ 524 } dpu_clip_color_mode_t; 525 /*! 526 * @brief Store unit Destination buffer configuration structure. 527 * 528 * Base address and stride alignment restrictions: 529 * 32 bpp: Base address and stride must be a multiple of 4 bytes. 530 * 16 bpp: Base address and stride must be a multiple of 2 bytes. 531 * others: any byte alignment allowed 532 */ 533 typedef struct _dpu_dst_buffer_config 534 { 535 uint32_t baseAddr; /*!< Destination buffer base address, see alignment restrictions. */ 536 uint16_t strideBytes; /*!< Destination buffer stride in bytes, see alignment restrictions. */ 537 uint8_t bitsPerPixel; /*!< Bits per pixel. */ 538 dpu_pixel_format_t pixelFormat; /*!< Pixel format. */ 539 uint16_t bufferHeight; /*!< Buffer height. */ 540 uint16_t bufferWidth; /*!< Buffer width. */ 541 } dpu_dst_buffer_config_t; 542 543 /*! @brief LayerBlend unit AlphaMask mode. */ 544 typedef enum _dpu_alpha_mask_mode 545 { 546 kDPU_AlphaMaskPrim, /*!< Areas with primary input alpha > 128 mapped to alpha 255, the rest mapped to 0. */ 547 kDPU_AlphaMaskSec, /*!< Areas with secondary input alpha > 128 mapped to alpha 255, the rest mapped to 0. */ 548 kDPU_AlphaMaskPrimOrSec, /*!< Primary and secondary OR'ed together. */ 549 kDPU_AlphaMaskPrimAndSec, /*!< Primary and secondary AND'ed together. */ 550 kDPU_AlphaMaskPrimInv, /*!< Primary input alpha inverted. */ 551 kDPU_AlphaMaskSecInv, /*!< Secondary input alpha inverted. */ 552 kDPU_AlphaMaskPrimOrSecInv, /*!< Primary and inverted secondary OR'ed together. */ 553 kDPU_AlphaMaskPrimAndSecInv /*!< Primary and inverted secondary AND'ed together. */ 554 } dpu_alpha_mask_mode_t; 555 556 /*! @brief LayerBlend unit alpha blend mode. */ 557 typedef enum _dpu_blend_mode 558 { 559 kDPU_BlendZero, /*!< OUT = IN * 0. */ 560 kDPU_BlendOne, /*!< OUT = IN * 1. */ 561 kDPU_BlendPrimAlpha, /*!< OUT = IN * ALPHA_primary. */ 562 kDPU_BlendPrimAlphaInv, /*!< OUT = IN * (1 - ALPHA_primary). */ 563 kDPU_BlendSecAlpha, /*!< OUT = IN * ALPHA_secondary. */ 564 kDPU_BlendSecAlphaInv, /*!< OUT = IN * (1 - ALPHA_secondary). */ 565 kDPU_BlendConstAlpha, /*!< OUT = IN * ALPHA_const. */ 566 kDPU_BlendConstAlphaInv, /*!< OUT = IN * (1 - ALPHA_const). */ 567 } dpu_blend_mode_t; 568 569 /*! @brief LayerBlend unit configuration structure. */ 570 typedef struct _dpu_layer_blend_config 571 { 572 uint8_t constAlpha; /*!< The const alpha value used in blend. */ 573 dpu_blend_mode_t secAlphaBlendMode; /*!< Secondary (overlay) input alpha blending function. */ 574 dpu_blend_mode_t primAlphaBlendMode; /*!< Primary (background) input alpha blending function. */ 575 dpu_blend_mode_t secColorBlendMode; /*!< Secondary (overlay) input color blending function. */ 576 dpu_blend_mode_t primColorBlendMode; /*!< Primary (background) input color blending function. */ 577 578 uint32_t srcReg; /*!< This value will be set to pixengcfg_layerblendX_dynamic 579 to set the unit input source, see @ref DPU_MAKE_SRC_REG2. */ 580 bool enableAlphaMask; /*!< Enable AlphaMask feature. */ 581 dpu_alpha_mask_mode_t alphaMaskMode; /*!< AlphaMask mode, only valid when enableAlphaMask is true. */ 582 } dpu_layer_blend_config_t; 583 584 /*! @brief BlitBlend blend function. */ 585 typedef enum _dpu_blit_blend_func 586 { 587 kDPU_BlitBlendFuncGlZero = 0, /*!< GL_ZERO. */ 588 kDPU_BlitBlendFuncGlOne = 1, /*!< GL_ONE. */ 589 kDPU_BlitBlendFuncGlSrcColor = 0x0300, /*!< GL_SRC_COLOR */ 590 kDPU_BlitBlendFuncGlOneMinusSrcColor = 0x0301, /*!< GL_ONE_MINUS_SRC_COLOR */ 591 kDPU_BlitBlendFuncGlSrcAlpha = 0x0302, /*!< GL_SRC_ALPHA */ 592 kDPU_BlitBlendFuncGlOneMinusSrcAlpha = 0x0303, /*!< GL_ONE_MINUS_SRC_ALPHA */ 593 kDPU_BlitBlendFuncGlDstAlpha = 0x0304, /*!< GL_DST_ALPHA */ 594 kDPU_BlitBlendFuncGlOneMinusDstAlpha = 0x0305, /*!< GL_ONE_MINUS_DST_ALPHA */ 595 kDPU_BlitBlendFuncGlDstColor = 0x0306, /*!< GL_DST_COLOR */ 596 kDPU_BlitBlendFuncGlOneMinusDstColor = 0x0307, /*!< GL_ONE_MINUS_DST_COLOR */ 597 kDPU_BlitBlendFuncGlSrcAlphaSaturate = 0x0308, /*!< GL_SRC_ALPHA_SATURATE */ 598 kDPU_BlitBlendFuncGlConstColor = 0x8001, /*!< GL_CONSTANT_COLOR */ 599 kDPU_BlitBlendFuncGlOneMinusConstColor = 0x8002, /*!< GL_ONE_MINUS_CONSTANT_COLOR */ 600 kDPU_BlitBlendFuncGlConstAlpha = 0x8003, /*!< GL_CONSTANT_ALPHA */ 601 kDPU_BlitBlendFuncGlOneMinusConstAlpha = 0x8004, /*!< GL_ONE_MINUS_CONSTANT_ALPHA */ 602 } dpu_blit_blend_func_t; 603 604 /*! @brief BlitBlend blend mode. */ 605 typedef enum _dpu_blit_blend_mode 606 { 607 kDPU_BlitBlendModeGlFuncAdd = 0x8006, /*!< GL_FUNC_ADD */ 608 kDPU_BlitBlendModeGlMin = 0x8007, /*!< GL_MIN */ 609 kDPU_BlitBlendModeGlMax = 0x8008, /*!< GL_MAX */ 610 kDPU_BlitBlendModeGlFuncSubtract = 0x800A, /*!< GL_FUNC_SUBTRACT */ 611 kDPU_BlitBlendModeGlFuncReverseSubtract = 0x800B, /*!< GL_FUNC_REVERSE_SUBTRACT */ 612 kDPU_BlitBlendModeVgBlendSrc = 0x2000, /*!< VG_BLEND_SRC */ 613 kDPU_BlitBlendModeVgBlendSrcOver = 0x2001, /*!< VG_BLEND_SRC_OVER */ 614 kDPU_BlitBlendModeVgBlendDstOver = 0x2002, /*!< VG_BLEND_DST_OVER */ 615 kDPU_BlitBlendModeVgBlendSrcIn = 0x2003, /*!< VG_BLEND_SRC_IN */ 616 kDPU_BlitBlendModeVgBlendDstIn = 0x2004, /*!< VG_BLEND_DST_IN */ 617 kDPU_BlitBlendModeVgBlendMultiply = 0x2005, /*!< VG_BLEND_MULTIPLY */ 618 kDPU_BlitBlendModeVgBlendScreen = 0x2006, /*!< VG_BLEND_SCREEN */ 619 kDPU_BlitBlendModeVgBlendDarken = 0x2007, /*!< VG_BLEND_DARKEN */ 620 kDPU_BlitBlendModeVgBlendLighten = 0x2008, /*!< VG_BLEND_LIGHTEN */ 621 kDPU_BlitBlendModeVgBlendAdditive = 0x2009, /*!< VG_BLEND_ADDITIVE */ 622 } dpu_blit_blend_mode_t; 623 624 /*! @brief BlitBlend neutral border mode. */ 625 typedef enum _dpu_blit_blend_neutral_border_mode 626 { 627 kDPU_BlitBlendNeutralBorderPrim = 0, /*!< Bypasses primary pixel. */ 628 kDPU_BlitBlendNeutralBorderSec = 0, /*!< Bypasses secondary pixel. */ 629 } dpu_blit_blend_neutral_border_mode_t; 630 631 /*! @brief BlitBlend unit configuration structure. */ 632 typedef struct _dpu_blit_blend_config 633 { 634 uint8_t neutralBorderRightPixels; /*!< Number of neutral right border pixels. */ 635 uint8_t neutralBorderLeftPixels; /*!< Number of neutral left border pixels. */ 636 dpu_blit_blend_neutral_border_mode_t neutralBorderMode; /*!< Neutral border mode. */ 637 uint32_t constColor; /*!< Const color used for blit blend, see @ref DPU_MAKE_CONST_COLOR. */ 638 639 dpu_blit_blend_func_t redBlendFuncSrc; /*!< Red component source blend function */ 640 dpu_blit_blend_func_t redBlendFuncDst; /*!< Red component destination blend function */ 641 dpu_blit_blend_func_t greenBlendFuncSrc; /*!< Green component source blend function */ 642 dpu_blit_blend_func_t greenBlendFuncDst; /*!< Green component destination blend function */ 643 dpu_blit_blend_func_t blueBlendFuncSrc; /*!< Blue component source blend function */ 644 dpu_blit_blend_func_t blueBlendFuncDst; /*!< Blue component destination blend function */ 645 dpu_blit_blend_func_t alphaBlendFuncSrc; /*!< Alpha component source blend function */ 646 dpu_blit_blend_func_t alphaBlendFuncDst; /*!< Alpha component destination blend function */ 647 dpu_blit_blend_mode_t redBlendMode; /*!< Red component blend mode */ 648 dpu_blit_blend_mode_t greenBlendMode; /*!< Green component blend mode */ 649 dpu_blit_blend_mode_t blueBlendMode; /*!< Blue component blend mode */ 650 dpu_blit_blend_mode_t alphaBlendMode; /*!< Alpha component blend mode */ 651 } dpu_blit_blend_config_t; 652 653 /*! @brief ROp unit control flags. */ 654 enum _dpu_rop_flags 655 { 656 kDPU_RopAddRed = 657 DPU_ROP_CONTROL_RedMode_MASK, /*!< Set to add the red component, otherwise raster with operation index. */ 658 kDPU_RopAddGreen = 659 DPU_ROP_CONTROL_GreenMode_MASK, /*!< Set to add the green component, otherwise raster with operation index. */ 660 kDPU_RopAddBlue = 661 DPU_ROP_CONTROL_BlueMode_MASK, /*!< Set to add the blue component, otherwise raster with operation index. */ 662 kDPU_RopAddAlpha = 663 DPU_ROP_CONTROL_AlphaMode_MASK, /*!< Set to add the alpha component, otherwise raster with operation index. */ 664 kDPU_RopTertDiv2 = DPU_ROP_CONTROL_TertDiv2_MASK, /*!< In add mode, set this to divide tertiary port input by 2. */ 665 kDPU_RopSecDiv2 = DPU_ROP_CONTROL_SecDiv2_MASK, /*!< In add mode, set this to divide secondary port input by 2. */ 666 kDPU_RopPrimDiv2 = DPU_ROP_CONTROL_PrimDiv2_MASK, /*!< In add mode, set this to divide primary port input by 2. */ 667 }; 668 669 /*! @brief ROp unit configuration structure. */ 670 typedef struct _dpu_rop_config 671 { 672 uint32_t controlFlags; /*!< Control flags, see @ref _dpu_rop_flags. */ 673 uint8_t alphaIndex; /*!< Alpha operation index. */ 674 uint8_t blueIndex; /*!< Blue operation index. */ 675 uint8_t greenIndex; /*!< Green operation index. */ 676 uint8_t redIndex; /*!< Red operation index. */ 677 } dpu_rop_config_t; 678 679 /*! @brief ConstFrame unit configuration structure. */ 680 typedef struct _dpu_const_frame_config 681 { 682 uint16_t frameHeight; /*!< Frame height. */ 683 uint16_t frameWidth; /*!< Frame width. */ 684 uint32_t constColor; /*!< See @ref DPU_MAKE_CONST_COLOR. */ 685 } dpu_const_frame_config_t; 686 687 /*! @brief Display timing configuration flags. */ 688 enum _dpu_display_timing_flags 689 { 690 kDPU_DisplayPixelActiveHigh = 0, /*!< Pixel data active high. */ 691 kDPU_DisplayPixelActiveLow = DPU_DISENGCONF_POLARITYCTRL_PixInv_MASK, /*!< Pixel data active low. */ 692 kDPU_DisplayDataEnableActiveHigh = 693 DPU_DISENGCONF_POLARITYCTRL_PolEn_MASK, /*!< Set to make data enable high active. */ 694 kDPU_DisplayDataEnableActiveLow = 0, /*!< Set to make data enable high low. */ 695 kDPU_DisplayHsyncActiveHigh = DPU_DISENGCONF_POLARITYCTRL_PolHs_MASK, /*!< Set to make HSYNC high active. */ 696 kDPU_DisplayHsyncActiveLow = 0, /*!< Set to make HSYNC low active. */ 697 kDPU_DisplayVsyncActiveHigh = DPU_DISENGCONF_POLARITYCTRL_PolVs_MASK, /*!< Set to make VSYNC high active. */ 698 kDPU_DisplayVsyncActiveLow = 0, /*!< Set to make VSYNC low active. */ 699 }; 700 701 /*! @brief Display timing configuration structure. */ 702 typedef struct _dpu_display_timing_config 703 { 704 uint16_t flags; /*!< OR'ed value of @ref _dpu_display_timing_flags. */ 705 uint16_t width; /*!< Active width. */ 706 uint16_t hsw; /*!< HSYNC pulse width. */ 707 uint16_t hfp; /*!< Horizontal front porch. */ 708 uint16_t hbp; /*!< Horizontal back porch. */ 709 uint16_t height; /*!< Active height. */ 710 uint16_t vsw; /*!< VSYNC pulse width. */ 711 uint16_t vfp; /*!< Vrtical front porch. */ 712 uint16_t vbp; /*!< Vertical back porch. */ 713 } dpu_display_timing_config_t; 714 715 /*! @brief Display mode, safety stream is the primary input, content stream is the secondary input. */ 716 typedef enum _dpu_display_mode 717 { 718 kDPU_DisplayBlackBackground, /*!< Black background is shown. */ 719 kDPU_DisplayConstBackground, /*!< Const color background is shown. */ 720 kDPU_DisplayOnlyPrim, /*!< Only primary input is shown. */ 721 kDPU_DisplayOnlySec, /*!< Only secondary input is shown. */ 722 kDPU_DisplayPrimOnTop, /*!< Both inputs overlaid with primary on top. */ 723 kDPU_DisplaySecOnTop, /*!< Both inputs overlaid with secondary on top. */ 724 kDPU_DisplayTest /*!< White background with test pattern shown. */ 725 } dpu_display_mode_t; 726 727 /*! @brief Display mode configuration structure. */ 728 typedef struct _dpu_display_config 729 { 730 bool enablePrimAlpha; /*!< Enable primary input alpha for screen composition. */ 731 bool enableSecAlpha; /*!< Enable secondary input alpha for screen composition. */ 732 dpu_display_mode_t displayMode; /*!< Display mode. */ 733 bool enablePrimAlphaInPanic; /*!< Enable primary input alpha for screen composition in panic mode. */ 734 bool enableSecAlphaInPanic; /*!< Enable secondary input alpha for screen composition in panic mode. */ 735 dpu_display_mode_t displayModeInPanic; /*!< Display mode in panic mode. */ 736 uint16_t constRed; /*!< Const red value, 10-bit. */ 737 uint16_t constGreen; /*!< Const green value, 10-bit. */ 738 uint16_t constBlue; /*!< Const green value, 10-bit. */ 739 uint8_t constAlpha; /*!< Const alpha value, 1-bit. */ 740 uint16_t primAreaStartX; /*!< Primary screen upper left corner, x component. 14-bit , start from 1. */ 741 uint16_t primAreaStartY; /*!< Primary screen upper left corner, y component. 14-bit, start from 1. */ 742 uint16_t secAreaStartX; /*!< Secondary screen upper left corner, x component. 14-bit, start from 1. */ 743 uint16_t secAreaStartY; /*!< Secondary screen upper left corner, y component. 14-bit, start from 1. */ 744 } dpu_display_config_t; 745 746 /*! @brief VScaler and HScaler configuration structure. */ 747 typedef struct _dpu_scaler_config 748 { 749 uint32_t srcReg; /*!< This value will be set to register pixengcfg_slacer_dynamic 750 to set the unit input source, see @ref DPU_MAKE_SRC_REG1. 751 When down-scaling horizontally, the path should be -> HScaler -> VScaler ->, 752 When up-scaling horizontally, the path should be -> VScaler -> HScaler ->. */ 753 uint16_t inputSize; /*!< For HScaler, it is frame width, for VScaler, it is frame height. */ 754 uint16_t outputSize; /*!< For HScaler, it is frame width, for VScaler, it is frame height. */ 755 756 } dpu_scaler_config_t; 757 758 /*! @brief Signature unit static configuration. */ 759 typedef struct _dpu_signature_config 760 { 761 uint8_t errorThreshold; /*!< Number of frames with signature violation before signature error is set for an 762 evaluation window. */ 763 uint8_t errorResetThreshold; /*!< Number of consecutive frames without signature violation before signature error is 764 reset for an 765 evaluation window. */ 766 uint8_t panicRed; /*!< Constant color shown in the window when local panic happens. */ 767 uint8_t panicGreen; /*!< Constant color shown in the window when local panic happens. */ 768 uint8_t panicBlue; /*!< Constant color shown in the window when local panic happens. */ 769 uint8_t panicAlpha; /*!< Constant color shown in the window when local panic happens. Must be 0 or 1 */ 770 } dpu_signature_config_t; 771 772 /*! @brief Signature unit evaluation window control flags. */ 773 enum _dpu_signature_window_flags 774 { 775 kDPU_SignatureWindowEnableGlobalPanic = DPU_SIG_EVALCONTROL_EnGlobalPanic_MASK, 776 /*!< When enabled the window error will activate display stream the panic mode. */ 777 kDPU_SignatureWindowEnableLocalPanic = DPU_SIG_EVALCONTROL_EnLocalPanic_MASK, 778 /*!< When enabled the window error will replace pixels in window to the const panic color. */ 779 kDPU_SignatureWindowEnableAlphaMask = DPU_SIG_EVALCONTROL_AlphaMask_MASK, 780 /*!< When enabled pixels with alpha bit = 0 are ignored for signature computation. */ 781 kDPU_SignatureWindowInvertAlpha = DPU_SIG_EVALCONTROL_AlphaInv_MASK, 782 /*!< When enabled pixels with alpha bit = 1 are ignored for signature computation. */ 783 kDPU_SignatureWindowDontSkipWindow = DPU_SIG_EVALCONTROL_EnCRC_MASK, 784 }; 785 786 /*! @brief Signature unit evaluation window configuration. */ 787 typedef struct _dpu_signature_window_config 788 { 789 uint32_t controlFlags; /*!< Control flags, OR'ed valud of @ref _dpu_signature_window_flags. */ 790 uint16_t upperLeftX; /*!< X coordinate of the upper left corner. */ 791 uint16_t upperLeftY; /*!< Y coordinate of the upper left corner. */ 792 uint16_t lowerRightX; /*!< X coordinate of the lower right corner. */ 793 uint16_t lowerRightY; /*!< Y coordinate of the lower right corner. */ 794 } dpu_signature_window_config_t; 795 796 /*! @brief Signature unit status. */ 797 enum _dpu_signature_status 798 { 799 kDPU_SignatureIdle = DPU_SIG_STATUS_StsSigIdle_MASK, /*!< Signature unit is in idle status. */ 800 kDPU_SignatureValid = DPU_SIG_STATUS_StsSigValid_MASK, /*!< Signature unit is in idle status. */ 801 }; 802 803 /******************************************************************************* 804 * API 805 ******************************************************************************/ 806 807 #if defined(__cplusplus) 808 extern "C" { 809 #endif /* __cplusplus */ 810 811 /*! 812 * @name DPU Initialization and de-initialization 813 * @{ 814 */ 815 816 /*! 817 * @brief Initializes the DPU peripheral. 818 * 819 * This function ungates the DPU clock. 820 * 821 * @param base DPU peripheral base address. 822 * 823 */ 824 void DPU_Init(IRIS_MVPL_Type *base); 825 826 /*! 827 * @brief Deinitializes the DPU peripheral. 828 * 829 * This function gates the DPU clock. 830 * 831 * @param base DPU peripheral base address. 832 */ 833 void DPU_Deinit(IRIS_MVPL_Type *base); 834 835 /*! 836 * @brief Prepare the unit path configuration. 837 * 838 * The DPU has a default path configuration. Before changing the configuration, 839 * this function could be used to break all the original path. This make sure 840 * one pixel engine unit is not used in multiple pipelines. 841 * 842 * @param base DPU peripheral base address. 843 */ 844 void DPU_PreparePathConfig(IRIS_MVPL_Type *base); 845 846 /* @} */ 847 848 /*! 849 * @name DPU interrupts 850 * @{ 851 */ 852 853 /*! 854 * @brief Enable the selected DPU interrupts. 855 * 856 * For example, to enable Store9 shadow load interrupt and Store9 frame complete 857 * interrupt, use like this: 858 * 859 * @code 860 DPU_EnableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt | 861 kDPU_Group0Store9FrameCompleteInterrupt); 862 @endcode 863 * 864 * @param base DPU peripheral base address. 865 * @param group Interrupt group index. 866 * @param mask The interrupts to enable, this is a logical OR of members in 867 * @ref _dpu_interrupt. 868 * @note Only the members in the same group could be OR'ed, at the same time, 869 * the parameter @p group should be passed in correctly. 870 */ 871 void DPU_EnableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 872 873 /*! 874 * @brief Disable the selected DPU interrupts. 875 * 876 * For example, to disable Store9 shadow load interrupt and Store9 frame complete 877 * interrupt, use like this: 878 * 879 * @code 880 DPU_DisableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt | 881 kDPU_Group0Store9FrameCompleteInterrupt); 882 @endcode 883 * 884 * @param base DPU peripheral base address. 885 * @param group Interrupt group index. 886 * @param mask The interrupts to disable, this is a logical OR of members in 887 * @ref _dpu_interrupt. 888 * @note Only the members in the same group could be OR'ed, at the same time, 889 * the parameter @p group should be passed in correctly. 890 */ 891 void DPU_DisableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 892 893 /*! 894 * @brief Get the DPU interrupts pending status. 895 * 896 * The pending status are returned as mask. For example, to check the Store9 897 * shadow load interrupt and Store9 frame complete interrupt pending status, 898 * use like this. 899 * 900 * @code 901 uint32_t pendingStatus = DPU_GetInterruptsPendingFlags(DPU, 0); 902 if (pendingStatus & kDPU_Group0Store9ShadowLoadInterrupt) 903 { 904 Store9 shadow load interrupt occurs, handle it. 905 } 906 if (pendingStatus & kDPU_Group0Store9FrameCompleteInterrupt) 907 { 908 Store9 frame complete interrupt occurs, handle it. 909 } 910 @endcode 911 * 912 * @param base DPU peripheral base address. 913 * @param group Interrupt group index. 914 * @return The interrupts pending status mask value, see @ref _dpu_interrupt. 915 */ 916 uint32_t DPU_GetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group); 917 918 /*! 919 * @brief Clear the specified DPU interrupts pending status. 920 * 921 * For example, to disable Store9 shadow load interrupt and Store9 frame complete 922 * interrupt pending status, use like this: 923 * 924 * @code 925 DPU_ClearInterruptsPendingFlags(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt | 926 kDPU_Group0Store9FrameCompleteInterrupt); 927 @endcode 928 * 929 * @param base DPU peripheral base address. 930 * @param group Interrupt group index. 931 * @param mask The interrupt pending flags to clear, this is a logical OR of members in 932 * @ref _dpu_interrupt. 933 * @note Only the members in the same group could be OR'ed, at the same time, 934 * the parameter @p group should be passed in correctly. 935 */ 936 void DPU_ClearInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 937 938 /*! 939 * @brief Set the specified DPU interrupts pending status. 940 * 941 * This function sets the interrupts pending flags, this is a method to trigger 942 * interrupts by software. 943 * 944 * @param base DPU peripheral base address. 945 * @param group Interrupt group index. 946 * @param mask The interrupt pending flags to set, this is a logical OR of members in 947 * @ref _dpu_interrupt. 948 * @note Only the members in the same group could be OR'ed, at the same time, 949 * the parameter @p group should be passed in correctly. 950 */ 951 void DPU_SetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 952 953 /*! 954 * @brief Mask the selected DPU user interrupts. 955 * 956 * The only difference between DPU user interrupt and normal interrupt is user 957 * interrupts could be masked by @ref DPU_MaskUserInterrupts. All other APIs 958 * useage are the same. 959 * 960 * @param base DPU peripheral base address. 961 * @param group Interrupt group index. 962 * @param mask The interrupts to mask, this is a logical OR of members in 963 * @ref _dpu_interrupt. 964 */ 965 void DPU_MaskUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 966 967 /*! 968 * @brief Enable the selected DPU user interrupts. 969 * 970 * The only difference between DPU user interrupt and normal interrupt is user 971 * interrupts could be masked by @ref DPU_MaskUserInterrupts. 972 * 973 * @param base DPU peripheral base address. 974 * @param group Interrupt group index. 975 * @param mask The interrupts to enable, this is a logical OR of members in 976 * @ref _dpu_interrupt. 977 */ 978 void DPU_EnableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 979 980 /*! 981 * @brief Disable the selected DPU user interrupts. 982 * 983 * The only difference between DPU user interrupt and normal interrupt is user 984 * interrupts could be masked by @ref DPU_MaskUserInterrupts. 985 * 986 * @param base DPU peripheral base address. 987 * @param group Interrupt group index. 988 * @param mask The interrupts to disable, this is a logical OR of members in 989 * @ref _dpu_interrupt. 990 */ 991 void DPU_DisableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 992 993 /*! 994 * @brief Get the DPU user interrupts pending status. 995 * 996 * The only difference between DPU user interrupt and normal interrupt is user 997 * interrupts could be masked by @ref DPU_MaskUserInterrupts. 998 * 999 * @param base DPU peripheral base address. 1000 * @param group Interrupt group index. 1001 * @return The interrupts pending status mask value, see @ref _dpu_interrupt. 1002 */ 1003 uint32_t DPU_GetUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group); 1004 1005 /*! 1006 * @brief Clear the specified DPU user interrupts pending status. 1007 * 1008 * The only difference between DPU user interrupt and normal interrupt is user 1009 * interrupts could be masked by @ref DPU_MaskUserInterrupts. 1010 * 1011 * @param base DPU peripheral base address. 1012 * @param group Interrupt group index. 1013 * @param mask The interrupt pending flags to clear, this is a logical OR of members in 1014 * @ref _dpu_interrupt. 1015 */ 1016 void DPU_ClearUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 1017 1018 /*! 1019 * @brief Set the specified DPU user interrupts pending status. 1020 * 1021 * The only difference between DPU user interrupt and normal interrupt is user 1022 * interrupts could be masked by @ref DPU_MaskUserInterrupts. 1023 * 1024 * @param base DPU peripheral base address. 1025 * @param group Interrupt group index. 1026 * @param mask The interrupt pending flags to set, this is a logical OR of members in 1027 * @ref _dpu_interrupt. 1028 */ 1029 void DPU_SetUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask); 1030 1031 /* @} */ 1032 1033 /*! 1034 * @name Shadow load related. 1035 * @{ 1036 */ 1037 1038 /*! 1039 * @brief Enable or disable the register shadowing for the DPU process units. 1040 * 1041 * For example, to enable the shadowing of all RWS registers of the pipeline with endpoint Store9. 1042 * @code 1043 DPU_EnableShadowLoad(DPU, kDPU_PipelineStore9, true); 1044 @endcode 1045 * 1046 * @param base DPU peripheral base address. 1047 * @param unit The unit whose shadow load to enable or disable, see @ref dpu_unit_t. 1048 * @param enable True to enable, false to disable. 1049 * @retval kStatus_Success The shadow load is enabled or disabled successfully. 1050 * @retval kStatus_InvalidArgument The unit does not support shadow load. 1051 */ 1052 status_t DPU_EnableShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable); 1053 /* @} */ 1054 1055 /*! 1056 * @name Pipline. 1057 * @{ 1058 */ 1059 1060 /*! 1061 * @brief Initialize the pipeline. 1062 * 1063 * @param base DPU peripheral base address. 1064 * @param unit The DPU pipeline unit. 1065 */ 1066 void DPU_InitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit); 1067 1068 /*! 1069 * @brief Deinitializes the pipeline. 1070 * 1071 * Power down the pipeline and disable the shadow load feature. 1072 * 1073 * @param base DPU peripheral base address. 1074 * @param unit The DPU pipeline unit. 1075 */ 1076 void DPU_DeinitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit); 1077 1078 /*! 1079 * @brief Trigger the pipeline shadow load. 1080 * 1081 * This function triggers the pipeline reconfiguration. 1082 * 1083 * @param base DPU peripheral base address. 1084 * @param unit The DPU pipeline unit. 1085 */ 1086 void DPU_TriggerPipelineShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit); 1087 1088 /*! 1089 * @brief Trigger the pipeline. 1090 * 1091 * This function triggers the pipeline sequence complete interrupt. After 1092 * triggered, this interrupt occurs when the pipeline is empty and no more 1093 * operations are pending. It will occur immediately, when this is the case 1094 * already during activation of the trigger. Generally this is used for the 1095 * blit operation, to make sure all operations finished. 1096 * 1097 * @param base DPU peripheral base address. 1098 * @param unit The DPU pipeline unit. 1099 */ 1100 void DPU_TriggerPipelineCompleteInterrupt(IRIS_MVPL_Type *base, dpu_unit_t unit); 1101 1102 /*! 1103 * @brief Set the DPU unit input source selection. 1104 * 1105 * Sets the DPU unit input source, the input source is controlled by the 1106 * register \<unit\>_dynamic in "Pixel Engin Top Level". This function writes 1107 * the register \<unit\>_dynamic directly, please check the reference manual 1108 * for the register details. This function only changes the input source 1109 * control bits in register. 1110 * 1111 * @param base DPU peripheral base address. 1112 * @param unit The DPU pipeline unit. 1113 * @param srcReg The value written to register \<unit\>_dynamic. Could be 1114 * generated using @ref DPU_MAKE_SRC_REG1, @ref DPU_MAKE_SRC_REG2, 1115 * and @ref DPU_MAKE_SRC_REG3. 1116 */ 1117 void DPU_SetUnitSrc(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1118 1119 /*! @} */ 1120 1121 /*! 1122 * @name Fetch Units 1123 * 1124 * The Fetch unit input frame buffer is used like this: 1125 * 1126 * @verbatim 1127 1128 <----------------- frameWidth --------------------> 1129 ^ +-------------------------------------------------+ 1130 | | ^ ^ Frame | 1131 | | | | | 1132 | | | offsetY | Clip window offsetY| 1133 | | v | | 1134 | |<------->+------------------|------+----+ | 1135 frameHeight | | offsetX | Source Buffer | | | | 1136 | | | v | | | 1137 | | | +----------------------+ | 1138 | | | |Clip Window | | 1139 | | Clip window offsetX | | | 1140 | |<-------------------->| | | 1141 | | | | | | 1142 | | | +----------------------+ | 1143 | | | | | | 1144 | | +-------------------------+----+ | 1145 | | | 1146 | | | 1147 v +-------------------------------------------------+ 1148 @endverbatim 1149 * @{ 1150 */ 1151 1152 /*! 1153 * @brief Get the default configuration for fetch unit. 1154 * 1155 * The default value is: 1156 * @code 1157 config->srcReg = 0U; 1158 config->frameHeight = 320U; 1159 config->frameWidth = 480U; 1160 @endcode 1161 * 1162 * @param config Pointer to the configuration structure. 1163 */ 1164 void DPU_FetchUnitGetDefaultConfig(dpu_fetch_unit_config_t *config); 1165 1166 /*! 1167 * @brief Initialize the fetch unit. 1168 * 1169 * This function initializes the fetch unit for the basic use, for other use 1170 * case such as arbitrary warping, use the functions @ref DPU_InitFetchUnitWarp 1171 * and @ref DPU_InitWarpCoordinates. 1172 * 1173 * The input source of fetch unit could be: 1174 * - @ref kDPU_UnitSrcNone 1175 * - @ref kDPU_UnitSrcFetchWarp9 1176 * - @ref kDPU_UnitSrcFetchEco2 1177 * - @ref kDPU_UnitSrcFetchEco9 1178 * - @ref kDPU_UnitSrcFetchEco0 1179 * - @ref kDPU_UnitSrcFetchEco1 1180 * 1181 * @param base DPU peripheral base address. 1182 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1183 * @param config Pointer to the configuration structure. 1184 */ 1185 void DPU_InitFetchUnit(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_fetch_unit_config_t *config); 1186 1187 /*! 1188 * @brief Set the color palette index width for fetch unit. 1189 * 1190 * The palette index width could be 1 to 8. Note the difference between palette 1191 * index width and the pixel width in framebuffer. 1192 * 1193 * @param base DPU peripheral base address. 1194 * @param unit DPU unit, see @ref dpu_unit_t, must be FetchDecode or FetchLayer here. 1195 * @param indexWidth The palette index width. 1196 * @retval kStatus_Success Initialization success. 1197 * @retval kStatus_InvalidArgument Wrong argument. 1198 */ 1199 status_t DPU_SetColorPaletteIndexWidth(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t indexWidth); 1200 1201 /*! 1202 * @brief Updates the color palette for fetch unit. 1203 * 1204 * This function updates the fetch unit color palette, the palette values specified 1205 * by @p palette are loaded to fetch unit from @p startIndex. The load count is 1206 * specified by @p count. 1207 * 1208 * @param base DPU peripheral base address. 1209 * @param unit DPU unit, see @ref dpu_unit_t, must be FetchDecode or FetchLayer here. 1210 * @param startIndex The start index of the fetch unit palette to update. 1211 * @param palette Pointer to the palette. 1212 * @param count Count of @p palette. 1213 * @retval kStatus_Success Initialization success. 1214 * @retval kStatus_InvalidArgument Wrong argument. 1215 */ 1216 status_t DPU_UpdateColorPalette( 1217 IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t startIndex, const uint32_t *palette, uint32_t count); 1218 1219 /*! 1220 * @brief Enable or disable color palette for some sublayer. 1221 * 1222 * @param base DPU peripheral base address. 1223 * @param unit DPU unit, see @ref dpu_unit_t, must be FetchDecode or FetchLayer here. 1224 * @param sublayer Sublayer index, should be 0 to 7. 1225 * @param enable True to enable, false to disable. 1226 */ 1227 void DPU_EnableColorPalette(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable); 1228 1229 /*! 1230 * @brief Get the default configuration structure for arbitrary warping re-sampling coordinates. 1231 * 1232 * The default value is: 1233 * @code 1234 config->bitsPerPixel = 0U; 1235 config->strideBytes = 0x500U; 1236 config->baseAddr = 0U; 1237 config->frameHeight = 320U; 1238 config->frameWidth = 480U; 1239 @endcode 1240 * 1241 * @param config Pointer to the configuration structure. 1242 */ 1243 void DPU_CorrdinatesGetDefaultConfig(dpu_coordinates_config_t *config); 1244 1245 /*! 1246 * @brief Initialize the arbitrary warping coordinates. 1247 * 1248 * This function initializes the FetchEco unit, so that it could 1249 * be used as the arbitrary warping coordinates. 1250 * 1251 * @param base DPU peripheral base address. 1252 * @param unit DPU unit, see @ref dpu_unit_t, must be FetchEco here. 1253 * @param config Pointer to the configuration structure. 1254 * @retval kStatus_Success Initialization success. 1255 * @retval kStatus_InvalidArgument Wrong argument. 1256 */ 1257 status_t DPU_InitWarpCoordinates(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_coordinates_config_t *config); 1258 1259 /*! 1260 * @brief Get the default warp configuration for FetchWarp unit. 1261 * 1262 * The default value is: 1263 * @code 1264 config->srcReg = 0U; 1265 config->frameHeight = 320U; 1266 config->frameWidth = 480U; 1267 config->warpBitsPerPixel = 0U; 1268 config->enableSymmetricOffset = false; 1269 config->coordMode = kDPU_WarpCoordinateModePNT; 1270 config->arbStartX = 0U; 1271 config->arbStartY = 0U; 1272 config->arbDeltaYY = 0U; 1273 config->arbDeltaYX = 0U; 1274 config->arbDeltaXY = 0U; 1275 config->arbDeltaXX = 0U; 1276 @endcode 1277 * 1278 * @param config Pointer to the configuration structure. 1279 */ 1280 void DPU_FetcUnitGetDefaultWarpConfig(dpu_warp_config_t *config); 1281 1282 /*! 1283 * @brief Initialize the Warp function for FetchWarp unit. 1284 * 1285 * This function initializes the FetchWarp unit for the arbitrary warping. 1286 * 1287 * The valid source of fetch warp unit could be: 1288 * - @ref kDPU_UnitSrcNone 1289 * - @ref kDPU_UnitSrcFetchEco2 1290 * - @ref kDPU_UnitSrcFetchEco9 1291 * 1292 * @param base DPU peripheral base address. 1293 * @param unit DPU unit, see @ref dpu_unit_t, must be FetchWarp unit here. 1294 * @param config Pointer to the configuration structure. 1295 * @retval kStatus_Success Initialization success. 1296 * @retval kStatus_InvalidArgument Wrong argument. 1297 */ 1298 status_t DPU_InitFetchUnitWarp(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_warp_config_t *config); 1299 1300 /*! 1301 * @brief Get default configuration structure for fetch unit source buffer. 1302 * 1303 * The default value is: 1304 * @code 1305 config->baseAddr = 0U; 1306 config->strideBytes = 0x500U; 1307 config->bitsPerPixel = 32U; 1308 config->pixelFormat = kDPU_PixelFormatARGB8888; 1309 config->bufferHeight = 0U; 1310 config->bufferWidth = 0U; 1311 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0); 1312 @endcode 1313 * 1314 * @param config Pointer to the configuration structure. 1315 */ 1316 void DPU_SrcBufferGetDefaultConfig(dpu_src_buffer_config_t *config); 1317 1318 /*! 1319 * @brief Set the fetch unit sublayer source buffer. 1320 * 1321 * @param base DPU peripheral base address. 1322 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1323 * @param sublayer Sublayer index, should be 0 to 7. 1324 * @param config Pointer to the configuration structure. 1325 * @retval kStatus_Success Initialization success. 1326 * @retval kStatus_InvalidArgument Wrong argument. 1327 */ 1328 status_t DPU_SetFetchUnitSrcBufferConfig(IRIS_MVPL_Type *base, 1329 dpu_unit_t unit, 1330 uint8_t sublayer, 1331 const dpu_src_buffer_config_t *config); 1332 1333 /*! 1334 * @brief Set the fetch unit sublayer source buffer base address. 1335 * 1336 * @param base DPU peripheral base address. 1337 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1338 * @param sublayer Sublayer index, should be 0 to 7. 1339 * @param baseAddr Source buffer base address. 1340 */ 1341 void DPU_SetFetchUnitSrcBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_t baseAddr); 1342 1343 /*! 1344 * @brief Set the fetch unit frame size. 1345 * 1346 * @param base DPU peripheral base address. 1347 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1348 * @param height Frame height. 1349 * @param width Frame width. 1350 */ 1351 void DPU_SetFetchUnitFrameSize(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t height, uint16_t width); 1352 1353 /*! 1354 * @brief Set the fetch unit sublayer offset. 1355 * 1356 * @param base DPU peripheral base address. 1357 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1358 * @param sublayer Sublayer index, should be 0 to 7. 1359 * @param offsetX Horizontal offset. 1360 * @param offsetY Vertical offset. 1361 */ 1362 void DPU_SetFetchUnitOffset( 1363 IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint16_t offsetX, uint16_t offsetY); 1364 1365 /*! 1366 * @brief Enable or disable fetch unit sublayer source buffer. 1367 * 1368 * @param base DPU peripheral base address. 1369 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1370 * @param sublayer Sublayer index, should be 0 to 7. 1371 * @param enable True to enable, false to disable. 1372 */ 1373 void DPU_EnableFetchUnitSrcBuffer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable); 1374 1375 /*! 1376 * @brief Get default configuration structure for clip window. 1377 * 1378 * The default value is: 1379 * @code 1380 config->windowOffsetX = 0U; 1381 config->windowOffsetY = 0U; 1382 config->windowHeight = 0U; 1383 config->windowWidth = 0U; 1384 @endcode 1385 * 1386 * @param config Pointer to the configuration structure. 1387 */ 1388 void DPU_ClipWindowGetDefaultConfig(dpu_clip_window_config_t *config); 1389 1390 /*! 1391 * @brief Set the fetch unit sublayer clip window. 1392 * 1393 * @param base DPU peripheral base address. 1394 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1395 * @param sublayer Sublayer index, should be 0 to 7. 1396 * @param config Pointer to the configuration structure. 1397 */ 1398 void DPU_SetFetchUnitClipWindowConfig(IRIS_MVPL_Type *base, 1399 dpu_unit_t unit, 1400 uint8_t sublayer, 1401 const dpu_clip_window_config_t *config); 1402 1403 /*! 1404 * @brief Enable or disable the fetch unit sublayer clip window. 1405 * 1406 * @param base DPU peripheral base address. 1407 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1408 * @param sublayer Sublayer index, should be 0 to 7. 1409 * @param enable True to enable, false to disable. 1410 */ 1411 void DPU_EnableFetchUnitClipWindow(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable); 1412 1413 /*! 1414 * @brief Set the fetch unit clip color mode. 1415 * 1416 * This function selects which color to take for pixels that do not lie inside 1417 * the clip window of any layer. 1418 * 1419 * @param base DPU peripheral base address. 1420 * @param unit DPU unit, see @ref dpu_unit_t, must be fetch unit here. 1421 * @param clipColorMode Select null color or use sublayer color. 1422 * @param sublayer Select which sublayer's color to use when @p clipColorMode 1423 * is @ref kDPU_ClipColorSublayer. 1424 */ 1425 void DPU_SetFetchUnitClipColor(IRIS_MVPL_Type *base, 1426 dpu_unit_t unit, 1427 dpu_clip_color_mode_t clipColorMode, 1428 uint8_t sublayer); 1429 1430 /* @} */ 1431 1432 /*! 1433 * @name ExtDst Units 1434 * @{ 1435 */ 1436 1437 /*! 1438 * @brief Initialize the ExtDst unit. 1439 * 1440 * @param base DPU peripheral base address. 1441 * @param unit DPU unit, see @ref dpu_unit_t, must be ExtDst unit here. 1442 * @param srcReg Input source selecte register value, pixencfg_extdstX_dynamic see @ref DPU_MAKE_SRC_REG1. 1443 * The valid source: 1444 * - @ref kDPU_UnitSrcNone 1445 * - @ref kDPU_UnitSrcBlitBlend9 1446 * - @ref kDPU_UnitSrcConstFrame0 1447 * - @ref kDPU_UnitSrcConstFrame1 1448 * - @ref kDPU_UnitSrcConstFrame4 1449 * - @ref kDPU_UnitSrcConstFrame5 1450 * - @ref kDPU_UnitSrcHScaler4 1451 * - @ref kDPU_UnitSrcVScaler4 1452 * - @ref kDPU_UnitSrcHScaler5 1453 * - @ref kDPU_UnitSrcVScaler5 1454 * - @ref kDPU_UnitSrcLayerBlend0 1455 * - @ref kDPU_UnitSrcLayerBlend1 1456 * - @ref kDPU_UnitSrcLayerBlend2 1457 * - @ref kDPU_UnitSrcLayerBlend3 1458 */ 1459 void DPU_InitExtDst(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1460 1461 /* @} */ 1462 1463 /*! 1464 * @name Store Units 1465 * 1466 * The Store unit output buffer is like this: 1467 * 1468 * @verbatim 1469 1470 <-------------------- Stride --------------------> 1471 <------------- bufferWidth ----------------> 1472 ^ +------------------------------------------------+ 1473 | | ^ | | 1474 | | | Destination Buffer | | 1475 | | | offsetY | | 1476 | | v | | 1477 | |<------->+===============+ | | 1478 bufferHeight | | offsetX " " | | 1479 | | " Input Frame " | | 1480 | | " " | | 1481 | | +===============+ | | 1482 | | | | 1483 | | | | 1484 | | | | 1485 v +------------------------------------------------+ 1486 @endverbatim 1487 * 1488 * @{ 1489 */ 1490 1491 /*! 1492 * @brief Initialize the Store unit. 1493 * 1494 * The valid input source of the store unit could be: 1495 * - @ref kDPU_UnitSrcNone 1496 * - @ref kDPU_UnitSrcHScaler9 1497 * - @ref kDPU_UnitSrcVScaler9 1498 * - @ref kDPU_UnitSrcVScaler9 1499 * - @ref kDPU_UnitSrcFilter9 1500 * - @ref kDPU_UnitSrcBlitBlend9 1501 * - @ref kDPU_UnitSrcFetchDecode9 1502 * - @ref kDPU_UnitSrcFetchWarp9 1503 * 1504 * @param base DPU peripheral base address. 1505 * @param unit DPU unit, see @ref dpu_unit_t, must be Store unit here. 1506 * @param srcReg Input source selecte register value, pixencfg_extdstX_dynamic 1507 * see @ref DPU_MAKE_SRC_REG1. 1508 */ 1509 void DPU_InitStore(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1510 1511 /*! 1512 * @brief Set the Store unit Destination buffer configuration. 1513 * 1514 * @param base DPU peripheral base address. 1515 * @param unit DPU unit, see @ref dpu_unit_t, must be Store unit here. 1516 * @param config Pointer to the configuration. 1517 * @retval kStatus_Success Initialization success. 1518 * @retval kStatus_InvalidArgument Wrong argument. 1519 */ 1520 status_t DPU_SetStoreDstBufferConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_dst_buffer_config_t *config); 1521 1522 /*! 1523 * @brief Get the default configuration for Store unit. 1524 * 1525 * The default value is: 1526 * @code 1527 config->baseAddr = 0U; 1528 config->strideBytes = 0x500U; 1529 config->bitsPerPixel = 32U, 1530 config->pixelFormat = kDPU_PixelFormatARGB8888; 1531 config->bufferHeight = 0U; 1532 config->bufferWidth = 0U; 1533 @endcode 1534 * @param config Pointer to the configuration. 1535 */ 1536 void DPU_DstBufferGetDefaultConfig(dpu_dst_buffer_config_t *config); 1537 1538 /*! 1539 * @brief Set the Store unit Destination buffer base address. 1540 * 1541 * This function is run time used for better performance. 1542 * 1543 * @param base DPU peripheral base address. 1544 * @param unit DPU unit, see @ref dpu_unit_t, must be Store unit here. 1545 * @param baseAddr Base address of the Destination buffer to set. 1546 */ 1547 void DPU_SetStoreDstBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t baseAddr); 1548 1549 /*! 1550 * @brief Set the Store unit output offset. 1551 * 1552 * @param base DPU peripheral base address. 1553 * @param unit DPU unit, see @ref dpu_unit_t, must be Store unit here. 1554 * @param offsetX Horizontal offset. 1555 * @param offsetY Vertical offset. 1556 * @note The horizontal offset has limitations for some formats. It must be a multiple of 1557 * - 8 for 1 bpp buffers 1558 * - 4 for 2 bpp and 18 bpp buffers 1559 * - 2 for 4 bpp buffers 1560 */ 1561 void DPU_SetStoreOffset(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t offsetX, uint16_t offsetY); 1562 1563 /*! 1564 * @brief Start the Store unit. 1565 * 1566 * This function starts the Store unit to save the frame to output buffer. When 1567 * the frame store completed, the interrupt flag @ref kDPU_Group0Store9FrameCompleteInterrupt 1568 * asserts. 1569 * 1570 * This is an example shows how to use Store unit: 1571 * 1572 * @code 1573 Initialize the Store unit, use FetchDecode9 output as its input. 1574 DPU_InitStore(DPU, kDPU_Store9, DPU_MAKE_SRC_REG1(kDPU_UnitSrcFetchDecode9)); 1575 1576 Configure the Store unit output buffer. 1577 DPU_SetStoreDstBufferConfig(DPU, kDPU_Store9, &DstBufferConfig); 1578 1579 Configure FetchDecode9 unit, including source buffer setting and so on. 1580 ... 1581 1582 Initialize the Store9 pipeline 1583 DPU_InitPipeline(DPU, kDPU_PipelineStore9); 1584 1585 DPU_ClearUserInterruptsPendingFlags(DPU, kDPU_Group0Store9ShadowLoadInterrupt); 1586 1587 Trigger the shadow load 1588 DPU_TriggerPipelineShadowLoad(DPU, kDPU_PipelineStore9); 1589 1590 DPU_ClearUserInterruptsPendingFlags(DPU, kDPU_Group0Store9FrameCompleteInterrupt); 1591 1592 Start the Store9 to convert and output. 1593 DPU_StartStore(DPU, kDPU_Store9); 1594 1595 Wait for Store 9 completed, this could also be monitored by interrupt. 1596 while (!(kDPU_Group0Store9FrameCompleteInterrupt & DPU_GetUserInterruptsPendingFlags(DPU, 0)) 1597 { 1598 } 1599 @endcode 1600 * 1601 * For better performance, it is allowed to set next operation while current is still in progress. 1602 * Upper layer could set next operation immediately after shadow load finished. 1603 * 1604 * @param base DPU peripheral base address. 1605 * @param unit DPU unit, see @ref dpu_unit_t, must be Store unit here. 1606 */ 1607 void DPU_StartStore(IRIS_MVPL_Type *base, dpu_unit_t unit); 1608 /* @} */ 1609 1610 /*! 1611 * @name Rop units 1612 * 1613 * Rop unit combines up to three input frames to a single output frame, all having 1614 * the same dimension. It supports: 1615 * 1616 * 1. Logic Operations 1617 * Each bit of the RGBA input code is combined with the same bit from the same pixel 1618 * from the other inputs by any logical operation (= 3 to 1 bit function). The input 1619 * and output relationship is: 1620 * @verbatim 1621 1622 Tertiary Input | Secondary Input | Primary Input | Output 1623 ========================================================================== 1624 0 | 0 | 0 | operation index[0] 1625 -------------------------------------------------------------------------- 1626 0 | 0 | 1 | operation index[1] 1627 -------------------------------------------------------------------------- 1628 0 | 1 | 0 | operation index[2] 1629 -------------------------------------------------------------------------- 1630 0 | 1 | 1 | operation index[3] 1631 -------------------------------------------------------------------------- 1632 1 | 0 | 0 | operation index[4] 1633 -------------------------------------------------------------------------- 1634 1 | 0 | 1 | operation index[5] 1635 -------------------------------------------------------------------------- 1636 1 | 1 | 0 | operation index[6] 1637 -------------------------------------------------------------------------- 1638 1 | 1 | 1 | operation index[7] 1639 ========================================================================== 1640 @endverbatim 1641 * 2. Arithmetic Operations 1642 * Input RGBA codes can simply be added for each pixel, optionally with an factor 1643 * 0.5 being applied for averaging two frames. 1644 * 1645 * @{ 1646 */ 1647 1648 /*! 1649 * @brief Initialize the ROp unit. 1650 * 1651 * The primary input source of the unit could be: 1652 * - @ref kDPU_UnitSrcNone 1653 * - @ref kDPU_UnitSrcFetchDecode9 1654 * - @ref kDPU_UnitSrcFetchWarp9 1655 * 1656 * The secondary input source of the unit could be: 1657 * - @ref kDPU_UnitSrcNone 1658 * - @ref kDPU_UnitSrcFetchEco9 1659 * 1660 * The tert input source of the unit could be: 1661 * - @ref kDPU_UnitSrcNone 1662 * - @ref kDPU_UnitSrcFetchDecode9 1663 * - @ref kDPU_UnitSrcFetchWarp9 1664 * 1665 * @param base DPU peripheral base address. 1666 * @param unit DPU unit, see @ref dpu_unit_t, must be Rop unit here. 1667 * @param srcReg Unit source selection, see @ref DPU_MAKE_SRC_REG3. 1668 */ 1669 void DPU_InitRop(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1670 1671 /*! 1672 * @brief Get the default ROp unit configuration. 1673 * 1674 * The default configuration is: 1675 * 1676 * @code 1677 config->controlFlags = 0U; 1678 config->alphaIndex = 0U; 1679 config->blueIndex = 0U; 1680 config->greenIndex = 0U; 1681 config->redIndex = 0U; 1682 @endcode 1683 * @param config Pointer to the configuration structure. 1684 */ 1685 void DPU_RopGetDefaultConfig(dpu_rop_config_t *config); 1686 1687 /*! 1688 * @brief Set the ROp unit configuration. 1689 * 1690 * @param base DPU peripheral base address. 1691 * @param unit DPU unit, see @ref dpu_unit_t, must be Rop unit here. 1692 * @param config Pointer to the configuration structure. 1693 */ 1694 void DPU_SetRopConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_rop_config_t *config); 1695 1696 /*! 1697 * @brief Enable or disable the ROp unit. 1698 * 1699 * If disabled, only the primary input is output. 1700 * 1701 * @param base DPU peripheral base address. 1702 * @param unit DPU unit, see @ref dpu_unit_t, must be Rop unit here. 1703 * @param enable Pass true to enable, false to disable. 1704 */ 1705 void DPU_EnableRop(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable); 1706 1707 /* @} */ 1708 1709 /*! 1710 * @name BlitBlend units 1711 * @{ 1712 */ 1713 1714 /*! 1715 * @brief Initialize the BlitBlend unit. 1716 * 1717 * The valid input primary source could be: 1718 * - @ref kDPU_UnitSrcNone 1719 * - @ref kDPU_UnitSrcHScaler9 1720 * - @ref kDPU_UnitSrcVScaler9 1721 * - @ref kDPU_UnitSrcFilter9 1722 * - @ref kDPU_UnitSrcRop9 1723 * 1724 * The valid input secondary source could be: 1725 * - @ref kDPU_UnitSrcNone 1726 * - @ref kDPU_UnitSrcFetchDecode9 1727 * - @ref kDPU_UnitSrcFetchWarp9 1728 * 1729 * @param base DPU peripheral base address. 1730 * @param unit DPU unit, see @ref dpu_unit_t, must be BlitBlend unit here. 1731 * @param srcReg Unit source selection, see @ref DPU_MAKE_SRC_REG2. 1732 */ 1733 void DPU_InitBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1734 1735 /*! 1736 * @brief Get the default BlitBlend unit configuration. 1737 * 1738 * The default configuration is: 1739 * @code 1740 config->neutralBorderRightPixels = 0U; 1741 config->neutralBorderLeftPixels = 0U; 1742 config->neutralBorderMode = kDPU_BlitBlendNeutralBorderPrim; 1743 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0); 1744 config->redBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor; 1745 config->redBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor; 1746 config->greenBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor; 1747 config->greenBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor; 1748 config->blueBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor; 1749 config->blueBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor; 1750 config->alphaBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor; 1751 config->alphaBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor; 1752 config->redBlendMode = kDPU_BlitBlendModeGlFuncAdd; 1753 config->greenBlendMode = kDPU_BlitBlendModeGlFuncAdd; 1754 config->blueBlendMode = kDPU_BlitBlendModeGlFuncAdd; 1755 config->alphaBlendMode = kDPU_BlitBlendModeGlFuncAdd; 1756 @endcode 1757 * @param config Pointer to the configuration structure. 1758 */ 1759 void DPU_BlitBlendGetDefaultConfig(dpu_blit_blend_config_t *config); 1760 1761 /*! 1762 * @brief Set the BlitBlend unit configuration. 1763 * 1764 * @param base DPU peripheral base address. 1765 * @param unit DPU unit, see @ref dpu_unit_t, must be BlitBlend unit here. 1766 * @param config Pointer to the configuration structure. 1767 */ 1768 void DPU_SetBlitBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_blit_blend_config_t *config); 1769 1770 /*! 1771 * @brief Enable or disable the BlitBlend unit. 1772 * 1773 * The BlitBlend unit could be runtime enabled or disabled, when disabled, the 1774 * primary input is output directly. 1775 * 1776 * @param base DPU peripheral base address. 1777 * @param unit DPU unit, see @ref dpu_unit_t, must be BlitBlend unit here. 1778 * @param enable Pass true to enable, false to disable. 1779 */ 1780 void DPU_EnableBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable); 1781 1782 /* @} */ 1783 1784 /*! 1785 * @name LayerBlend units 1786 * @{ 1787 */ 1788 1789 /*! 1790 * @brief Get default configuration structure for LayerBlend. 1791 * 1792 * The default value is: 1793 * @code 1794 config->constAlpha = 0U; 1795 config->secAlphaBlendMode = kDPU_BlendOne; 1796 config->primAlphaBlendMode = kDPU_BlendZero; 1797 config->secColorBlendMode = kDPU_BlendOne; 1798 config->primColorBlendMode = kDPU_BlendZero; 1799 config->enableAlphaMask = true; 1800 config->alphaMaskMode = kDPU_AlphaMaskPrim; 1801 @endcode 1802 * 1803 * @param config Pointer to the configuration structure. 1804 */ 1805 void DPU_LayerBlendGetDefaultConfig(dpu_layer_blend_config_t *config); 1806 1807 /*! 1808 * @brief Initialize the LayerBlend. 1809 * 1810 * The valid primary source: 1811 * - @ref kDPU_UnitSrcNone 1812 * - @ref kDPU_UnitSrcConstFrame0 1813 * - @ref kDPU_UnitSrcConstFrame1 1814 * - @ref kDPU_UnitSrcConstFrame4 1815 * - @ref kDPU_UnitSrcConstFrame5 1816 * - @ref kDPU_UnitSrcHScaler4 1817 * - @ref kDPU_UnitSrcVScaler4 1818 * - @ref kDPU_UnitSrcHScaler5 1819 * - @ref kDPU_UnitSrcVScaler5 1820 * - @ref kDPU_UnitSrcMatrix4 1821 * - @ref kDPU_UnitSrcMatrix5 1822 * - @ref kDPU_UnitSrcLayerBlend0 1823 * - @ref kDPU_UnitSrcLayerBlend1 1824 * - @ref kDPU_UnitSrcLayerBlend2 1825 * - @ref kDPU_UnitSrcLayerBlend3 1826 * 1827 * The valid secondary source: 1828 * - @ref kDPU_UnitSrcNone 1829 * - @ref kDPU_UnitSrcConstFrame0 1830 * - @ref kDPU_UnitSrcConstFrame1 1831 * - @ref kDPU_UnitSrcConstFrame4 1832 * - @ref kDPU_UnitSrcConstFrame5 1833 * - @ref kDPU_UnitSrcHScaler4 1834 * - @ref kDPU_UnitSrcVScaler4 1835 * - @ref kDPU_UnitSrcHScaler5 1836 * - @ref kDPU_UnitSrcVScaler5 1837 * - @ref kDPU_UnitSrcMatrix4 1838 * - @ref kDPU_UnitSrcMatrix5 1839 * - @ref kDPU_UnitSrcLayerBlend0 1840 * - @ref kDPU_UnitSrcLayerBlend1 1841 * - @ref kDPU_UnitSrcLayerBlend2 1842 * - @ref kDPU_UnitSrcLayerBlend3 1843 * 1844 * @param base DPU peripheral base address. 1845 * @param unit DPU unit, see @ref dpu_unit_t, must be LayerBlend unit here. 1846 * @param srcReg Unit source selection, see @ref DPU_MAKE_SRC_REG2. 1847 */ 1848 void DPU_InitLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg); 1849 1850 /*! 1851 * @brief Set the LayerBlend unit configuration. 1852 * 1853 * @param base DPU peripheral base address. 1854 * @param unit DPU unit, see @ref dpu_unit_t, must be LayerBlend unit here. 1855 * @param config Pointer to the configuration structure. 1856 */ 1857 void DPU_SetLayerBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_layer_blend_config_t *config); 1858 1859 /*! 1860 * @brief Enable or disable the LayerBlend unit. 1861 * 1862 * If enabled, the blend result is output, otherwise, the primary input is output. 1863 * 1864 * @param base DPU peripheral base address. 1865 * @param unit DPU unit, see @ref dpu_unit_t, must be LayerBlend unit here. 1866 * @param enable Pass true to enable, false to disable. 1867 */ 1868 void DPU_EnableLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable); 1869 1870 /* @} */ 1871 1872 /*! 1873 * @name ConstFrame units 1874 * @{ 1875 */ 1876 1877 /*! 1878 * @brief Initialize the ConstFrame unit. 1879 * 1880 * @param base DPU peripheral base address. 1881 * @param unit DPU unit, see @ref dpu_unit_t, must be ConstFrame unit here. 1882 */ 1883 void DPU_InitConstFrame(IRIS_MVPL_Type *base, dpu_unit_t unit); 1884 1885 /*! 1886 * @brief Get default configuration structure for ConstFrame unit. 1887 * 1888 * The default value is: 1889 @code 1890 config->frameHeight = 320U; 1891 config->frameWidth = 480U; 1892 config->constColor = DPU_MAKE_CONST_COLOR(0xFF, 0xFF, 0xFF, 0xFF); 1893 @endcode 1894 * 1895 * @param config Pointer to the configuration structure. 1896 */ 1897 void DPU_ConstFrameGetDefaultConfig(dpu_const_frame_config_t *config); 1898 1899 /*! 1900 * @brief Set the ConstFrame unit configuration. 1901 * 1902 * @param base DPU peripheral base address. 1903 * @param unit DPU unit, see @ref dpu_unit_t, must be ConstFrame unit here. 1904 * @param config Pointer to the configuration structure. 1905 */ 1906 void DPU_SetConstFrameConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_const_frame_config_t *config); 1907 1908 /* @} */ 1909 1910 /*! 1911 * @name VScaler and HScaler units 1912 * 1913 * @note When both horizontal and vertical scaling is active, then the sequence 1914 * of both units in the Pixelbus configuration should be 1915 * 1916 * -> HScaler -> VScaler -> when down-scaling horizontally 1917 * -> VScaler -> HScaler -> when up-scaling horizontally 1918 * 1919 * @{ 1920 */ 1921 1922 /*! 1923 * @brief Initialize the VScaler or HScaler unit. 1924 * 1925 * @param base DPU peripheral base address. 1926 * @param unit DPU unit, see @ref dpu_unit_t, must be HScaler or VScaler unit here. 1927 */ 1928 void DPU_InitScaler(IRIS_MVPL_Type *base, dpu_unit_t unit); 1929 1930 /*! 1931 * @brief Get default configuration structure for VScaler and HScaler. 1932 * 1933 * The default value is: 1934 @code 1935 config->srcReg = 0U; 1936 config->inputSize = 0U; 1937 config->outputSize = 0U; 1938 @endcode 1939 * 1940 * @param config Pointer to the configuration structure. 1941 */ 1942 void DPU_ScalerGetDefaultConfig(dpu_scaler_config_t *config); 1943 1944 /*! 1945 * @brief Set the VScaler or HScaler units configuration. 1946 * 1947 * The valid input source could be: 1948 * - @ref kDPU_UnitSrcNone 1949 * - @ref kDPU_UnitSrcFetchDecode0 1950 * - @ref kDPU_UnitSrcMatrix4 1951 * - @ref kDPU_UnitSrcVScaler4 1952 * - @ref kDPU_UnitSrcHScaler4 1953 * - @ref kDPU_UnitSrcFetchDecode1 1954 * - @ref kDPU_UnitSrcMatrix5 1955 * - @ref kDPU_UnitSrcVScaler5 1956 * - @ref kDPU_UnitSrcHScaler5 1957 * - @ref kDPU_UnitSrcVScaler9 1958 * - @ref kDPU_UnitSrcHScaler9 1959 * - @ref kDPU_UnitSrcFilter9 1960 * - @ref kDPU_UnitSrcMatrix9 1961 * 1962 * @param base DPU peripheral base address. 1963 * @param unit DPU unit, see @ref dpu_unit_t, must be HScaler or VScaler unit here. 1964 * @param config Pointer to the configuration structure. 1965 */ 1966 void DPU_SetScalerConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_scaler_config_t *config); 1967 1968 /* @} */ 1969 1970 /*! 1971 * @name Display engine 1972 * @{ 1973 */ 1974 1975 /*! 1976 * @brief Get default configuration structure for display mode. 1977 * 1978 * The default value is: 1979 * @code 1980 config->flags = kDPU_DisplayDeActiveHigh; 1981 config->width = 320U; 1982 config->hsw = 32U; 1983 config->hfp = 8U; 1984 config->hbp = 40U; 1985 config->height = 240U; 1986 config->vsw = 4U; 1987 config->vfp = 13U; 1988 config->vbp = 6U; 1989 @endcode 1990 * 1991 * @param config Pointer to the configuration structure. 1992 */ 1993 void DPU_DisplayTimingGetDefaultConfig(dpu_display_timing_config_t *config); 1994 1995 /*! 1996 * @brief Initialize the display timing. 1997 * 1998 * @param base DPU peripheral base address. 1999 * @param displayIndex Index of the display. 2000 * @param config Pointer to the configuration structure. 2001 */ 2002 void DPU_InitDisplayTiming(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_display_timing_config_t *config); 2003 2004 /*! 2005 * @brief Get default configuration structure for display frame mode. 2006 * 2007 * The default value is: 2008 @code 2009 config->enablePrimAlpha = false; 2010 config->enableSecAlpha = false; 2011 config->displayMode = kDPU_DisplayTest; 2012 config->enablePrimAlphaInPanic = false; 2013 config->enableSecAlphaInPanic = false; 2014 config->displayModeInPanic = kDPU_DisplayTest; 2015 config->constRed = 0x3FFU; 2016 config->constGreen = 0x3FFU; 2017 config->constBlue = 0x3FFU; 2018 config->constAlpha = 1U; 2019 config->primAreaStartX = 1U; 2020 config->primAreaStartY = 1U; 2021 config->secAreaStartX = 1U; 2022 config->secAreaStartY = 1U; 2023 @endcode 2024 * 2025 * @param config Pointer to the configuration structure. 2026 */ 2027 void DPU_DisplayGetDefaultConfig(dpu_display_config_t *config); 2028 2029 /*! 2030 * @brief Set the display mode. 2031 * 2032 * @param base DPU peripheral base address. 2033 * @param displayIndex Index of the display. 2034 * @param config Pointer to the configuration structure. 2035 */ 2036 void DPU_SetDisplayConfig(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_display_config_t *config); 2037 2038 /*! 2039 * @brief Start the display. 2040 * 2041 * @param base DPU peripheral base address. 2042 * @param displayIndex Index of the display. 2043 */ 2044 void DPU_StartDisplay(IRIS_MVPL_Type *base, uint8_t displayIndex); 2045 2046 /*! 2047 * @brief Stop the display. 2048 * 2049 * This function stops the display and wait the sequence complete. 2050 * 2051 * @param base DPU peripheral base address. 2052 * @param displayIndex Index of the display. 2053 */ 2054 void DPU_StopDisplay(IRIS_MVPL_Type *base, uint8_t displayIndex); 2055 2056 /*! 2057 * @brief Clear the FrameGen unit status flags. 2058 * 2059 * @param base DPU peripheral base address. 2060 * @param displayIndex Display index. 2061 * @param interruptIndex Interrupt index, there could be 4 interrupts for each display. 2062 * @param intConfig Interrupt mode, could be one of DPU_FRAME_GEN_INT_DISABLE, 2063 * DPU_FRAME_GEN_INT_PER_LINE, and DPU_FRAME_GEN_INT_PER_FRAME. 2064 */ 2065 void DPU_SetFrameGenInterruptConfig(IRIS_MVPL_Type *base, 2066 uint8_t displayIndex, 2067 uint8_t interruptIndex, 2068 uint32_t intConfig); 2069 2070 /*! 2071 * @brief Trigger the display stream shadow load token. 2072 * 2073 * Trigger the display stream shadow load token, then the shadow register will 2074 * be loaded at the begining of next frame. 2075 * 2076 * @param base DPU peripheral base address. 2077 * @param displayIndex Display index. 2078 */ 2079 void DPU_TriggerDisplayShadowLoad(IRIS_MVPL_Type *base, uint8_t displayIndex); 2080 2081 /* @} */ 2082 2083 /*! 2084 * @name Signature unit 2085 * 2086 * The Signature unit could compute the CRC value of interested region and compare 2087 * to the reference value to detect incorrect display output. 2088 * 2089 * Up to 8 evaluation windows can be setup. Signature computation and reference check 2090 * is done individually for each window. 2091 * 2092 * A pixel of the input frame does not contribute to more than one window. In case of 2093 * overlapping windows, the window with larger index is on top. 2094 * 2095 * Alpha mask could be involved into the signature evaluation, thus any kind of shape 2096 * could be monitored. 2097 * 2098 * Note that the mask is considered for checksum computation only, not for assignment 2099 * of individual pixels to a certain evaluation window. So, a non-rectangular overlap 2100 * between different windows is not possible. 2101 * 2102 * An evaluation window could be configured as skipped. This provides another method for 2103 * monitoring non-rectangular windows. For example: 2104 * 2105 * @verbatim 2106 +------------------------------------------------+ 2107 | | 2108 | | 2109 | +-------------------+ | 2110 | | Window 0 xxxxxxxxx| | 2111 | |xxxxxxxxxxxxxxxxxxx| | 2112 | |xxxxxxxx+-------------------------------+ | 2113 | |xxxxxxxx| Window 1 (Skipped) | | 2114 | |xxxxxxxx| | | 2115 | +--------| | | 2116 | | | | 2117 | +-------------------------------+ | 2118 | | 2119 +------------------------------------------------+ 2120 @endverbatim 2121 * 2122 * In this example, windows 1 is skipped, in this case, only the shadow part of 2123 * window 0 is monitored. 2124 * 2125 * @{ 2126 */ 2127 2128 /*! 2129 * @brief Get Signature unit default configuration. 2130 * 2131 * The default configuration is: 2132 * 2133 * @code 2134 config->errorThreshold = 0U; 2135 config->errorResetThreshold = 8U; 2136 config->panicRed = 0U; 2137 config->panicGreen = 0U; 2138 config->panicBlue = 0U; 2139 config->panicAlpha = 0U; 2140 @endcode 2141 * @param config Pointer to the configuration. 2142 */ 2143 void DPU_SignatureGetDefaultConfig(dpu_signature_config_t *config); 2144 2145 /*! 2146 * @brief Initialize the Signature unit. 2147 * 2148 * @param base DPU peripheral base address. 2149 * @param displayIndex Display index. 2150 * @param config Pointer to the configuration. 2151 */ 2152 void DPU_InitSignature(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_signature_config_t *config); 2153 2154 /*! 2155 * @brief Get Signature unit validate window default configuration. 2156 * 2157 * The default configuration is: 2158 * 2159 * @code 2160 config->controlFlags = 0U; 2161 config->upperLeftX = 0U; 2162 config->upperLeftY = 0U; 2163 config->lowerRightX = 0U; 2164 config->lowerRightY = 0U; 2165 @endcode 2166 * 2167 * @param config Pointer to the configuration. 2168 */ 2169 void DPU_SignatureWindowGetDefaultConfig(dpu_signature_window_config_t *config); 2170 2171 /*! 2172 * @brief Set the Signature unit evaluation window configuration. 2173 * 2174 * @param base DPU peripheral base address. 2175 * @param displayIndex Display index. 2176 * @param windowIndex Evaluation window index, should be 0 to 7. 2177 * @param config Pointer to the configuration. 2178 */ 2179 void DPU_SetSignatureWindowConfig(IRIS_MVPL_Type *base, 2180 uint8_t displayIndex, 2181 uint8_t windowIndex, 2182 const dpu_signature_window_config_t *config); 2183 2184 /*! 2185 * @brief Enable or disable the Signature unit evaluation window CRC value computation. 2186 * 2187 * When enabled, a CRC signature is computed for all pixels inside this evaluation window, 2188 * When disabled, the internal status for this window is reset (StsSigError bit and frame counters) 2189 * 2190 * @param base DPU peripheral base address. 2191 * @param displayIndex Display index. 2192 * @param windowIndex Evaluation window index, should be 0 to 7. 2193 * @param enable Pass true to enable, false to disable. 2194 */ 2195 void DPU_EnableSignatureWindowCompute(IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable); 2196 2197 /*! 2198 * @brief Enable or disable the Signature unit evaluation window CRC value check. 2199 * 2200 * When enabled, the measured signature is checked against a reference value. 2201 * 2202 * @param base DPU peripheral base address. 2203 * @param displayIndex Display index. 2204 * @param windowIndex Evaluation window index, should be 0 to 7. 2205 * @param enable Pass true to enable, false to disable. 2206 */ 2207 void DPU_EnableSignatureWindowCheck(IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable); 2208 2209 /*! 2210 * @brief Get the measured signature value of the evaluation window. 2211 * 2212 * @param base DPU peripheral base address. 2213 * @param displayIndex Display index. 2214 * @param windowIndex Evaluation window index, should be 0 to 7. 2215 * @param redCRC Measured signature value of red. 2216 * @param greenCRC Measured signature value of green. 2217 * @param blueCRC Measured signature value of blue. 2218 */ 2219 void DPU_GetSignatureWindowCrc(IRIS_MVPL_Type *base, 2220 uint8_t displayIndex, 2221 uint8_t windowIndex, 2222 uint32_t *redCRC, 2223 uint32_t *greenCRC, 2224 uint32_t *blueCRC); 2225 2226 /*! 2227 * @brief Set the reference signature value of the evaluation window. 2228 * 2229 * @param base DPU peripheral base address. 2230 * @param displayIndex Display index. 2231 * @param windowIndex Evaluation window index, should be 0 to 7. 2232 * @param redCRC Reference signature value of red. 2233 * @param greenCRC Referencesignature value of green. 2234 * @param blueCRC Reference signature value of blue. 2235 */ 2236 void DPU_SetSignatureWindowRefCrc(IRIS_MVPL_Type *base, 2237 uint8_t displayIndex, 2238 uint8_t windowIndex, 2239 uint32_t redCRC, 2240 uint32_t greenCRC, 2241 uint32_t blueCRC); 2242 2243 /*! 2244 * @brief Get the signature unit status. 2245 * 2246 * This function returns the signature unit status. The return value could be 2247 * compared to check the status defined in @ref _dpu_signature_status. 2248 * For example: 2249 * 2250 * @code 2251 uint32_t status = DPU_GetSignatureStatus(DPU, 0); 2252 2253 if (kDPU_SignatureValid & status) 2254 { 2255 DPU_GetSignatureWindowCrc(...); 2256 } 2257 @endcode 2258 * 2259 * The error flags are also returned as an mask value, upper layer could get specific 2260 * window status by checking the returned bit accordingly. For example, 2261 * 2262 * @code 2263 uint32_t status = DPU_GetSignatureStatus(DPU, 0); 2264 2265 if ((1<<3) & status) 2266 { 2267 Window 3 error detected. 2268 } 2269 2270 if ((1<<5) & status) 2271 { 2272 Window 5 error detected. 2273 } 2274 2275 @endcode 2276 * 2277 * @param base DPU peripheral base address. 2278 * @param displayIndex Display index. 2279 * @return Mask value of status. 2280 */ 2281 uint32_t DPU_GetSignatureStatus(IRIS_MVPL_Type *base, uint8_t displayIndex); 2282 2283 /*! 2284 * @brief Trigger the Signature unit configuration shadow load. 2285 * 2286 * When new configuration set by @ref DPU_SetSignatureWindowConfig, 2287 * @ref DPU_EnableSignatureWindowCheck, @ref DPU_EnableSignatureWindowCompute, 2288 * and @ref DPU_SetSignatureWindowRefCrc, use this function to trigger the 2289 * shadow load, then the new configuration takes effect. 2290 * 2291 * Upper layer should monitor the @ref kDPU_Group0Sig0ShadowLoadInterrupt or 2292 * @ref kDPU_Group1Sig1ShadowLoadInterrupt to wait shadow load finished. New 2293 * configurations should only be set after shadow load finished. 2294 * 2295 * @param base DPU peripheral base address. 2296 * @param displayIndex Display index. 2297 */ 2298 void DPU_TriggerSignatureShadowLoad(IRIS_MVPL_Type *base, uint8_t displayIndex); 2299 2300 /* @} */ 2301 2302 #if defined(__cplusplus) 2303 } 2304 #endif /* __cplusplus */ 2305 2306 /* @} */ 2307 2308 #endif /* _FSL_DPU_H_ */ 2309
