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Searched refs:hwChannel (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c227 extern void Emios_Icu_Ip_SignalMeasurementHandler(const uint8 instance, const uint8 hwChannel, bool…
244 const uint8 hwChannel,
265 const uint8 hwChannel
282 const uint8 hwChannel
299 const uint8 hwChannel,
312 uint8 hwChannel,
343 const uint8 hwChannel, in Emios_Icu_Ip_UCSetMode() argument
349 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_MODE_MASK; in Emios_Icu_Ip_UCSetMode()
351 s_emiosBase[instance]->CH.UC[hwChannel].C |= (u32Mode & eMIOS_C_MODE_MASK); in Emios_Icu_Ip_UCSetMode()
357 uint8 hwChannel, in Emios_Icu_Ip_GetMasterBus() argument
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DEmios_Icu_Ip_Irq.c187 static inline void Emios_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel, boolean bOverflow);
197 static inline void Emios_Icu_Ip_ReportOverflow(uint8 instance, uint8 hwChannel, boolean bOverflow);
212 const uint8 hwChannel
228 const uint8 hwChannel
245 const uint8 hwChannel,
263 const uint8 hwChannel
267 uint8 hwChannel,
281 const uint8 hwChannel
287 const uint8 hwChannel,
294 const uint8 hwChannel,
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DSiul2_Icu_Ip.c219 uint8 hwChannel; in Siul2_Icu_Ip_DeInit() local
228 for(hwChannel = 0; hwChannel < (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS; hwChannel++) in Siul2_Icu_Ip_DeInit()
231 if (Siul2_Icu_Ip_IndexInChState[instance][hwChannel] < SIUL2_ICU_IP_NUM_OF_CHANNELS_USED) in Siul2_Icu_Ip_DeInit()
233 … if(TRUE == Siul2_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][hwChannel]].chInit) in Siul2_Icu_Ip_DeInit()
236 Siul2_Icu_Ip_DisableInterrupt (instance, hwChannel); in Siul2_Icu_Ip_DeInit()
238 base->IREER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
239 base->IFEER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
241 base->IFER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
243 base->IFMCR[hwChannel] = 0x0U; in Siul2_Icu_Ip_DeInit()
245 … Siul2_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][hwChannel]].chInit = FALSE; in Siul2_Icu_Ip_DeInit()
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DWkpu_Ip.c399 void Wkpu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel) in Wkpu_Ip_EnableInterrupt() argument
407 DevAssert(hwChannel < WKPU_IP_NUM_OF_CHANNELS); in Wkpu_Ip_EnableInterrupt()
414 if(32U > hwChannel) in Wkpu_Ip_EnableInterrupt()
416 channelMaskLo = (uint32)1UL << (uint32)hwChannel; in Wkpu_Ip_EnableInterrupt()
423 channelMaskHi = (uint32)1UL << ((uint32)hwChannel - (uint32)32U); in Wkpu_Ip_EnableInterrupt()
462 void Wkpu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel) in Wkpu_Ip_DisableInterrupt() argument
470 DevAssert(hwChannel < WKPU_IP_NUM_OF_CHANNELS); in Wkpu_Ip_DisableInterrupt()
477 if(32U > hwChannel) in Wkpu_Ip_DisableInterrupt()
479 channelMaskLo = (uint32)1UL << (uint32)hwChannel; in Wkpu_Ip_DisableInterrupt()
486 channelMaskHi = (uint32)1UL << ((uint32)hwChannel - (uint32)32U); in Wkpu_Ip_DisableInterrupt()
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DWkpu_Ip_Irq.c129 static inline void Wkpu_Ip_Callback(uint8 hwChannel);
225 static inline void Wkpu_Ip_Callback(uint8 hwChannel) in Wkpu_Ip_Callback() argument
227 if(((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].chInit) && \ in Wkpu_Ip_Callback()
228 (NULL_PTR != Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].callback)) in Wkpu_Ip_Callback()
230 …pu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].callback(Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChS… in Wkpu_Ip_Callback()
235 if (((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].chInit) && \ in Wkpu_Ip_Callback()
236 …(NULL_PTR != Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[(uint8)hwChannel]].WkpuChannelNotification)… in Wkpu_Ip_Callback()
237 … ((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].notificationEnable)) in Wkpu_Ip_Callback()
239 Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[(uint8)hwChannel]].WkpuChannelNotification(); in Wkpu_Ip_Callback()
DSiul2_Icu_Ip_Irq.c172 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel);
267 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel) in Siul2_Icu_Ip_ReportEvents() argument
269 uint8 u8ChIndex = Siul2_Icu_Ip_IndexInChState[instance][hwChannel]; in Siul2_Icu_Ip_ReportEvents()
/hal_nxp-3.5.0/s32/drivers/s32ze/Icu/src/
DSiul2_Icu_Ip.c187 uint8 hwChannel; in Siul2_Icu_Ip_DeInit() local
196 for(hwChannel = 0; hwChannel < (uint8)SIUL2_ICU_IP_NUM_OF_CHANNELS; hwChannel++) in Siul2_Icu_Ip_DeInit()
199 if(TRUE == Siul2_Icu_Ip_aChannelState[instance][hwChannel].chInit) in Siul2_Icu_Ip_DeInit()
202 Siul2_Icu_Ip_DisableInterrupt (instance, hwChannel); in Siul2_Icu_Ip_DeInit()
204 base->IREER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
205 base->IFEER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
207 base->IFER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DeInit()
209 base->IFMCR[hwChannel] = 0x0U; in Siul2_Icu_Ip_DeInit()
211 Siul2_Icu_Ip_aChannelState[instance][hwChannel].chInit = FALSE; in Siul2_Icu_Ip_DeInit()
212 Siul2_Icu_Ip_aChannelState[instance][hwChannel].callback = NULL_PTR; in Siul2_Icu_Ip_DeInit()
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DSiul2_Icu_Ip_Irq.c163 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel);
258 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel) in Siul2_Icu_Ip_ReportEvents() argument
261 if (Siul2_Icu_Ip_aChannelState[instance][hwChannel].callback != NULL_PTR) in Siul2_Icu_Ip_ReportEvents()
263 …Siul2_Icu_Ip_aChannelState[instance][hwChannel].callback(Siul2_Icu_Ip_aChannelState[instance][hwCh… in Siul2_Icu_Ip_ReportEvents()
268 … if ((NULL_PTR != Siul2_Icu_Ip_aChannelState[instance][hwChannel].Siul2ChannelNotification) && \ in Siul2_Icu_Ip_ReportEvents()
269 ((boolean)TRUE == Siul2_Icu_Ip_aChannelState[instance][hwChannel].notificationEnable)) in Siul2_Icu_Ip_ReportEvents()
271 Siul2_Icu_Ip_aChannelState[instance][hwChannel].Siul2ChannelNotification(); in Siul2_Icu_Ip_ReportEvents()
/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/include/
DEmios_Icu_Ip.h192 void Emios_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
202 void Emios_Icu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel);
214 void Emios_Icu_Ip_SetActivation(uint8 instance, uint8 hwChannel, eMios_Icu_Ip_EdgeType edge);
226 void Emios_Icu_Ip_EnableEdgeDetection(uint8 instance, uint8 hwChannel);
237 void Emios_Icu_Ip_DisableEdgeDetection(uint8 instance, uint8 hwChannel);
247 void Emios_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
256 void Emios_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel);
277 uint8 hwChannel,
297 uint8 hwChannel
310 void Emios_Icu_Ip_StopTimestamp(uint8 instance, uint8 hwChannel);
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DWkpu_Ip.h154 void Wkpu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
165 void Wkpu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel);
176 void Wkpu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
186 void Wkpu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
225 void Wkpu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Wkpu_Ip_EdgeType edge);
239 boolean Wkpu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
244 void Wkpu_Ip_EnableNotification(uint8 hwChannel);
249 void Wkpu_Ip_DisableNotification(uint8 hwChannel);
DSiul2_Icu_Ip.h177 void Siul2_Icu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Siul2_Icu_Ip_EdgeType edg…
187 boolean Siul2_Icu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
198 void Siul2_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
208 void Siul2_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
219 void Siul2_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
253 void Siul2_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
262 void Siul2_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel);
DEmios_Icu_Ip_Irq.h164 void Emios_Icu_Ip_SignalMeasurementHandler(const uint8 instance, const uint8 hwChannel, boolean bOv…
178 void Emios_Icu_Ip_TimestampDmaProcessing(uint8 instance, uint8 hwChannel);
192 void Emios_Icu_Ip_SignalMeasurementDmaProcessing(uint8 instance, uint8 hwChannel);
DSiul2_Icu_Ip_Types.h136 …uint8 hwChannel; /**< @brief The interrupt pin index … member
DWkpu_Ip_Types.h159 …uint8 hwChannel; /**< @brief The WKPU hardware channel. … member
DEmios_Icu_Ip_Types.h327 uint8 hwChannel; /*!< Channel Id */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Icu/include/
DSiul2_Icu_Ip.h170 void Siul2_Icu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Siul2_Icu_Ip_EdgeType edg…
180 boolean Siul2_Icu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
191 void Siul2_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
201 void Siul2_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
212 void Siul2_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
246 void Siul2_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
255 void Siul2_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel);
DSiul2_Icu_Ip_Types.h134 …uint8 hwChannel; /**< @brief The interrupt pin index … member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c194 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK; in Emios_Mcl_Ip_Init()
198 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*Con… in Emios_Mcl_Ip_Init()
203 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
206 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
209 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].B = 0; in Emios_Mcl_Ip_Init()
210 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
213 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
216 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
224 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].CNT = (*ConfigPtr->masterBusC… in Emios_Mcl_Ip_Init()
227 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_MODE((*ConfigPtr… in Emios_Mcl_Ip_Init()
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/hal_nxp-3.5.0/s32/drivers/s32ze/Gpt/src/
DStm_Ip.c539 DevAssert(STM_CHANNEL_COUNT > configPtr->hwChannel); in Stm_Ip_InitChannel()
543 Stm_Ip_ChannelEnable(instance, configPtr->hwChannel, FALSE); in Stm_Ip_InitChannel()
545 Stm_Ip_ClearInterruptFlag(instance, configPtr->hwChannel); in Stm_Ip_InitChannel()
547 Stm_Ip_SetCmpValue(instance, configPtr->hwChannel, 0U); in Stm_Ip_InitChannel()
555 Stm_Ip_u32ChState[instance][configPtr->hwChannel].chInit = TRUE; in Stm_Ip_InitChannel()
556 Stm_Ip_u32ChState[instance][configPtr->hwChannel].callback = configPtr->callback; in Stm_Ip_InitChannel()
557 Stm_Ip_u32ChState[instance][configPtr->hwChannel].callbackParam = configPtr->callbackParam; in Stm_Ip_InitChannel()
558 Stm_Ip_u32ChState[instance][configPtr->hwChannel].channelMode = configPtr->channelMode; in Stm_Ip_InitChannel()
/hal_nxp-3.5.0/s32/drivers/s32ze/Gpt/include/
DStm_Ip_Types.h141 uint8 hwChannel; /**< @brief Timer channel number */ member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/include/
DEmios_Mcl_Ip_Types.h112 const uint8 hwChannel; member