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Searched refs:clk (Results 1 – 25 of 97) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h885 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
887 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
892 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
895 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
898 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
915 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
917 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h885 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
887 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
892 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
895 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
898 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
915 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
917 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/svc/pm/
Dpm_api.h512 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
537 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
565 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
589 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
610 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/svc/pm/
Dpm_api.h522 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
547 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
575 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
599 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
620 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC804/drivers/
Dfsl_clock.h368 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
370 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) |= in CLOCK_EnableClock()
371 1UL << CLK_GATE_GET_BITS_SHIFT(clk); in CLOCK_EnableClock()
379 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
381 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) &= in CLOCK_DisableClock()
382 ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/mcan/
Dfsl_mcan.c461 uint32_t clk; /* the clock is tqNumb x baudRate. */ in MCAN_CalculateImprovedNominalTimingValues() local
471 clk = baudRate * tqNum; in MCAN_CalculateImprovedNominalTimingValues()
472 if (clk > sourceClock_Hz) in MCAN_CalculateImprovedNominalTimingValues()
477 if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) in MCAN_CalculateImprovedNominalTimingValues()
483 configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); in MCAN_CalculateImprovedNominalTimingValues()
543 uint32_t clk; in MCAN_FDCalculateImprovedTimingValues() local
562 clk = baudRateFD * tqNum; in MCAN_FDCalculateImprovedTimingValues()
563 if (clk > sourceClock_Hz) in MCAN_FDCalculateImprovedTimingValues()
568 if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) in MCAN_FDCalculateImprovedTimingValues()
573 pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); in MCAN_FDCalculateImprovedTimingValues()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h1098 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
1100 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1128 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
1130 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h1098 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
1100 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1128 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
1130 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h1098 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
1100 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1128 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
1130 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/drivers/
Dfsl_clock.h564 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
566 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
569 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
573 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
577 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
579 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
582 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
586 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/drivers/
Dfsl_clock.h463 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
465 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
468 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
472 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
476 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
478 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
481 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
485 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/drivers/
Dfsl_clock.h463 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
465 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
468 SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
472 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
476 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
478 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
481 SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
485 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()

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