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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_crc/
Dfsl_crc.c162 *((__O uint8_t *)&(base->WR_DATA)) = *data; in CRC_WriteData()
171 *((__O uint32_t *)&(base->WR_DATA)) = *data32; in CRC_WriteData()
181 *((__O uint8_t *)&(base->WR_DATA)) = *data; in CRC_WriteData()
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MSCM.h93 …__O uint32_t IRCP0IGR0; /**< Interrupt Router CP0 Interrupt Generation, o…
95 …__O uint32_t IRCP0IGR1; /**< Interrupt Router CP0 Interrupt Generation, o…
97 …__O uint32_t IRCP0IGR2; /**< Interrupt Router CP0 Interrupt Generation, o…
99 …__O uint32_t IRCP0IGR3; /**< Interrupt Router CP0 Interrupt Generation, o…
101 …__O uint32_t IRCP1IGR0; /**< Interrupt Router CP1 Interrupt Generation, o…
103 …__O uint32_t IRCP1IGR1; /**< Interrupt Router CP1 Interrupt Generation, o…
105 …__O uint32_t IRCP1IGR2; /**< Interrupt Router CP1 Interrupt Generation, o…
107 …__O uint32_t IRCP1IGR3; /**< Interrupt Router CP1 Interrupt Generation, o…
DS32K344_SCB.h111 …__O uint32_t STIR; /**< Software Triggered Interrupt Register, offse…
117 …__O uint32_t ICIALLU; /**< Instruction cache invalidate all to Point of…
119 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P…
120 …__O uint32_t DCIMVAC; /**< Data cache invalidate by address to Point of…
121 …__O uint32_t DCISW; /**< Data cache invalidate by set/way, offset: 0x…
122 …__O uint32_t DCCMVAU; /**< Data cache by address to PoU, offset: 0xF64 …
123 …__O uint32_t DCCMVAC; /**< Data cache clean by address to PoC, offset: …
124 …__O uint32_t DCCSW; /**< Data cache clean by set/way, offset: 0xF6C */
125 …__O uint32_t DCCIMVAC; /**< Data cache clean and invalidate by address t…
126 …__O uint32_t DCCISW; /**< Data cache clean and invalidate by set/way, …
DS32K344_FCCU.h84 __O uint32_t CTRLK; /**< Control Key, offset: 0x4 */
93 __O uint32_t NCFK; /**< Non-critical Fault Key, offset: 0x90 */
107 __O uint32_t NCFF; /**< Non-critical Fault Fake, offset: 0xDC */
111 …__O uint32_t TRANS_LOCK; /**< Transient Configuration Lock, offset: 0xF0 */
112 …__O uint32_t PERMNT_LOCK; /**< Permanent Configuration Lock, offset: 0xF4 */
DS32K344_FLEXIO.h116 __O uint32_t PINOUTDIS; /**< Pin Output Disable Register, offset: 0x68 */
117 __O uint32_t PINOUTCLR; /**< Pin Output Clear Register, offset: 0x6C */
118 __O uint32_t PINOUTSET; /**< Pin Output Set Register, offset: 0x70 */
119 __O uint32_t PINOUTTOG; /**< Pin Output Toggle Register, offset: 0x74 */
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SCB.h113 …__O uint32_t STIR; /**< Software Triggered Interrupt Register, offse…
119 …__O uint32_t ICIALLU; /**< Instruction cache invalidate all to Point of…
121 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P…
122 …__O uint32_t DCIMVAC; /**< Data cache invalidate by address to Point of…
123 …__O uint32_t DCISW; /**< Data cache invalidate by set/way, offset: 0x…
124 …__O uint32_t DCCMVAU; /**< Data cache by address to PoU, offset: 0xF64 …
125 …__O uint32_t DCCMVAC; /**< Data cache clean by address to PoC, offset: …
126 …__O uint32_t DCCSW; /**< Data cache clean by set/way, offset: 0xF6C */
127 …__O uint32_t DCCIMVAC; /**< Data cache clean and invalidate by address t…
128 …__O uint32_t DCCISW; /**< Data cache clean and invalidate by set/way, …
DS32Z2_DBG.h74 …__O uint32_t DBGACS; /**< Error Access Control Register, offset: 0x4 */
95 …__O uint32_t CENSIRQ_S; /**< Critical Error Interrupt Request Shadow Regi…
96 …__O uint32_t CENSIRQ2_S; /**< Critical Error Interrupt Request 2 Shadow Re…
97 …__O uint32_t CWDOGIRQ_S; /**< Critical Error Interrupt Request Shadow Regi…
98 …__O uint32_t NENSIRQ_S; /**< Normal Error Interrupt Requests Shadow Regis…
99 …__O uint32_t TIMER_IRQ_S; /**< Timer Interrupt Shadow Register, offset: 0x7…
100 …__O uint32_t DMA_IRQ_S; /**< DMA Interrupt Shadow Register, offset: 0x74 …
DS32Z2_I3C.h88 __O uint32_t SWDATAB; /**< Slave Write Data Byte, offset: 0x30 */
89 __O uint32_t SWDATABE; /**< Slave Write Data Byte End, offset: 0x34 */
90 __O uint32_t SWDATAH; /**< Slave Write Data Half-word, offset: 0x38 */
91 …__O uint32_t SWDATAHE; /**< Slave Write Data Half-word End, offset: 0x3C…
117 __O uint32_t MWDATAB; /**< Master Write Data Byte, offset: 0xB0 */
118 __O uint32_t MWDATABE; /**< Master Write Data Byte End, offset: 0xB4 */
119 __O uint32_t MWDATAH; /**< Master Write Data Half-word, offset: 0xB8 */
120 __O uint32_t MWDATAHE; /**< Master Write Data Byte End, offset: 0xBC */
124 …__O uint32_t MWDATAB1; /**< Byte-only Write Byte Data (to bus), offset: …
126 …__O uint32_t MWMSG_SDR_CONTROL; /**< Master Write Message in SDR mode, offset: 0x…
[all …]
DS32Z2_DMSS_SAFETY.h77 …__O uint32_t D_UCSERR_S; /**< DMSS UCS ERR Shadow Register, offset: 0x10 */
78 __O uint32_t D_CSERR_S; /**< DMSS CS ERR Shadow Register, offset: 0x14 */
DS32Z2_ACE.h73 __O uint64_t INIT_VEC; /**< , offset: 0x0 */
74 __O uint64_t DATA_IN; /**< , offset: 0x8 */
DS32Z2_RTUP_NIC_B.h73 __O uint32_t REMAP; /**< Remap, offset: 0x0 */
DS32Z2_RTUF_NIC_D.h73 __O uint32_t REMAP; /**< Remap, offset: 0x0 */
DS32Z2_RTUM_NIC_D.h73 __O uint32_t REMAP; /**< Remap, offset: 0x0 */
DS32Z2_RTUE_NIC_D.h73 __O uint32_t REMAP; /**< Remap, offset: 0x0 */
DS32Z2_PMSS_SAFETY.h77 …__O uint32_t P_UCSERR_S; /**< PMSS UCS ERR Shadow Register, offset: 0x10 */
78 __O uint32_t P_CSERR_S; /**< PMSS CE ERR Shadow Register, offset: 0x14 */
DS32Z2_CORE_SAFETY.h74 __O uint32_t C_UCPERR_S; /**< Core UCP ERR Shadow Register, offset: 0x4 */
DS32Z2_CE_SEMA42.h80 __O uint16_t W; /**< Reset Gate Write, offset: 0x42 */
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h1047 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1048 …__O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1051 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1052 …__O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 …
1177 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1757 …__O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., …
1767 …__O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels.…
1773 …__O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA ch…
1775 …__O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channel…
1777 …__O uint32_t ABORT; /**< Channel Abort control for all DMA channels.,…
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/CMSIS/Include/
Dcore_dsp.h47 #define __O volatile /*!< Defines 'write only' permissions */ macro
/hal_nxp-3.5.0/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dcmsis_compiler.h79 #define __O volatile /*!< Defines 'write only' permissions */ macro
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h993 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
994 …__O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
997 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
998 …__O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 …
1133 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1721 …__O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., …
1731 …__O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels.…
1737 …__O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA ch…
1739 …__O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channel…
1741 …__O uint32_t ABORT; /**< Channel Abort control for all DMA channels.,…
[all …]
DLPC54114_cm4.h1004 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1005 …__O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1008 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1009 …__O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 …
1144 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1732 …__O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., …
1742 …__O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels.…
1748 …__O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA ch…
1750 …__O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channel…
1752 …__O uint32_t ABORT; /**< Channel Abort control for all DMA channels.,…
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h1005 __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
1006 …__O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
1009 __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
1010 …__O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 …
1145 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1733 …__O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., …
1743 …__O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels.…
1749 …__O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA ch…
1751 …__O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channel…
1753 …__O uint32_t ABORT; /**< Channel Abort control for all DMA channels.,…
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h295 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
6191 …__O uint32_t START; /**< Write address for issuing the START command.…
6192 …__O uint32_t STOP; /**< Write address for issuing the STOP command.,…
6193 …__O uint32_t RESTART; /**< Write address for issuing the RESTART comman…
6194 …__O uint32_t ADD; /**< Write address for issuing the ADD command., …
6195 …__O uint32_t ADD1; /**< Write address for issuing the ADD1 command.,…
6196 …__O uint32_t ADD16; /**< Write address for issuing the ADD16 command.…
6197 …__O uint32_t ADD256; /**< Write address for issuing the ADD16 command.…
6198 …__O uint32_t SUB; /**< Write address for issuing the SUB command., …
6199 …__O uint32_t SUB1; /**< Write address for issuing the SUB1 command.,…
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h295 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
6191 …__O uint32_t START; /**< Write address for issuing the START command.…
6192 …__O uint32_t STOP; /**< Write address for issuing the STOP command.,…
6193 …__O uint32_t RESTART; /**< Write address for issuing the RESTART comman…
6194 …__O uint32_t ADD; /**< Write address for issuing the ADD command., …
6195 …__O uint32_t ADD1; /**< Write address for issuing the ADD1 command.,…
6196 …__O uint32_t ADD16; /**< Write address for issuing the ADD16 command.…
6197 …__O uint32_t ADD256; /**< Write address for issuing the ADD16 command.…
6198 …__O uint32_t SUB; /**< Write address for issuing the SUB command., …
6199 …__O uint32_t SUB1; /**< Write address for issuing the SUB1 command.,…
[all …]

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