1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_WM8962_H_ 9 #define _FSL_WM8962_H_ 10 11 #include "fsl_codec_i2c.h" 12 #include "fsl_common.h" 13 14 /*! 15 * @addtogroup wm8962 16 * @ingroup codec 17 * @{ 18 */ 19 20 /******************************************************************************* 21 * Definitions 22 ******************************************************************************/ 23 /*! @name Driver version */ 24 /*@{*/ 25 /*! @brief CLOCK driver version 2.1.0 */ 26 #define FSL_WM8962_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) 27 /*@}*/ 28 29 /*! @brief wm8962 handle size */ 30 #ifndef WM8962_I2C_HANDLER_SIZE 31 #define WM8962_I2C_HANDLER_SIZE CODEC_I2C_MASTER_HANDLER_SIZE 32 #endif 33 34 #define DEBUG_WM8962_REGISTER 0 35 #if DEBUG_WM8962_REGISTER 36 #include "fsl_debug_console.h" 37 #endif 38 39 /*! @brief Define the register address of WM8962. */ 40 #define WM8962_LINVOL 0x0U 41 #define WM8962_RINVOL 0x1U 42 #define WM8962_LOUT1 0x2U 43 #define WM8962_ROUT1 0x3U 44 #define WM8962_CLOCK1 0x4U 45 #define WM8962_DACCTL1 0x5U 46 #define WM8962_DACCTL2 0x6U 47 #define WM8962_IFACE0 0x7U 48 #define WM8962_IFACE1 0x9U 49 #define WM8962_CLOCK2 0x8U 50 #define WM8962_IFACE2 0xEU 51 #define WM8962_LDAC 0xaU 52 #define WM8962_RDAC 0xbU 53 54 #define WM8962_RESET 0xfU 55 #define WM8962_3D 0x10U 56 #define WM8962_ALC1 0x11U 57 #define WM8962_ALC2 0x12U 58 #define WM8962_ALC3 0x13U 59 #define WM8962_NOISEG 0x14U 60 #define WM8962_LADC 0x15U 61 #define WM8962_RADC 0x16U 62 #define WM8962_ADDCTL1 0x17U 63 #define WM8962_ADDCTL2 0x18U 64 #define WM8962_POWER1 0x19U 65 #define WM8962_POWER2 0x1aU 66 #define WM8962_ADDCTL3 0x1bU 67 #define WM8962_APOP1 0x1cU 68 #define WM8962_APOP2 0x1dU 69 #define WM8962_INPUT_MIXER_1 0x1FU 70 71 #define WM8962_LINPATH 0x20U 72 #define WM8962_RINPATH 0x21U 73 #define WM8962_INPUTMIX 0x22U 74 75 #define WM8962_LEFT_INPUT_PGA 0x25U 76 #define WM8962_RIGHT_INPUT_PGA 0x26U 77 #define WM8962_MONOMIX2 0x27U 78 #define WM8962_LOUT2 0x28U 79 #define WM8962_ROUT2 0x29U 80 #define WM8962_TEMP 0x2FU 81 #define WM8962_ADDCTL4 0x30U 82 #define WM8962_CLASSD1 0x31U 83 84 #define WM8962_CLASSD3 0x33U 85 #define WM8962_PLL1 0x34U 86 #define WM8962_PLL2 0x35U 87 #define WM8962_PLL3 0x36U 88 #define WM8962_PLL4 0x37U 89 #define WM8962_CLK4 0x38U 90 #define WM8962_DC_SERVO_0 0x3CU 91 #define WM8962_DC_SERVO_1 0x3DU 92 #define WM8962_ANALOG_HP_0 0x45U 93 #define WM8962_CHARGE_PUMP_1 0x48U 94 95 #define WM8962_LEFT_HEADPHONE_MIXER 0x64U 96 #define WM8962_RIGHT_HEADPHONE_MIXER 0x65U 97 #define WM8962_LEFT_HEADPHONE_MIXER_VOLUME 0x66U 98 #define WM8962_RIGHT_HEADPHONE_MIXER_VOLUME 0x67U 99 100 #define WM8962_LEFT_SPEAKER_MIXER 0x69U 101 #define WM8962_RIGHT_SPEAKER_MIXER 0x6AU 102 #define WM8962_LEFT_SPEAKER_MIXER_VOLUME 0x6BU 103 #define WM8962_RIGHT_SPEAKER_MIXER_VOLUME 0x6CU 104 105 #define WM8962_FLL_CTRL_1 0x9BU 106 #define WM8962_FLL_CTRL_2 0x9CU 107 #define WM8962_FLL_CTRL_3 0x9DU 108 #define WM8962_FLL_CTRL_6 0xA0U 109 #define WM8962_FLL_CTRL_7 0xA1U 110 #define WM8962_FLL_CTRL_8 0xA2U 111 #define WM8962_INT_STATUS_2 0x231U 112 /*! @brief Cache register number */ 113 #define WM8962_CACHEREGNUM 56U 114 115 /*! @brief WM8962 CLOCK2 bits */ 116 #define WM8962_CLOCK2_BCLK_DIV_MASK 0xFU 117 118 /*! @brief WM8962_IFACE0 FORMAT bits */ 119 #define WM8962_IFACE0_FORMAT_MASK 0x13U 120 #define WM8962_IFACE0_FORMAT_SHIFT 0x00U 121 #define WM8962_IFACE0_FORMAT_RJ 0x00U 122 #define WM8962_IFACE0_FORMAT_LJ 0x01U 123 #define WM8962_IFACE0_FORMAT_I2S 0x02U 124 #define WM8962_IFACE0_FORMAT_DSP 0x03U 125 #define WM8962_IFACE0_FORMAT(x) (((x) << WM8962_IFACE1_FORMAT_SHIFT) & WM8962_IFACE1_FORMAT_MASK) 126 127 /*! @brief WM8962_IFACE0 WL bits */ 128 #define WM8962_IFACE0_WL_MASK 0x0CU 129 #define WM8962_IFACE0_WL_SHIFT 0x02U 130 #define WM8962_IFACE0_WL_16BITS 0x00U 131 #define WM8962_IFACE0_WL_20BITS 0x01U 132 #define WM8962_IFACE0_WL_24BITS 0x02U 133 #define WM8962_IFACE0_WL_32BITS 0x03U 134 #define WM8962_IFACE0_WL(x) (((x) << WM8962_IFACE0_WL_SHIFT) & WM8962_IFACE0_WL_MASK) 135 136 /*! @brief WM8962_IFACE1 LRP bit */ 137 #define WM8962_IFACE1_LRP_MASK 0x10U 138 #define WM8962_IFACE1_LRP_SHIFT 0x04U 139 #define WM8962_IFACE1_LRCLK_NORMAL_POL 0x00U 140 #define WM8962_IFACE1_LRCLK_INVERT_POL 0x01U 141 #define WM8962_IFACE1_DSP_MODEA 0x00U 142 #define WM8962_IFACE1_DSP_MODEB 0x01U 143 #define WM8962_IFACE1_LRP(x) (((x) << WM8962_IFACE1_LRP_SHIFT) & WM8962_IFACE1_LRP_MASK) 144 145 /*! @brief WM8962_IFACE1 DLRSWAP bit */ 146 #define WM8962_IFACE1_DLRSWAP_MASK 0x20U 147 #define WM8962_IFACE1_DLRSWAP_SHIFT 0x05U 148 #define WM8962_IFACE1_DACCH_NORMAL 0x00U 149 #define WM8962_IFACE1_DACCH_SWAP 0x01U 150 #define WM8962_IFACE1_DLRSWAP(x) (((x) << WM8962_IFACE1_DLRSWAP_SHIFT) & WM8962_IFACE1_DLRSWAP_MASK) 151 152 /*! @brief WM8962_IFACE1 MS bit */ 153 #define WM8962_IFACE1_MS_MASK 0x40U 154 #define WM8962_IFACE1_MS_SHIFT 0x06U 155 #define WM8962_IFACE1_SLAVE 0x00U 156 #define WM8962_IFACE1_MASTER 0x01U 157 #define WM8962_IFACE1_MS(x) (((x) << WM8962_IFACE1_MS_SHIFT) & WM8962_IFACE1_MS_MASK) 158 159 /*! @brief WM8962_IFACE1 BCLKINV bit */ 160 #define WM8962_IFACE1_BCLKINV_MASK 0x80U 161 #define WM8962_IFACE1_BCLKINV_SHIFT 0x07U 162 #define WM8962_IFACE1_BCLK_NONINVERT 0x00U 163 #define WM8962_IFACE1_BCLK_INVERT 0x01U 164 #define WM8962_IFACE1_BCLKINV(x) (((x) << WM8962_IFACE1_BCLKINV_SHIFT) & WM8962_IFACE1_BCLKINV_MASK) 165 166 /*! @brief WM8962_IFACE1 ALRSWAP bit */ 167 #define WM8962_IFACE1_ALRSWAP_MASK 0x100U 168 #define WM8962_IFACE1_ALRSWAP_SHIFT 0x08U 169 #define WM8962_IFACE1_ADCCH_NORMAL 0x00U 170 #define WM8962_IFACE1_ADCCH_SWAP 0x01U 171 #define WM8962_IFACE1_ALRSWAP(x) (((x) << WM8962_IFACE1_ALRSWAP_SHIFT) & WM8962_IFACE1_ALRSWAP_MASK) 172 173 /*! @brief WM8962_POWER1 */ 174 #define WM8962_POWER1_VREF_MASK 0x40U 175 #define WM8962_POWER1_VREF_SHIFT 0x06U 176 177 #define WM8962_POWER1_AINL_MASK 0x20U 178 #define WM8962_POWER1_AINL_SHIFT 0x05U 179 180 #define WM8962_POWER1_AINR_MASK 0x10U 181 #define WM8962_POWER1_AINR_SHIFT 0x04U 182 183 #define WM8962_POWER1_ADCL_MASK 0x08U 184 #define WM8962_POWER1_ADCL_SHIFT 0x03U 185 186 #define WM8962_POWER1_ADCR_MASK 0x4U 187 #define WM8962_POWER1_ADCR_SHIFT 0x02U 188 189 #define WM8962_POWER1_MICB_MASK 0x02U 190 #define WM8962_POWER1_MICB_SHIFT 0x01U 191 192 #define WM8962_POWER1_DIGENB_MASK 0x01U 193 #define WM8962_POWER1_DIGENB_SHIFT 0x00U 194 195 /*! @brief WM8962_POWER2 */ 196 #define WM8962_POWER2_DACL_MASK 0x100U 197 #define WM8962_POWER2_DACL_SHIFT 0x08U 198 199 #define WM8962_POWER2_DACR_MASK 0x80U 200 #define WM8962_POWER2_DACR_SHIFT 0x07U 201 202 #define WM8962_POWER2_LOUT1_MASK 0x40U 203 #define WM8962_POWER2_LOUT1_SHIFT 0x06U 204 205 #define WM8962_POWER2_ROUT1_MASK 0x20U 206 #define WM8962_POWER2_ROUT1_SHIFT 0x05U 207 208 #define WM8962_POWER2_SPKL_MASK 0x10U 209 #define WM8962_POWER2_SPKL_SHIFT 0x04U 210 211 #define WM8962_POWER2_SPKR_MASK 0x08U 212 #define WM8962_POWER2_SPKR_SHIFT 0x03U 213 214 #define WM8962_POWER3_LMIC_MASK 0x20U 215 #define WM8962_POWER3_LMIC_SHIFT 0x05U 216 #define WM8962_POWER3_RMIC_MASK 0x10U 217 #define WM8962_POWER3_RMIC_SHIFT 0x04U 218 #define WM8962_POWER3_LOMIX_MASK 0x08U 219 #define WM8962_POWER3_LOMIX_SHIFT 0x03U 220 #define WM8962_POWER3_ROMIX_MASK 0x04U 221 #define WM8962_POWER3_ROMIX_SHIFT 0x02U 222 /*! @brief WM8962 I2C address. */ 223 #define WM8962_I2C_ADDR (0x34 >> 1U) 224 /*! @brief WM8962 I2C baudrate */ 225 #define WM8962_I2C_BAUDRATE (100000U) 226 /*! @brief WM8962 maximum volume value */ 227 #define WM8962_ADC_MAX_VOLUME_vALUE 0xFFU 228 #define WM8962_DAC_MAX_VOLUME_vALUE 0xFFU 229 #define WM8962_HEADPHONE_MAX_VOLUME_vALUE 0x7FU 230 #define WM8962_HEADPHONE_MIN_VOLUME_vALUE 0x30U 231 #define WM8962_LINEIN_MAX_VOLUME_vALUE 0x3FU 232 #define WM8962_SPEAKER_MAX_VOLUME_vALUE 0x7FU 233 #define WM8962_SPEAKER_MIN_VOLUME_vALUE 0x30U 234 235 /*! @brief wm8962 input mixer source. 236 * @anchor wm8962_input_mixer_source_t 237 */ 238 enum 239 { 240 kWM8962_InputMixerSourceInput2 = 4U, /*!< input mixer source input 2 */ 241 kWM8962_InputMixerSourceInput3 = 2U, /*!< input mixer source input 3 */ 242 kWM8962_InputMixerSourceInputPGA = 1U, /*!< input mixer source input PGA */ 243 }; 244 245 /*! @brief wm8962 output mixer source. 246 * @anchor wm8962_output_mixer_source_t 247 */ 248 enum 249 { 250 kWM8962_OutputMixerDisabled = 0U, /*!< output mixer disabled */ 251 kWM8962_OutputMixerSourceInput4Right = 1U, /*!< output mixer source input 4 left */ 252 kWM8962_OutputMixerSourceInput4Left = 2U, /*!< output mixer source input 4 right */ 253 kWM8962_OutputMixerSourceRightInputMixer = 4U, /*!< output mixer source left input mixer */ 254 kWM8962_OutputMixerSourceLeftInputMixer = 8U, /*!< output mixer source right input mixer*/ 255 kWM8962_OutputMixerSourceRightDAC = 0x10U, /*!< output mixer source left DAC */ 256 kWM8962_OutputMixerSourceLeftDAC = 0x20U, /*!< output mixer source Right DAC */ 257 }; 258 259 /*! @brief Modules in WM8962 board. */ 260 typedef enum _wm8962_module 261 { 262 kWM8962_ModuleADC = 0, /*!< ADC module in WM8962 */ 263 kWM8962_ModuleDAC = 1, /*!< DAC module in WM8962 */ 264 kWM8962_ModuleMICB = 4, /*!< Mic bias */ 265 kWM8962_ModuleMIC = 5, /*!< Input Mic */ 266 kWM8962_ModuleLineIn = 6, /*!< Analog in PGA */ 267 kWM8962_ModuleHeadphone = 7, /*!< Line out module */ 268 kWM8962_ModuleSpeaker = 8, /*!< Speaker module */ 269 kWM8962_ModuleHeaphoneMixer = 9, /*!< Output mixer */ 270 kWM8962_ModuleSpeakerMixer = 10, /*!< Output mixer */ 271 } wm8962_module_t; 272 273 /*! @brief wm8962 play channel 274 * @anchor _wm8962_play_channel 275 */ 276 enum 277 { 278 kWM8962_HeadphoneLeft = 1, /*!< wm8962 headphone left channel */ 279 kWM8962_HeadphoneRight = 2, /*!< wm8962 headphone right channel */ 280 kWM8962_SpeakerLeft = 4, /*!< wm8962 speaker left channel */ 281 kWM8962_SpeakerRight = 8, /*!< wm8962 speaker right channel */ 282 }; 283 284 /*! 285 * @brief The audio data transfer protocol choice. 286 * WM8962 only supports I2S format and PCM format. 287 */ 288 typedef enum _wm8962_protocol 289 { 290 kWM8962_BusPCMA = 4, /*!< PCMA mode */ 291 kWM8962_BusPCMB = 3, /*!< PCMB mode */ 292 kWM8962_BusI2S = 2, /*!< I2S type */ 293 kWM8962_BusLeftJustified = 1, /*!< Left justified mode */ 294 kWM8962_BusRightJustified = 0, /*!< Right justified mode */ 295 } wm8962_protocol_t; 296 297 /*! @brief wm8962 input source */ 298 typedef enum _wm8962_input_pga_source 299 { 300 kWM8962_InputPGASourceInput1 = 8, /*!< Input PGA source input1 */ 301 kWM8962_InputPGASourceInput2 = 4, /*!< Input PGA source input2 */ 302 kWM8962_InputPGASourceInput3 = 2, /*!< Input PGA source input3 */ 303 kWM8962_InputPGASourceInput4 = 1, /*!< Input PGA source input4 */ 304 } wm8962_input_pga_source_t; 305 306 /*! @brief wm8962 input source */ 307 typedef enum _wm8962_output_pga_source 308 { 309 kWM8962_OutputPGASourceMixer = 0, /*!< Output PGA source mixer */ 310 kWM8962_OutputPGASourceDAC = 1, /*!< Output PGA source DAC */ 311 } wm8962_output_pga_source_t; 312 313 /*! @brief audio sample rate definition 314 * @anchor _wm8962_sample_rate 315 */ 316 enum 317 { 318 kWM8962_AudioSampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ 319 kWM8962_AudioSampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ 320 kWM8962_AudioSampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ 321 kWM8962_AudioSampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ 322 kWM8962_AudioSampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ 323 kWM8962_AudioSampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ 324 kWM8962_AudioSampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ 325 kWM8962_AudioSampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ 326 kWM8962_AudioSampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ 327 kWM8962_AudioSampleRate88200Hz = 88200U, /*!< Sample rate 88200 Hz */ 328 kWM8962_AudioSampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ 329 }; 330 331 /*! @brief audio bit width 332 * @anchor _wm8962_audio_bit_width 333 */ 334 enum 335 { 336 kWM8962_AudioBitWidth16bit = 16U, /*!< audio bit width 16 */ 337 kWM8962_AudioBitWidth20bit = 20U, /*!< audio bit width 20 */ 338 kWM8962_AudioBitWidth24bit = 24U, /*!< audio bit width 24 */ 339 kWM8962_AudioBitWidth32bit = 32U, /*!< audio bit width 32 */ 340 }; 341 342 /*! @brief wm8962 fll clock source */ 343 typedef enum _wm8962_fllclk_source 344 { 345 kWM8962_FLLClkSourceMCLK = 0U, /*!< FLL clock source from MCLK */ 346 kWM8962_FLLClkSourceBCLK = 1U, /*!< FLL clock source from BCLK */ 347 } wm8962_fllclk_source_t; 348 349 /*! @brief wm8962 sysclk source */ 350 typedef enum _wm8962_sysclk_source 351 { 352 kWM8962_SysClkSourceMclk = 0U, /*!< sysclk source from external MCLK */ 353 kWM8962_SysClkSourceFLL = 1U, /*!< sysclk source from internal FLL */ 354 } wm8962_sysclk_source_t; 355 356 /*! @brief wm8962 audio format */ 357 typedef struct _wm8962_audio_format 358 { 359 uint32_t mclk_HZ; /*!< master clock frequency */ 360 uint32_t sampleRate; /*!< sample rate */ 361 uint32_t bitWidth; /*!< bit width */ 362 } wm8962_audio_format_t; 363 364 /*! @brief wm8962 master system clock configuration */ 365 typedef struct _wm8962_fll_clk_config 366 { 367 wm8962_fllclk_source_t fllClockSource; /*!< fll clock source */ 368 uint32_t fllReferenceClockFreq; /*!< external input frequency */ 369 uint32_t fllOutputFreq; /*!< FLL output frequency value */ 370 } wm8962_fll_clk_config_t; 371 372 /*! 373 * @brief WM8962 data route configurations 374 */ 375 typedef struct _wm8962_route_config 376 { 377 bool enableLoopBack; /*!< enable loopback: ADC->DAC directly*/ 378 379 /* adc input come from input mixer, input mixer source from: input PGA OR external input */ 380 wm8962_input_pga_source_t leftInputPGASource; /*!< Left input source for WM8962 */ 381 uint32_t leftInputMixerSource; /*!< left input MIXER source, combination value of wm8962_input_mixer_source_t */ 382 383 wm8962_input_pga_source_t rightInputPGASource; /*!< right input PGA source */ 384 uint32_t rightInputMixerSource; /*!< right input MIXER source, combination value of wm8962_input_mixer_source_t */ 385 386 /* headphone/speaker source from output PGA, output PGA source from mixer OR DAC */ 387 uint32_t 388 leftSpeakerMixerSource; /*!< speaker left MIXER source, combination value of wm8962_output_mixer_source_t */ 389 wm8962_output_pga_source_t leftSpeakerPGASource; /*!< speaker left PGA source */ 390 391 uint32_t 392 rightSpeakerMixerSource; /*!< speaker right MIXER source, combination value of wm8962_output_mixer_source_t */ 393 wm8962_output_pga_source_t rightSpeakerPGASource; /*!< speaker left PGA source */ 394 395 uint32_t 396 leftHeadphoneMixerSource; /*!< headphone left MIXER source, combination value of wm8962_output_mixer_source_t */ 397 wm8962_output_pga_source_t leftHeadphonePGASource; /*!< speaker left PGA source */ 398 399 uint32_t rightHeadphoneMixerSource; /*!< headphone left MIXER source, combination value of 400 wm8962_output_mixer_source_t */ 401 wm8962_output_pga_source_t rightHeadphonePGASource; /*!< speaker left PGA source */ 402 } wm8962_route_config_t; 403 404 /*! @brief Initialize structure of WM8962 */ 405 typedef struct wm8962_config 406 { 407 wm8962_route_config_t route; /*!< Audio data route.*/ 408 409 wm8962_protocol_t bus; /*!< Audio transfer protocol */ 410 wm8962_audio_format_t format; /*!< Audio format */ 411 412 bool masterSlave; /*!< Master or slave. true: master mode, false: slave mode */ 413 wm8962_sysclk_source_t sysclkSource; /*!< sysclk source */ 414 wm8962_fll_clk_config_t fllClock; /*!< FLL clock configurations, shall be configured when masterSlave is true */ 415 416 uint8_t slaveAddress; /*!< wm8962 device address */ 417 codec_i2c_config_t i2cConfig; /*!< i2c configuration */ 418 } wm8962_config_t; 419 420 /*! @brief wm8962 codec handler 421 */ 422 typedef struct _wm8962_handle 423 { 424 const wm8962_config_t *config; /*!< wm8904 config pointer */ 425 uint8_t i2cHandle[WM8962_I2C_HANDLER_SIZE]; /*!< i2c handle */ 426 } wm8962_handle_t; 427 /******************************************************************************* 428 * API 429 ******************************************************************************/ 430 #if defined(__cplusplus) 431 extern "C" { 432 #endif 433 434 /*! 435 * @brief WM8962 initialize function. 436 * 437 * The second parameter is NULL to WM8962 in this version. If users want 438 * to change the settings, they have to use wm8962_write_reg() or wm8962_modify_reg() 439 * to set the register value of WM8962. 440 * Note: If the codec_config is NULL, it would initialize WM8962 using default settings. 441 * The default setting: 442 * codec_config->route = kWM8962_RoutePlaybackandRecord 443 * codec_config->bus = kWM8962_BusI2S 444 * codec_config->master = slave 445 * 446 * @param handle WM8962 handle structure. 447 * @param config WM8962 configuration structure. 448 */ 449 status_t WM8962_Init(wm8962_handle_t *handle, const wm8962_config_t *config); 450 451 /*! 452 * @brief Deinit the WM8962 codec. 453 * 454 * This function close all modules in WM8962 to save power. 455 * 456 * @param handle WM8962 handle structure pointer. 457 */ 458 status_t WM8962_Deinit(wm8962_handle_t *handle); 459 460 /*! 461 * @brief Set audio data route in WM8962. 462 * 463 * This function would set the data route according to route. The route cannot be combined, 464 * as all route would enable different modules. 465 * Note: If a new route is set, the previous route would not work. 466 * 467 * @param handle WM8962 handle structure. 468 * @param route Audio data route in WM8962. 469 */ 470 status_t WM8962_SetDataRoute(wm8962_handle_t *handle, const wm8962_route_config_t *route); 471 472 /*! 473 * @brief Set the audio transfer protocol. 474 * 475 * WM8960 only supports I2S, left justified, right justified, PCM A, PCM B format. 476 * 477 * @param handle WM8960 handle structure. 478 * @param protocol Audio data transfer protocol. 479 */ 480 status_t WM8962_SetProtocol(wm8962_handle_t *handle, wm8962_protocol_t protocol); 481 482 /*! 483 * @brief Set the volume of different modules in WM8962. 484 * 485 * This function would set the volume of WM8962 modules. Uses need to appoint the module. 486 * The function assume that left channel and right channel has the same volume. 487 * 488 * Module:kWM8962_ModuleADC, volume range value: 0 is mute, 1-255 is -97db to 30db 489 * Module:kWM8962_ModuleDAC, volume range value: 0 is mute, 1-255 is -127db to 0db 490 * Module:kWM8962_ModuleHP, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db 491 * Module:kWM8962_ModuleLineIn, volume range value: 0 - 0x3F is -17.25db to 30db 492 * Module:kWM8962_ModuleSpeaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db 493 * 494 * 495 * @param handle WM8962 handle structure. 496 * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. 497 * @param volume Volume value need to be set. 498 */ 499 status_t WM8962_SetModuleVolume(wm8962_handle_t *handle, wm8962_module_t module, uint32_t volume); 500 501 /*! 502 * @brief Get the volume of different modules in WM8962. 503 * 504 * This function gets the volume of WM8962 modules. Uses need to appoint the module. 505 * The function assume that left channel and right channel has the same volume. 506 * 507 * @param handle WM8962 handle structure. 508 * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. 509 * @return Volume value of the module. 510 */ 511 uint32_t WM8962_GetModuleVolume(wm8962_handle_t *handle, wm8962_module_t module); 512 513 /*! 514 * @brief Mute modules in WM8962. 515 * 516 * @param handle WM8962 handle structure. 517 * @param module Modules need to be mute. 518 * @param isEnabled Mute or unmute, 1 represent mute. 519 */ 520 status_t WM8962_SetModuleMute(wm8962_handle_t *handle, wm8962_module_t module, bool isEnabled); 521 522 /*! 523 * @brief Enable/disable expected devices. 524 * 525 * @param handle WM8962 handle structure. 526 * @param module Module expected to enable. 527 * @param isEnabled Enable or disable moudles. 528 */ 529 status_t WM8962_SetModulePower(wm8962_handle_t *handle, wm8962_module_t module, bool isEnabled); 530 531 /*! 532 * @brief Configure the data format of audio data. 533 * 534 * This function would configure the registers about the sample rate, bit depths. 535 * 536 * @param handle WM8962 handle structure pointer. 537 * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. 538 * @param sample_rate Sample rate of audio file running in WM8962. WM8962 now 539 * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. 540 * @param bits Bit depth of audio file (WM8962 only supports 16bit, 20bit, 24bit 541 * and 32 bit in HW). 542 */ 543 status_t WM8962_ConfigDataFormat(wm8962_handle_t *handle, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); 544 545 /*! 546 * @brief Write register to WM8962 using I2C. 547 * 548 * @param handle WM8962 handle structure. 549 * @param reg The register address in WM8962. 550 * @param val Value needs to write into the register. 551 */ 552 status_t WM8962_WriteReg(wm8962_handle_t *handle, uint16_t reg, uint16_t val); 553 554 /*! 555 * @brief Read register from WM8962 using I2C. 556 * @param reg The register address in WM8962. 557 * @param val Value written to. 558 */ 559 status_t WM8962_ReadReg(wm8962_handle_t *handle, uint16_t reg, uint16_t *val); 560 561 /*! 562 * @brief Modify some bits in the register using I2C. 563 * @param handle WM8962 handle structure. 564 * @param reg The register address in WM8962. 565 * @param mask The mask code for the bits want to write. The bit you want to write should be 0. 566 * @param val Value needs to write into the register. 567 */ 568 status_t WM8962_ModifyReg(wm8962_handle_t *handle, uint16_t reg, uint16_t mask, uint16_t val); 569 570 #if DEBUG_WM8962_REGISTER 571 /*! 572 * @brief Dump all the wm8962 register. 573 574 * @param handle WM8962 handle structure. 575 * @param endAddress The end register address in WM8962. 576 */ 577 void WM8962_ReadAllReg(wm8962_handle_t *handle, uint32_t endAddress); 578 #endif 579 #if defined(__cplusplus) 580 } 581 #endif 582 583 /*! @} */ 584 585 #endif /* _FSL_WM8962_H_ */ 586 587 /******************************************************************************* 588 * API 589 ******************************************************************************/ 590
