Home
last modified time | relevance | path

Searched refs:TRUE (Results 1 – 25 of 60) sorted by relevance

123

/hal_nxp-3.5.0/s32/soc/s32z27/include/
DLinflexd_Uart_Ip_Defines.h77 …TRUE, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE, (b…
DPlatformTypes.h142 #ifndef TRUE
148 #define TRUE true macro
154 #define TRUE 1
/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip_Irq.c231 ((EMIOS_PWM_IP_ACTIVE_LOW == Polarity) && (TRUE == OutputPin))) in Emios_Pwm_Ip_IrqDaocHandler()
265 ((TRUE == Emios_Pwm_Ip_GetOverRunFlag(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) || in Emios_Pwm_Ip_IrqHandler()
266 (TRUE == Emios_Pwm_Ip_GetOverFlagEvent(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) || in Emios_Pwm_Ip_IrqHandler()
267 (TRUE == Emios_Pwm_Ip_GetOverFlowFlag(Emios_Pwm_Ip_aBasePtr[Instance], Channel)))) in Emios_Pwm_Ip_IrqHandler()
275 if ((TRUE == Emios_Pwm_Ip_GetInterruptRequest(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) && in Emios_Pwm_Ip_IrqHandler()
276 ((TRUE == Emios_Pwm_Ip_GetOverRunFlag(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) || in Emios_Pwm_Ip_IrqHandler()
277 (TRUE == Emios_Pwm_Ip_GetOverFlagEvent(Emios_Pwm_Ip_aBasePtr[Instance], Channel)) || in Emios_Pwm_Ip_IrqHandler()
278 (TRUE == Emios_Pwm_Ip_GetOverFlowFlag(Emios_Pwm_Ip_aBasePtr[Instance], Channel)))) in Emios_Pwm_Ip_IrqHandler()
DEmios_Pwm_Ip.c242 … (((Emios_Pwm_Ip_aChannelModes[Instance][(uint8)Mode] >> Channel) & 0x01UL) == 1UL) ? TRUE : FALSE; in Emios_Pwm_Ip_ValidateMode()
337 …DevAssert(TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_O… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
404 …DevAssert(TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_O… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmMode()
512 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
596 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
648 …DevAssert((TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_… in Emios_Pwm_Ip_InitDeadTimeMode()
649 … (TRUE == Emios_Pwm_Ip_ValidateMode(Instance, UserChCfg->ChannelId, EMIOS_PWM_IP_HW_MODE_OPWMC))); in Emios_Pwm_Ip_InitDeadTimeMode()
751 Emios_Pwm_Ip_SetForceMatchB(Base, Channel, TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwmcb()
755 Emios_Pwm_Ip_SetForceMatchA(Base, Channel, TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwmcb()
772 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwmcb()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Specific.c221 if (TRUE == TimeoutOccurred) in Clock_Ip_PllPowerClockIp()
245 if (TRUE == TimeoutOccurred) in Clock_Ip_PllPowerClockIp()
281 if (TRUE == TimeoutOccurred) in Clock_Ip_PowerClockIpModules()
305 if (TRUE == TimeoutOccurred) in Clock_Ip_PowerClockIpModules()
329 if (TRUE == TimeoutOccurred) in Clock_Ip_PowerClockIpModules()
352 if (TRUE == TimeoutOccurred) in Clock_Ip_PowerClockIpModules()
508 FircConfig.Enable = TRUE; in EnableFircInStandbyMode()
522 SircConfig.Enable = TRUE; in EnableSircInStandbyMode()
531 Clock_Ip_bObjectsAreInitialized = TRUE; in Clock_Ip_ClockInitializeObjects()
DPower_Ip_MC_ME.c551 if ( TRUE == TempPartitionConfig->PartitionUnderMcuControl ) in Power_Ip_MC_ME_ConfigCoreCOFBClock()
557 … if ( TRUE == (*TempPartitionConfig->ArrayPartitionCofbConfigPtr)[CofbIndex].CofbUnderMcuControl ) in Power_Ip_MC_ME_ConfigCoreCOFBClock()
566 … if ( TRUE == (*TempPartitionConfig->ArrayPartitionCoreConfigPtr)[CoreIndex].CoreUnderMcuControl ) in Power_Ip_MC_ME_ConfigCoreCOFBClock()
594 if ( TRUE == TempPartitionConfig->PartitionUnderMcuControl ) in Power_Ip_MC_ME_EnablePartitionClock()
596 if ( TRUE == TempPartitionConfig->PartitionPowerUnderMcuControl ) in Power_Ip_MC_ME_EnablePartitionClock()
635 if ( TRUE == TempPartitionConfig->PartitionUnderMcuControl ) in Power_Ip_MC_ME_DisablePartitionClock()
637 if ( TRUE == TempPartitionConfig->PartitionPowerUnderMcuControl ) in Power_Ip_MC_ME_DisablePartitionClock()
DClock_Ip_Gate.c178 if (TRUE == TimeoutOccurred) in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
208 if (TRUE == TimeoutOccurred) in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
234 if (TRUE == Gate) in Clock_Ip_ClockUpdateGateMcMePartitionCollectionClockRequest()
/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c274 if ((TRUE == UartState->IsTxBusy) || (TRUE == UartState->IsRxBusy)) in Linflexd_Uart_Ip_SetBaudrate()
308 IsReturn = TRUE; in Linflexd_Uart_Ip_SetBaudrate()
312 ResetIdle = TRUE; in Linflexd_Uart_Ip_SetBaudrate()
321 if (TRUE == ResetIdle) in Linflexd_Uart_Ip_SetBaudrate()
407 UartStatePtr->IsDriverInitialized = TRUE; in Linflexd_Uart_Ip_Init()
754 UartState->IsTxBusy = TRUE; in Linflexd_Uart_Ip_SyncSend()
772 Linflexd_Uart_Ip_SetTransmitterState(Base, TRUE); in Linflexd_Uart_Ip_SyncSend()
892 UartState->IsRxBusy = TRUE; in Linflexd_Uart_Ip_SyncReceive()
1067 UartState->IsRxBusy = TRUE; in Linflexd_Uart_Ip_StartReceiveUsingInterrupts()
1081 Linflexd_Uart_Ip_SetReceiverState(Base, TRUE); in Linflexd_Uart_Ip_StartReceiveUsingInterrupts()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h141 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDebugMode()
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
166 …DIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetOutputUpdate()
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetChannelEnable()
201 … & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetChannelEnable()
358 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDMARequest()
388 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetInterruptRequest()
608 return (((Base->CH.UC[Channel].S & eMIOS_S_OVR_MASK) >> eMIOS_S_OVR_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetOverRunFlag()
636 … return (((Base->CH.UC[Channel].S & eMIOS_S_OVFL_MASK) >> eMIOS_S_OVFL_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetOverFlowFlag()
648 …eturn (((Base->CH.UC[Channel].S & eMIOS_S_UCOUT_MASK) >> eMIOS_S_UCOUT_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetOutputPinState()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DWkpu_Ip.c438 TRUE); in Wkpu_Ip_EnableInterrupt()
445 TRUE); in Wkpu_Ip_EnableInterrupt()
590 Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].chInit = TRUE; in Wkpu_Ip_Init()
727 TRUE); in Wkpu_Ip_SetActivationCondition()
747 TRUE); in Wkpu_Ip_SetActivationCondition()
771 TRUE); in Wkpu_Ip_SetActivationCondition()
777 TRUE); in Wkpu_Ip_SetActivationCondition()
824 bstate = TRUE; in Wkpu_Ip_GetInputState()
836 bstate = TRUE; in Wkpu_Ip_GetInputState()
854 Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].notificationEnable = TRUE; in Wkpu_Ip_EnableNotification()
DWkpu_Ip_Irq.c227 if(((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].chInit) && \ in Wkpu_Ip_Callback()
235 if (((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].chInit) && \ in Wkpu_Ip_Callback()
237 … ((boolean)TRUE == Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].notificationEnable)) in Wkpu_Ip_Callback()
DSiul2_Icu_Ip.c233 … if(TRUE == Siul2_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][hwChannel]].chInit) in Siul2_Icu_Ip_DeInit()
315 if ( TRUE == (*userConfig->pChannelsConfig)[index].digFilterEn) in Siul2_Icu_Ip_Init()
361 Siul2_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][hwChannel]].chInit = TRUE; in Siul2_Icu_Ip_Init()
423 bStatus = TRUE; in Siul2_Icu_Ip_GetInputState()
494 …_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][hwChannel]].notificationEnable = TRUE; in Siul2_Icu_Ip_EnableNotification()
DEmios_Icu_Ip_Irq.c446 …s_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].callbackParam, (1U << 1), TRUE); in Emios_Icu_Ip_SignalMeasurementStore()
851 …((boolean)TRUE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificat… in Emios_Icu_Ip_TimestampHandler()
888 bOverflowUsingMasterbus = TRUE; in Emios_Icu_Ip_ProcessMasterBusInterrupt()
896 bOverflowUsingMasterbus = TRUE; in Emios_Icu_Ip_ProcessMasterBusInterrupt()
904 bOverflowUsingMasterbus = TRUE; in Emios_Icu_Ip_ProcessMasterBusInterrupt()
914 if(TRUE == bOverflowUsingMasterbus) in Emios_Icu_Ip_ProcessMasterBusInterrupt()
919 Emios_Icu_Ip_ReportOverflow(instance, nCounter, TRUE); in Emios_Icu_Ip_ProcessMasterBusInterrupt()
949 …((boolean)TRUE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificat… in Emios_Icu_Ip_ReportEvents()
1055 bEnableInter = TRUE; in Emios_Icu_Ip_IrqHandler()
1064 bOverflow = ((eMIOS_S_OVFL_MASK == (u32RegCSR & eMIOS_S_OVFL_MASK)) ? TRUE : FALSE); in Emios_Icu_Ip_IrqHandler()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c178 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == TRUE) in Emios_Mcl_Ip_Init()
233 …ChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].channelInitState = TRUE; in Emios_Mcl_Ip_Init()
243 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = TRUE; in Emios_Mcl_Ip_Init()
339 if(Emios_Ip_axChState[Instance][CurrentChannel].channelInitState == TRUE) in Emios_Mcl_Ip_Deinit()
393 if (TRUE == Emios_Ip_axChState[HwInstance][HwChannel].channelInitState) in Emios_Mcl_Ip_ValidateChannel()
395 Valid = TRUE; in Emios_Mcl_Ip_ValidateChannel()
465 Valid = TRUE; in Emios_Mcl_Ip_ValidateMultiCoreInit()
/hal_nxp-3.5.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c352 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE); in Netc_EthSwt_Ip_TimeoutExpired()
435 if(TRUE == PortEnable) in Netc_EthSwt_Ip_SetPortMode()
496 *PortEnable = TRUE; in Netc_EthSwt_Ip_GetPortMode()
508 *PortEnable = TRUE; in Netc_EthSwt_Ip_GetPortMode()
951 …MECAPE_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_TIMECAPE_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
952 …DYNAMIC_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_DYNAMIC_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
954 …ELD_IMIRE_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_IMIRE_SHIFT) != 0x0UL) ? TRUE : FALSE; in Netc_EthSwt_Ip_QueryFdbTableEntry()
1113 if (TRUE == *StatciEntryQuerying) in VerifyFillInFdbTableListDataFuncCond()
1119 *QueryDone = TRUE; in VerifyFillInFdbTableListDataFuncCond()
1158 …TableDataBuffer.TableDataField[NETC_ETHSWT_IP_FDBTABLE_SEARCH_CRITERIA_CFGECONFIG] = (TRUE == *Sta… in SearchAndFillInFdbTableList()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c299 ErrorFlag = (boolean)TRUE; in Spi_Ip_TransferProcess()
343 if ((State->RxIndex == State->ExpectedFifoReads) || ((boolean)TRUE == ErrorFlag)) in Spi_Ip_TransferProcess()
346 if(((boolean)TRUE == ErrorFlag) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_TransferProcess()
652 ClearCS = (boolean)TRUE; in Spi_Ip_DmaConfig()
684 if((boolean)TRUE == ClearCS) in Spi_Ip_DmaConfig()
694 EnScatterGather = (boolean)TRUE; in Spi_Ip_DmaConfig()
703 if((boolean)TRUE == EnScatterGather) in Spi_Ip_DmaConfig()
867 ClearCS = (boolean)TRUE; in Spi_Ip_DmaContinueTransfer()
899 if((boolean)TRUE == ClearCS) in Spi_Ip_DmaContinueTransfer()
909 EnScatterGather = (boolean)TRUE; in Spi_Ip_DmaContinueTransfer()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DPlatformTypes.h137 #ifndef TRUE
143 #define TRUE true macro
149 #define TRUE 1
/hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c319 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE); in Netc_Eth_Ip_TimeoutExpired()
476 …TimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampValueInvalidForEth = (boolean)TRUE; in Netc_Eth_Ip_InitRxBD()
477 …TimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].TimestampValueInvalidForSwt = (boolean)TRUE; in Netc_Eth_Ip_InitRxBD()
732 MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus = TRUE; in Netc_Eth_Ip_AddMACFilterEntry()
760 if ((TRUE == MACFilterHashTableAddrs[CtrlIndex][CurrentEntry].EntryStatus) && \ in Netc_Eth_Ip_DeleteMACFilterEntry()
778 MatchedEntry = TRUE; in Netc_Eth_Ip_DeleteMACFilterEntry()
998 … if (TRUE == (*(*config->generalConfig).stationInterfaceGeneralConfig)[u8Iterator].enableSi) in Netc_Eth_Ip_Init()
1053 if (TRUE == SiConfig->EnableSIVlan) in Netc_Eth_Ip_Init()
1146 … (Netc_Eth_Ip_apxState[ctrlIndex]->TxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ; in Netc_Eth_Ip_EnableController()
1148 … (Netc_Eth_Ip_apxState[ctrlIndex]->RxPacketsThreshold[0U] != 0U)) ? TRUE : FALSE ; in Netc_Eth_Ip_EnableController()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer_System.c294 OsIf_abMdlInit[CoreId] = TRUE; in OsIf_Timer_System_Init()
326 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_GetCounter()
380 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_GetElapsed()
435 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_SetTimerFrequency()
484 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer_System.c292 OsIf_abMdlInit[CoreId] = TRUE; in OsIf_Timer_System_Init()
321 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_GetCounter()
375 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_GetElapsed()
430 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_SetTimerFrequency()
479 if (TRUE != OsIf_abMdlInit[CoreId]) in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.5.0/s32/drivers/s32ze/Icu/src/
DSiul2_Icu_Ip.c199 if(TRUE == Siul2_Icu_Ip_aChannelState[instance][hwChannel].chInit) in Siul2_Icu_Ip_DeInit()
281 if ( TRUE == (*userConfig->pChannelsConfig)[index].digFilterEn) in Siul2_Icu_Ip_Init()
327 Siul2_Icu_Ip_aChannelState[instance][hwChannel].chInit = TRUE; in Siul2_Icu_Ip_Init()
389 bStatus = TRUE; in Siul2_Icu_Ip_GetInputState()
460 Siul2_Icu_Ip_aChannelState[instance][hwChannel].notificationEnable = TRUE; in Siul2_Icu_Ip_EnableNotification()
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h94 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrTxStatus()
116 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrAhbStatus()
448 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetSlaveLockStatusA()
465 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetLockStatusA()
481 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetErrorStatusA()
715 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetBusyStatus()
739 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetRxDataEvent()
765 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetTxWatermarkAvailable()
1224 return (RegValue != 0U) ? TRUE : FALSE; in Qspi_Ip_Sfp_TgIpcrsValid()
/hal_nxp-3.5.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c122 …0U == (base->SYSMC & (CANXL_SIC_SYSMC_LPMREQ_MASK | CANXL_SIC_SYSMC_FRZREQ_MASK))) ? TRUE : FALSE); in Canexcel_Ip_GetStartMode()
140 if (TRUE == CanXL_IsFreezeMode(CANEXCEL.EXL_SIC[instance])) in Canexcel_Ip_ConfigTimeStamp()
243 if (TRUE == Config->is_rx_fifo_needed) in Canexcel_Ip_Init()
249 Canexcel_Ip_apxState[instance]->rxFifo.isXLFrame = TRUE; in Canexcel_Ip_Init()
267 if (Config->pRxFifoConfig->Rx_Fifo_EnFilterBank1 == TRUE) in Canexcel_Ip_Init()
340 state->msgDesc[descNo].isXLFrame = TRUE; in Canexcel_Ip_ConfigRx()
476 Canexcel_Ip_apxState[instance]->msgDesc[mbIdx].isXLFrame = TRUE; in Canexcel_Ip_ConfigXlTx()
521 if (info->enable_brs == TRUE) in Canexcel_Ip_ConfigFdTx()
602 state->isIntActive = TRUE; in Canexcel_Ip_EnableInterrupts()
722 if (TRUE == CanXL_IsFreezeMode(CANEXCEL.EXL_SIC[u8Instance])) in Canexcel_Ip_SetErrorInt()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Gpt/src/
DStm_Ip.c323 if (TRUE == stopRun) in Stm_Ip_SetDebugMode()
338 if (TRUE == enable) in Stm_Ip_TimerEnable()
369 if (TRUE == enable) in Stm_Ip_ChannelEnable()
475 if((TRUE == Stm_Ip_u32ChState[instance][channel].chInit) && \ in Stm_Ip_ProcessCommonInterrupt()
512 Stm_Ip_TimerEnable(instance, TRUE); in Stm_Ip_Init()
555 Stm_Ip_u32ChState[instance][configPtr->hwChannel].chInit = TRUE; in Stm_Ip_InitChannel()
630 Stm_Ip_ChannelEnable(instance, channel, TRUE); in Stm_Ip_StartCounting()
657 Stm_Ip_ChannelEnable(instance, channel, TRUE); in Stm_Ip_StartCountingAbsolute()
680 Stm_Ip_TimerEnable(instance, TRUE); in Stm_Ip_StartTimer()
722 Stm_Ip_ChannelEnable(instance, channel, TRUE); in Stm_Ip_EnableChannel()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Swt/src/
DSwt_Ip.c472 Wdg_Ip_abStatus[Instance] = TRUE; in Swt_Ip_Init()
551 BUnlockSequence = TRUE; in Swt_Ip_Service()
558 BUnlockSequence = TRUE; in Swt_Ip_Service()
563 if ((SWT_IP_SOFTLOCK == Swt_Ip_GetLock(Base)) && (TRUE == BUnlockSequence)) in Swt_Ip_Service()
821 if(Wdg_Ip_abStatus[Instance] == TRUE) in Swt_Ip_IrqHandler()

123