1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_TMU.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_TMU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_TMU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_TMU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TMU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TMU - Size of Registers Arrays */ 72 #define TMU_TRITRATSR_COUNT 5u 73 #define TMU_NUM_SITE_RC_COUNT 16u 74 75 /** TMU - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t TMR; /**< Mode, offset: 0x0 */ 78 __IO uint32_t TSR; /**< Status, offset: 0x4 */ 79 __IO uint32_t TMSR; /**< Monitor Site, offset: 0x8 */ 80 __IO uint32_t TMTMIR; /**< Monitor Temperature Measurement Interval, offset: 0xC */ 81 uint8_t RESERVED_0[16]; 82 __IO uint32_t TIER; /**< Interrupt Enable, offset: 0x20 */ 83 __IO uint32_t TIDR; /**< Interrupt Detect, offset: 0x24 */ 84 uint8_t RESERVED_1[8]; 85 __IO uint32_t TIISCR; /**< Interrupt Immediate Site Capture, offset: 0x30 */ 86 __IO uint32_t TIASCR; /**< Interrupt Average Site Capture, offset: 0x34 */ 87 __IO uint32_t TICSCR; /**< Interrupt Critical Site Capture, offset: 0x38 */ 88 uint8_t RESERVED_2[4]; 89 __IO uint32_t TMHTCR; /**< Monitor High Temperature Capture, offset: 0x40 */ 90 __IO uint32_t TMLTCR; /**< Monitor Low Temperature Capture, offset: 0x44 */ 91 __IO uint32_t TMRTRCR; /**< Monitor Rising Temperature Rate Capture, offset: 0x48 */ 92 __IO uint32_t TMFTRCR; /**< Monitor Falling Temperature Rate Capture, offset: 0x4C */ 93 __IO uint32_t TMHTITR; /**< Monitor High Temperature Immediate Threshold, offset: 0x50 */ 94 __IO uint32_t TMHTATR; /**< Monitor High Temperature Average Threshold, offset: 0x54 */ 95 __IO uint32_t TMHTACTR; /**< Monitor High Temperature Average Critical Threshold, offset: 0x58 */ 96 uint8_t RESERVED_3[4]; 97 __IO uint32_t TMLTITR; /**< Monitor Low Temperature Immediate Threshold, offset: 0x60 */ 98 __IO uint32_t TMLTATR; /**< Monitor Low Temperature Average Threshold, offset: 0x64 */ 99 __IO uint32_t TMLTACTR; /**< Monitor Low Temperature Average Critical Threshold, offset: 0x68 */ 100 uint8_t RESERVED_4[4]; 101 __IO uint32_t TMRTRCTR; /**< Monitor Rising Temperature Rate Critical Threshold, offset: 0x70 */ 102 __IO uint32_t TMFTRCTR; /**< Monitor Falling Temperature Rate Critical Threshold, offset: 0x74 */ 103 uint8_t RESERVED_5[8]; 104 __IO uint32_t TTCFGR; /**< Temperature Configuration, offset: 0x80 */ 105 __IO uint32_t TSCFGR; /**< Sensor Configuration, offset: 0x84 */ 106 uint8_t RESERVED_6[120]; 107 struct { /* offset: 0x100, array step: 0x10 */ 108 __I uint32_t TRITSR; /**< Report Immediate Temperature at Site, array offset: 0x100, array step: 0x10 */ 109 __I uint32_t TRATSR; /**< Report Average Temperature at Site, array offset: 0x104, array step: 0x10 */ 110 uint8_t RESERVED_0[8]; 111 } TRITRATSR[TMU_TRITRATSR_COUNT]; 112 uint8_t RESERVED_7[3504]; 113 __IO uint32_t TCMCFG; /**< Central Module Configuration, offset: 0xF00 */ 114 uint8_t RESERVED_8[12]; 115 __IO uint32_t TTRCR[TMU_NUM_SITE_RC_COUNT]; /**< Temperature Range Control 0..Temperature Range Control 15, array offset: 0xF10, array step: 0x4 */ 116 } TMU_Type, *TMU_MemMapPtr; 117 118 /** Number of instances of the TMU module. */ 119 #define TMU_INSTANCE_COUNT (1u) 120 121 /* TMU - Peripheral instance base addresses */ 122 /** Peripheral TMU base address */ 123 #define IP_TMU_BASE (0x402B0000u) 124 /** Peripheral TMU base pointer */ 125 #define IP_TMU ((TMU_Type *)IP_TMU_BASE) 126 /** Array initializer of TMU peripheral base addresses */ 127 #define IP_TMU_BASE_ADDRS { IP_TMU_BASE } 128 /** Array initializer of TMU peripheral base pointers */ 129 #define IP_TMU_BASE_PTRS { IP_TMU } 130 131 /* ---------------------------------------------------------------------------- 132 -- TMU Register Masks 133 ---------------------------------------------------------------------------- */ 134 135 /*! 136 * @addtogroup TMU_Register_Masks TMU Register Masks 137 * @{ 138 */ 139 140 /*! @name TMR - Mode */ 141 /*! @{ */ 142 143 #define TMU_TMR_ALPF_MASK (0x3000000U) 144 #define TMU_TMR_ALPF_SHIFT (24U) 145 #define TMU_TMR_ALPF_WIDTH (2U) 146 #define TMU_TMR_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_ALPF_SHIFT)) & TMU_TMR_ALPF_MASK) 147 148 #define TMU_TMR_CMD_MASK (0x20000000U) 149 #define TMU_TMR_CMD_SHIFT (29U) 150 #define TMU_TMR_CMD_WIDTH (1U) 151 #define TMU_TMR_CMD(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_CMD_SHIFT)) & TMU_TMR_CMD_MASK) 152 153 #define TMU_TMR_MODE_MASK (0xC0000000U) 154 #define TMU_TMR_MODE_SHIFT (30U) 155 #define TMU_TMR_MODE_WIDTH (2U) 156 #define TMU_TMR_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMR_MODE_SHIFT)) & TMU_TMR_MODE_MASK) 157 /*! @} */ 158 159 /*! @name TSR - Status */ 160 /*! @{ */ 161 162 #define TMU_TSR_ORH_MASK (0x10000000U) 163 #define TMU_TSR_ORH_SHIFT (28U) 164 #define TMU_TSR_ORH_WIDTH (1U) 165 #define TMU_TSR_ORH(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORH_SHIFT)) & TMU_TSR_ORH_MASK) 166 167 #define TMU_TSR_ORL_MASK (0x20000000U) 168 #define TMU_TSR_ORL_SHIFT (29U) 169 #define TMU_TSR_ORL_WIDTH (1U) 170 #define TMU_TSR_ORL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_ORL_SHIFT)) & TMU_TSR_ORL_MASK) 171 172 #define TMU_TSR_MIE_MASK (0x40000000U) 173 #define TMU_TSR_MIE_SHIFT (30U) 174 #define TMU_TSR_MIE_WIDTH (1U) 175 #define TMU_TSR_MIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_MIE_SHIFT)) & TMU_TSR_MIE_MASK) 176 177 #define TMU_TSR_TB_MASK (0x80000000U) 178 #define TMU_TSR_TB_SHIFT (31U) 179 #define TMU_TSR_TB_WIDTH (1U) 180 #define TMU_TSR_TB(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_TB_SHIFT)) & TMU_TSR_TB_MASK) 181 /*! @} */ 182 183 /*! @name TMSR - Monitor Site */ 184 /*! @{ */ 185 186 #define TMU_TMSR_SITE_MASK (0x1FU) 187 #define TMU_TMSR_SITE_SHIFT (0U) 188 #define TMU_TMSR_SITE_WIDTH (5U) 189 #define TMU_TMSR_SITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMSR_SITE_SHIFT)) & TMU_TMSR_SITE_MASK) 190 /*! @} */ 191 192 /*! @name TMTMIR - Monitor Temperature Measurement Interval */ 193 /*! @{ */ 194 195 #define TMU_TMTMIR_TMI_MASK (0xFU) 196 #define TMU_TMTMIR_TMI_SHIFT (0U) 197 #define TMU_TMTMIR_TMI_WIDTH (4U) 198 #define TMU_TMTMIR_TMI(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMTMIR_TMI_SHIFT)) & TMU_TMTMIR_TMI_MASK) 199 /*! @} */ 200 201 /*! @name TIER - Interrupt Enable */ 202 /*! @{ */ 203 204 #define TMU_TIER_FTRCTIE_MASK (0x1000000U) 205 #define TMU_TIER_FTRCTIE_SHIFT (24U) 206 #define TMU_TIER_FTRCTIE_WIDTH (1U) 207 #define TMU_TIER_FTRCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_FTRCTIE_SHIFT)) & TMU_TIER_FTRCTIE_MASK) 208 209 #define TMU_TIER_RTRCTIE_MASK (0x2000000U) 210 #define TMU_TIER_RTRCTIE_SHIFT (25U) 211 #define TMU_TIER_RTRCTIE_WIDTH (1U) 212 #define TMU_TIER_RTRCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_RTRCTIE_SHIFT)) & TMU_TIER_RTRCTIE_MASK) 213 214 #define TMU_TIER_ALTCTIE_MASK (0x4000000U) 215 #define TMU_TIER_ALTCTIE_SHIFT (26U) 216 #define TMU_TIER_ALTCTIE_WIDTH (1U) 217 #define TMU_TIER_ALTCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ALTCTIE_SHIFT)) & TMU_TIER_ALTCTIE_MASK) 218 219 #define TMU_TIER_ALTTIE_MASK (0x8000000U) 220 #define TMU_TIER_ALTTIE_SHIFT (27U) 221 #define TMU_TIER_ALTTIE_WIDTH (1U) 222 #define TMU_TIER_ALTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ALTTIE_SHIFT)) & TMU_TIER_ALTTIE_MASK) 223 224 #define TMU_TIER_ILTTIE_MASK (0x10000000U) 225 #define TMU_TIER_ILTTIE_SHIFT (28U) 226 #define TMU_TIER_ILTTIE_WIDTH (1U) 227 #define TMU_TIER_ILTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ILTTIE_SHIFT)) & TMU_TIER_ILTTIE_MASK) 228 229 #define TMU_TIER_AHTCTIE_MASK (0x20000000U) 230 #define TMU_TIER_AHTCTIE_SHIFT (29U) 231 #define TMU_TIER_AHTCTIE_WIDTH (1U) 232 #define TMU_TIER_AHTCTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_AHTCTIE_SHIFT)) & TMU_TIER_AHTCTIE_MASK) 233 234 #define TMU_TIER_AHTTIE_MASK (0x40000000U) 235 #define TMU_TIER_AHTTIE_SHIFT (30U) 236 #define TMU_TIER_AHTTIE_WIDTH (1U) 237 #define TMU_TIER_AHTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_AHTTIE_SHIFT)) & TMU_TIER_AHTTIE_MASK) 238 239 #define TMU_TIER_IHTTIE_MASK (0x80000000U) 240 #define TMU_TIER_IHTTIE_SHIFT (31U) 241 #define TMU_TIER_IHTTIE_WIDTH (1U) 242 #define TMU_TIER_IHTTIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_IHTTIE_SHIFT)) & TMU_TIER_IHTTIE_MASK) 243 /*! @} */ 244 245 /*! @name TIDR - Interrupt Detect */ 246 /*! @{ */ 247 248 #define TMU_TIDR_FTRCT_MASK (0x1000000U) 249 #define TMU_TIDR_FTRCT_SHIFT (24U) 250 #define TMU_TIDR_FTRCT_WIDTH (1U) 251 #define TMU_TIDR_FTRCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_FTRCT_SHIFT)) & TMU_TIDR_FTRCT_MASK) 252 253 #define TMU_TIDR_RTRCT_MASK (0x2000000U) 254 #define TMU_TIDR_RTRCT_SHIFT (25U) 255 #define TMU_TIDR_RTRCT_WIDTH (1U) 256 #define TMU_TIDR_RTRCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_RTRCT_SHIFT)) & TMU_TIDR_RTRCT_MASK) 257 258 #define TMU_TIDR_ALTCT_MASK (0x4000000U) 259 #define TMU_TIDR_ALTCT_SHIFT (26U) 260 #define TMU_TIDR_ALTCT_WIDTH (1U) 261 #define TMU_TIDR_ALTCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ALTCT_SHIFT)) & TMU_TIDR_ALTCT_MASK) 262 263 #define TMU_TIDR_ALTT_MASK (0x8000000U) 264 #define TMU_TIDR_ALTT_SHIFT (27U) 265 #define TMU_TIDR_ALTT_WIDTH (1U) 266 #define TMU_TIDR_ALTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ALTT_SHIFT)) & TMU_TIDR_ALTT_MASK) 267 268 #define TMU_TIDR_ILTT_MASK (0x10000000U) 269 #define TMU_TIDR_ILTT_SHIFT (28U) 270 #define TMU_TIDR_ILTT_WIDTH (1U) 271 #define TMU_TIDR_ILTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ILTT_SHIFT)) & TMU_TIDR_ILTT_MASK) 272 273 #define TMU_TIDR_AHTCT_MASK (0x20000000U) 274 #define TMU_TIDR_AHTCT_SHIFT (29U) 275 #define TMU_TIDR_AHTCT_WIDTH (1U) 276 #define TMU_TIDR_AHTCT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_AHTCT_SHIFT)) & TMU_TIDR_AHTCT_MASK) 277 278 #define TMU_TIDR_AHTT_MASK (0x40000000U) 279 #define TMU_TIDR_AHTT_SHIFT (30U) 280 #define TMU_TIDR_AHTT_WIDTH (1U) 281 #define TMU_TIDR_AHTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_AHTT_SHIFT)) & TMU_TIDR_AHTT_MASK) 282 283 #define TMU_TIDR_IHTT_MASK (0x80000000U) 284 #define TMU_TIDR_IHTT_SHIFT (31U) 285 #define TMU_TIDR_IHTT_WIDTH (1U) 286 #define TMU_TIDR_IHTT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_IHTT_SHIFT)) & TMU_TIDR_IHTT_MASK) 287 /*! @} */ 288 289 /*! @name TIISCR - Interrupt Immediate Site Capture */ 290 /*! @{ */ 291 292 #define TMU_TIISCR_SITE_MASK (0x1FU) 293 #define TMU_TIISCR_SITE_SHIFT (0U) 294 #define TMU_TIISCR_SITE_WIDTH (5U) 295 #define TMU_TIISCR_SITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIISCR_SITE_SHIFT)) & TMU_TIISCR_SITE_MASK) 296 /*! @} */ 297 298 /*! @name TIASCR - Interrupt Average Site Capture */ 299 /*! @{ */ 300 301 #define TMU_TIASCR_SITE_MASK (0x1FU) 302 #define TMU_TIASCR_SITE_SHIFT (0U) 303 #define TMU_TIASCR_SITE_WIDTH (5U) 304 #define TMU_TIASCR_SITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIASCR_SITE_SHIFT)) & TMU_TIASCR_SITE_MASK) 305 /*! @} */ 306 307 /*! @name TICSCR - Interrupt Critical Site Capture */ 308 /*! @{ */ 309 310 #define TMU_TICSCR_SITE_MASK (0x1FU) 311 #define TMU_TICSCR_SITE_SHIFT (0U) 312 #define TMU_TICSCR_SITE_WIDTH (5U) 313 #define TMU_TICSCR_SITE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TICSCR_SITE_SHIFT)) & TMU_TICSCR_SITE_MASK) 314 /*! @} */ 315 316 /*! @name TMHTCR - Monitor High Temperature Capture */ 317 /*! @{ */ 318 319 #define TMU_TMHTCR_TEMP_MASK (0x1FFU) 320 #define TMU_TMHTCR_TEMP_SHIFT (0U) 321 #define TMU_TMHTCR_TEMP_WIDTH (9U) 322 #define TMU_TMHTCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCR_TEMP_SHIFT)) & TMU_TMHTCR_TEMP_MASK) 323 324 #define TMU_TMHTCR_TP5_MASK (0x200U) 325 #define TMU_TMHTCR_TP5_SHIFT (9U) 326 #define TMU_TMHTCR_TP5_WIDTH (1U) 327 #define TMU_TMHTCR_TP5(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCR_TP5_SHIFT)) & TMU_TMHTCR_TP5_MASK) 328 329 #define TMU_TMHTCR_V_MASK (0x80000000U) 330 #define TMU_TMHTCR_V_SHIFT (31U) 331 #define TMU_TMHTCR_V_WIDTH (1U) 332 #define TMU_TMHTCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTCR_V_SHIFT)) & TMU_TMHTCR_V_MASK) 333 /*! @} */ 334 335 /*! @name TMLTCR - Monitor Low Temperature Capture */ 336 /*! @{ */ 337 338 #define TMU_TMLTCR_TEMP_MASK (0x1FFU) 339 #define TMU_TMLTCR_TEMP_SHIFT (0U) 340 #define TMU_TMLTCR_TEMP_WIDTH (9U) 341 #define TMU_TMLTCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTCR_TEMP_SHIFT)) & TMU_TMLTCR_TEMP_MASK) 342 343 #define TMU_TMLTCR_TP5_MASK (0x200U) 344 #define TMU_TMLTCR_TP5_SHIFT (9U) 345 #define TMU_TMLTCR_TP5_WIDTH (1U) 346 #define TMU_TMLTCR_TP5(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTCR_TP5_SHIFT)) & TMU_TMLTCR_TP5_MASK) 347 348 #define TMU_TMLTCR_V_MASK (0x80000000U) 349 #define TMU_TMLTCR_V_SHIFT (31U) 350 #define TMU_TMLTCR_V_WIDTH (1U) 351 #define TMU_TMLTCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTCR_V_SHIFT)) & TMU_TMLTCR_V_MASK) 352 /*! @} */ 353 354 /*! @name TMRTRCR - Monitor Rising Temperature Rate Capture */ 355 /*! @{ */ 356 357 #define TMU_TMRTRCR_TEMP_MASK (0xFFU) 358 #define TMU_TMRTRCR_TEMP_SHIFT (0U) 359 #define TMU_TMRTRCR_TEMP_WIDTH (8U) 360 #define TMU_TMRTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCR_TEMP_SHIFT)) & TMU_TMRTRCR_TEMP_MASK) 361 362 #define TMU_TMRTRCR_V_MASK (0x80000000U) 363 #define TMU_TMRTRCR_V_SHIFT (31U) 364 #define TMU_TMRTRCR_V_WIDTH (1U) 365 #define TMU_TMRTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCR_V_SHIFT)) & TMU_TMRTRCR_V_MASK) 366 /*! @} */ 367 368 /*! @name TMFTRCR - Monitor Falling Temperature Rate Capture */ 369 /*! @{ */ 370 371 #define TMU_TMFTRCR_TEMP_MASK (0xFFU) 372 #define TMU_TMFTRCR_TEMP_SHIFT (0U) 373 #define TMU_TMFTRCR_TEMP_WIDTH (8U) 374 #define TMU_TMFTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCR_TEMP_SHIFT)) & TMU_TMFTRCR_TEMP_MASK) 375 376 #define TMU_TMFTRCR_V_MASK (0x80000000U) 377 #define TMU_TMFTRCR_V_SHIFT (31U) 378 #define TMU_TMFTRCR_V_WIDTH (1U) 379 #define TMU_TMFTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCR_V_SHIFT)) & TMU_TMFTRCR_V_MASK) 380 /*! @} */ 381 382 /*! @name TMHTITR - Monitor High Temperature Immediate Threshold */ 383 /*! @{ */ 384 385 #define TMU_TMHTITR_TEMP_MASK (0x1FFU) 386 #define TMU_TMHTITR_TEMP_SHIFT (0U) 387 #define TMU_TMHTITR_TEMP_WIDTH (9U) 388 #define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK) 389 390 #define TMU_TMHTITR_EN_MASK (0x80000000U) 391 #define TMU_TMHTITR_EN_SHIFT (31U) 392 #define TMU_TMHTITR_EN_WIDTH (1U) 393 #define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK) 394 /*! @} */ 395 396 /*! @name TMHTATR - Monitor High Temperature Average Threshold */ 397 /*! @{ */ 398 399 #define TMU_TMHTATR_TEMP_MASK (0x1FFU) 400 #define TMU_TMHTATR_TEMP_SHIFT (0U) 401 #define TMU_TMHTATR_TEMP_WIDTH (9U) 402 #define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK) 403 404 #define TMU_TMHTATR_EN_MASK (0x80000000U) 405 #define TMU_TMHTATR_EN_SHIFT (31U) 406 #define TMU_TMHTATR_EN_WIDTH (1U) 407 #define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK) 408 /*! @} */ 409 410 /*! @name TMHTACTR - Monitor High Temperature Average Critical Threshold */ 411 /*! @{ */ 412 413 #define TMU_TMHTACTR_TEMP_MASK (0x1FFU) 414 #define TMU_TMHTACTR_TEMP_SHIFT (0U) 415 #define TMU_TMHTACTR_TEMP_WIDTH (9U) 416 #define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK) 417 418 #define TMU_TMHTACTR_EN_MASK (0x80000000U) 419 #define TMU_TMHTACTR_EN_SHIFT (31U) 420 #define TMU_TMHTACTR_EN_WIDTH (1U) 421 #define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK) 422 /*! @} */ 423 424 /*! @name TMLTITR - Monitor Low Temperature Immediate Threshold */ 425 /*! @{ */ 426 427 #define TMU_TMLTITR_TEMP_MASK (0x1FFU) 428 #define TMU_TMLTITR_TEMP_SHIFT (0U) 429 #define TMU_TMLTITR_TEMP_WIDTH (9U) 430 #define TMU_TMLTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTITR_TEMP_SHIFT)) & TMU_TMLTITR_TEMP_MASK) 431 432 #define TMU_TMLTITR_EN_MASK (0x80000000U) 433 #define TMU_TMLTITR_EN_SHIFT (31U) 434 #define TMU_TMLTITR_EN_WIDTH (1U) 435 #define TMU_TMLTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTITR_EN_SHIFT)) & TMU_TMLTITR_EN_MASK) 436 /*! @} */ 437 438 /*! @name TMLTATR - Monitor Low Temperature Average Threshold */ 439 /*! @{ */ 440 441 #define TMU_TMLTATR_TEMP_MASK (0x1FFU) 442 #define TMU_TMLTATR_TEMP_SHIFT (0U) 443 #define TMU_TMLTATR_TEMP_WIDTH (9U) 444 #define TMU_TMLTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTATR_TEMP_SHIFT)) & TMU_TMLTATR_TEMP_MASK) 445 446 #define TMU_TMLTATR_EN_MASK (0x80000000U) 447 #define TMU_TMLTATR_EN_SHIFT (31U) 448 #define TMU_TMLTATR_EN_WIDTH (1U) 449 #define TMU_TMLTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTATR_EN_SHIFT)) & TMU_TMLTATR_EN_MASK) 450 /*! @} */ 451 452 /*! @name TMLTACTR - Monitor Low Temperature Average Critical Threshold */ 453 /*! @{ */ 454 455 #define TMU_TMLTACTR_TEMP_MASK (0x1FFU) 456 #define TMU_TMLTACTR_TEMP_SHIFT (0U) 457 #define TMU_TMLTACTR_TEMP_WIDTH (9U) 458 #define TMU_TMLTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTACTR_TEMP_SHIFT)) & TMU_TMLTACTR_TEMP_MASK) 459 460 #define TMU_TMLTACTR_EN_MASK (0x80000000U) 461 #define TMU_TMLTACTR_EN_SHIFT (31U) 462 #define TMU_TMLTACTR_EN_WIDTH (1U) 463 #define TMU_TMLTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMLTACTR_EN_SHIFT)) & TMU_TMLTACTR_EN_MASK) 464 /*! @} */ 465 466 /*! @name TMRTRCTR - Monitor Rising Temperature Rate Critical Threshold */ 467 /*! @{ */ 468 469 #define TMU_TMRTRCTR_TEMP_MASK (0xFFU) 470 #define TMU_TMRTRCTR_TEMP_SHIFT (0U) 471 #define TMU_TMRTRCTR_TEMP_WIDTH (8U) 472 #define TMU_TMRTRCTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCTR_TEMP_SHIFT)) & TMU_TMRTRCTR_TEMP_MASK) 473 474 #define TMU_TMRTRCTR_EN_MASK (0x80000000U) 475 #define TMU_TMRTRCTR_EN_SHIFT (31U) 476 #define TMU_TMRTRCTR_EN_WIDTH (1U) 477 #define TMU_TMRTRCTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMRTRCTR_EN_SHIFT)) & TMU_TMRTRCTR_EN_MASK) 478 /*! @} */ 479 480 /*! @name TMFTRCTR - Monitor Falling Temperature Rate Critical Threshold */ 481 /*! @{ */ 482 483 #define TMU_TMFTRCTR_TEMP_MASK (0xFFU) 484 #define TMU_TMFTRCTR_TEMP_SHIFT (0U) 485 #define TMU_TMFTRCTR_TEMP_WIDTH (8U) 486 #define TMU_TMFTRCTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCTR_TEMP_SHIFT)) & TMU_TMFTRCTR_TEMP_MASK) 487 488 #define TMU_TMFTRCTR_EN_MASK (0x80000000U) 489 #define TMU_TMFTRCTR_EN_SHIFT (31U) 490 #define TMU_TMFTRCTR_EN_WIDTH (1U) 491 #define TMU_TMFTRCTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMFTRCTR_EN_SHIFT)) & TMU_TMFTRCTR_EN_MASK) 492 /*! @} */ 493 494 /*! @name TTCFGR - Temperature Configuration */ 495 /*! @{ */ 496 497 #define TMU_TTCFGR_CAL_PT_MASK (0xFU) 498 #define TMU_TTCFGR_CAL_PT_SHIFT (0U) 499 #define TMU_TTCFGR_CAL_PT_WIDTH (4U) 500 #define TMU_TTCFGR_CAL_PT(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTCFGR_CAL_PT_SHIFT)) & TMU_TTCFGR_CAL_PT_MASK) 501 /*! @} */ 502 503 /*! @name TSCFGR - Sensor Configuration */ 504 /*! @{ */ 505 506 #define TMU_TSCFGR_SENSOR_MASK (0x1FFU) 507 #define TMU_TSCFGR_SENSOR_SHIFT (0U) 508 #define TMU_TSCFGR_SENSOR_WIDTH (9U) 509 #define TMU_TSCFGR_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCFGR_SENSOR_SHIFT)) & TMU_TSCFGR_SENSOR_MASK) 510 /*! @} */ 511 512 /*! @name TRITSR - Report Immediate Temperature at Site */ 513 /*! @{ */ 514 515 #define TMU_TRITSR_TEMP_MASK (0x1FFU) 516 #define TMU_TRITSR_TEMP_SHIFT (0U) 517 #define TMU_TRITSR_TEMP_WIDTH (9U) 518 #define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK) 519 520 #define TMU_TRITSR_TP5_MASK (0x200U) 521 #define TMU_TRITSR_TP5_SHIFT (9U) 522 #define TMU_TRITSR_TP5_WIDTH (1U) 523 #define TMU_TRITSR_TP5(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TP5_SHIFT)) & TMU_TRITSR_TP5_MASK) 524 525 #define TMU_TRITSR_V_MASK (0x80000000U) 526 #define TMU_TRITSR_V_SHIFT (31U) 527 #define TMU_TRITSR_V_WIDTH (1U) 528 #define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK) 529 /*! @} */ 530 531 /*! @name TRATSR - Report Average Temperature at Site */ 532 /*! @{ */ 533 534 #define TMU_TRATSR_TEMP_MASK (0x1FFU) 535 #define TMU_TRATSR_TEMP_SHIFT (0U) 536 #define TMU_TRATSR_TEMP_WIDTH (9U) 537 #define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK) 538 539 #define TMU_TRATSR_V_MASK (0x80000000U) 540 #define TMU_TRATSR_V_SHIFT (31U) 541 #define TMU_TRATSR_V_WIDTH (1U) 542 #define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK) 543 /*! @} */ 544 545 /*! @name TCMCFG - Central Module Configuration */ 546 /*! @{ */ 547 548 #define TMU_TCMCFG_DAC_OFFSET_MASK (0x7FU) 549 #define TMU_TCMCFG_DAC_OFFSET_SHIFT (0U) 550 #define TMU_TCMCFG_DAC_OFFSET_WIDTH (7U) 551 #define TMU_TCMCFG_DAC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_DAC_OFFSET_SHIFT)) & TMU_TCMCFG_DAC_OFFSET_MASK) 552 553 #define TMU_TCMCFG_CMET_MASK (0x300U) 554 #define TMU_TCMCFG_CMET_SHIFT (8U) 555 #define TMU_TCMCFG_CMET_WIDTH (2U) 556 #define TMU_TCMCFG_CMET(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_CMET_SHIFT)) & TMU_TCMCFG_CMET_MASK) 557 558 #define TMU_TCMCFG_DFD_MASK (0xC00U) 559 #define TMU_TCMCFG_DFD_SHIFT (10U) 560 #define TMU_TCMCFG_DFD_WIDTH (2U) 561 #define TMU_TCMCFG_DFD(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_DFD_SHIFT)) & TMU_TCMCFG_DFD_MASK) 562 563 #define TMU_TCMCFG_CLK_DIV_MASK (0xF000U) 564 #define TMU_TCMCFG_CLK_DIV_SHIFT (12U) 565 #define TMU_TCMCFG_CLK_DIV_WIDTH (4U) 566 #define TMU_TCMCFG_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_CLK_DIV_SHIFT)) & TMU_TCMCFG_CLK_DIV_MASK) 567 568 #define TMU_TCMCFG_SAR_RDY_MASK (0x10000U) 569 #define TMU_TCMCFG_SAR_RDY_SHIFT (16U) 570 #define TMU_TCMCFG_SAR_RDY_WIDTH (1U) 571 #define TMU_TCMCFG_SAR_RDY(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_SAR_RDY_SHIFT)) & TMU_TCMCFG_SAR_RDY_MASK) 572 573 #define TMU_TCMCFG_RCTC_MASK (0x7000000U) 574 #define TMU_TCMCFG_RCTC_SHIFT (24U) 575 #define TMU_TCMCFG_RCTC_WIDTH (3U) 576 #define TMU_TCMCFG_RCTC(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_RCTC_SHIFT)) & TMU_TCMCFG_RCTC_MASK) 577 578 #define TMU_TCMCFG_DEMA_MASK (0x10000000U) 579 #define TMU_TCMCFG_DEMA_SHIFT (28U) 580 #define TMU_TCMCFG_DEMA_WIDTH (1U) 581 #define TMU_TCMCFG_DEMA(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_DEMA_SHIFT)) & TMU_TCMCFG_DEMA_MASK) 582 583 #define TMU_TCMCFG_OCS_MASK (0x20000000U) 584 #define TMU_TCMCFG_OCS_SHIFT (29U) 585 #define TMU_TCMCFG_OCS_WIDTH (1U) 586 #define TMU_TCMCFG_OCS(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_OCS_SHIFT)) & TMU_TCMCFG_OCS_MASK) 587 588 #define TMU_TCMCFG_OCM_MASK (0x40000000U) 589 #define TMU_TCMCFG_OCM_SHIFT (30U) 590 #define TMU_TCMCFG_OCM_WIDTH (1U) 591 #define TMU_TCMCFG_OCM(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_OCM_SHIFT)) & TMU_TCMCFG_OCM_MASK) 592 593 #define TMU_TCMCFG_DPM_MASK (0x80000000U) 594 #define TMU_TCMCFG_DPM_SHIFT (31U) 595 #define TMU_TCMCFG_DPM_WIDTH (1U) 596 #define TMU_TCMCFG_DPM(x) (((uint32_t)(((uint32_t)(x)) << TMU_TCMCFG_DPM_SHIFT)) & TMU_TCMCFG_DPM_MASK) 597 /*! @} */ 598 599 /*! @name TTRCR - Temperature Range Control 0..Temperature Range Control 15 */ 600 /*! @{ */ 601 602 #define TMU_TTRCR_TEMP_MASK (0x1FFU) 603 #define TMU_TTRCR_TEMP_SHIFT (0U) 604 #define TMU_TTRCR_TEMP_WIDTH (9U) 605 #define TMU_TTRCR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_TEMP_SHIFT)) & TMU_TTRCR_TEMP_MASK) 606 607 #define TMU_TTRCR_V_MASK (0x80000000U) 608 #define TMU_TTRCR_V_SHIFT (31U) 609 #define TMU_TTRCR_V_WIDTH (1U) 610 #define TMU_TTRCR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TTRCR_V_SHIFT)) & TMU_TTRCR_V_MASK) 611 /*! @} */ 612 613 /*! 614 * @} 615 */ /* end of group TMU_Register_Masks */ 616 617 /*! 618 * @} 619 */ /* end of group TMU_Peripheral_Access_Layer */ 620 621 #endif /* #if !defined(S32Z2_TMU_H_) */ 622
