| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/tmu_1/ |
| D | fsl_tmu.c | 114 base->TIER = TMU_TIER_ITTEIE_MASK; /* Clear interrupt detect register. */ in TMU_ClearInterruptStatusFlags()
119 base->TIER = TMU_TIER_ATTEIE_MASK; /* Clear interrupt detect register. */ in TMU_ClearInterruptStatusFlags()
124 base->TIER = TMU_TIER_ATCTEIE_MASK; /* Clear interrupt detect register. */ in TMU_ClearInterruptStatusFlags()
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| D | fsl_tmu.h | 225 base->TIER |= mask; in TMU_EnableInterrupts()
236 base->TIER &= ~mask; in TMU_DisableInterrupts()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/tmu_2/ |
| D | fsl_tmu.h | 183 base->TIER |= mask; in TMU_EnableInterrupts()
194 base->TIER &= ~mask; in TMU_DisableInterrupts()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/drivers/tmu/ |
| D | fsl_tmu.h | 214 base->TIER |= mask; in TMU_EnableInterrupts()
225 base->TIER &= ~mask; in TMU_DisableInterrupts()
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| /hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_TMU.h | 82 __IO uint32_t TIER; /**< Interrupt Enable, offset: 0x20 */ member
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| D | S32Z2_LFAST.h | 89 …__IO uint32_t TIER; /**< LFAST Tx Interrupt Enable Register, offset: … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_ca53.h | 50085 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| D | MIMX8MN6_cm7.h | 50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 50073 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 50071 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 53127 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 55300 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x20 … member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM4/ |
| D | MIMX8MM4_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM6/ |
| D | MIMX8MM6_cm4.h | 68889 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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| D | MIMX8MM6_ca53.h | 68354 …__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */ member
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