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Searched refs:SPI_CFG_ENABLE_MASK (Results 1 – 25 of 64) sorted by relevance

123

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_minispi/
Dfsl_spi.h375 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
379 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.h417 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
421 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
Dfsl_spi.c206 SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); in SPI_MasterInit()
318 SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); in SPI_SlaveInit()
364 base->CFG &= ~(SPI_CFG_ENABLE_MASK); in SPI_Deinit()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC802/
DLPC802.h3520 #define SPI_CFG_ENABLE_MASK (0x1U) macro
3526 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC811/
DLPC811.h3711 #define SPI_CFG_ENABLE_MASK (0x1U) macro
3717 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC810/
DLPC810.h3711 #define SPI_CFG_ENABLE_MASK (0x1U) macro
3717 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC812/
DLPC812.h3715 #define SPI_CFG_ENABLE_MASK (0x1U) macro
3721 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC804/
DLPC804.h4191 #define SPI_CFG_ENABLE_MASK (0x1U) macro
4197 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC834/
DLPC834.h5211 #define SPI_CFG_ENABLE_MASK (0x1U) macro
5217 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC824/
DLPC824.h5367 #define SPI_CFG_ENABLE_MASK (0x1U) macro
5373 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC822/
DLPC822.h5367 #define SPI_CFG_ENABLE_MASK (0x1U) macro
5373 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC832/
DLPC832.h5211 #define SPI_CFG_ENABLE_MASK (0x1U) macro
5217 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC844/
DLPC844.h5867 #define SPI_CFG_ENABLE_MASK (0x1U) macro
5873 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC845/
DLPC845.h6391 #define SPI_CFG_ENABLE_MASK (0x1U) macro
6397 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h6991 #define SPI_CFG_ENABLE_MASK (0x1U) macro
6997 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h7292 #define SPI_CFG_ENABLE_MASK (0x1U) macro
7298 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
DLPC54114_cm4.h7303 #define SPI_CFG_ENABLE_MASK (0x1U) macro
7309 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h7304 #define SPI_CFG_ENABLE_MASK (0x1U) macro
7310 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10606 #define SPI_CFG_ENABLE_MASK (0x1U) macro
10612 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11380 #define SPI_CFG_ENABLE_MASK (0x1U) macro
11386 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h10736 #define SPI_CFG_ENABLE_MASK (0x1U) macro
10742 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11398 #define SPI_CFG_ENABLE_MASK (0x1U) macro
11404 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h14959 #define SPI_CFG_ENABLE_MASK (0x1U) macro
14965 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h13987 #define SPI_CFG_ENABLE_MASK (0x1U) macro
13993 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h14884 #define SPI_CFG_ENABLE_MASK (0x1U) macro
14890 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)

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