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/hal_nxp-3.5.0/mcux/mcux-sdk/tools/cmake_toolchain_files/
Dxcc.cmake5 SET(TOOLCHAIN_EXT ".exe")
7 SET(TOOLCHAIN_EXT "")
11 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
14 SET(TOOLCHAIN_DIR $ENV{XCC_DIR})
23 SET(XTENSA_SYSTEM $ENV{XTENSA_SYSTEM})
25 SET(XTENSA_SYSTEM "/opt/xtensa/builds/RI-2019.1-linux/nxp_rt600_RI2019_newlib/config")
27 SET(XTENSA_CORE $ENV{XTENSA_CORE})
29 SET(XTENSA_CORE "nxp_rt600_RI2019_newlib")
33 SET(TARGET_TRIPLET "xt")
35 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
[all …]
Dxclang.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{XCC_DIR})
21 SET(XTENSA_SYSTEM $ENV{XTENSA_SYSTEM})
23 SET(XTENSA_SYSTEM "/opt/xtensa/builds/RI-2019.1-linux/nxp_rt600_RI2019_newlib/config")
25 SET(XTENSA_CORE $ENV{XTENSA_CORE})
27 SET(XTENSA_CORE "nxp_rt600_RI2019_newlib")
31 SET(TARGET_TRIPLET "xt")
33 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
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Darmgcc_aarch64.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "aarch64-none-elf")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
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Darmgcc_force_cpp.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "arm-none-eabi")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
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Darmgcc.cmake3 SET(TOOLCHAIN_EXT ".exe")
5 SET(TOOLCHAIN_EXT "")
9 SET (CMAKE_EXECUTABLE_SUFFIX ".elf")
12 SET(TOOLCHAIN_DIR $ENV{ARMGCC_DIR})
22 SET(TARGET_TRIPLET "arm-none-eabi")
24 SET(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_DIR}/bin)
25 SET(TOOLCHAIN_INC_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/include)
26 SET(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_DIR}/${TARGET_TRIPLET}/lib)
28 SET(CMAKE_SYSTEM_NAME Generic)
29 SET(CMAKE_SYSTEM_PROCESSOR arm)
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/ci_pi/
Dfsl_ci_pi.c84 …base->IF_CTRL_REG.SET = CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK | CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK; in CI_PI_Init()
174 base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK; in CI_PI_Start()
189 …base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK | CI_PI_CSR_CSI_CTRL_REG_VSYNC… in CI_PI_Stop()
Dfsl_ci_pi.h153 base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK; in CI_PI_Reset()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/prg/
Dfsl_prg.h85 base->PRG_CTRL.SET = PRG_PRG_CTRL_BYPASS_MASK; in PRG_Enable()
103 base->PRG_CTRL.SET = PRG_PRG_CTRL_SHADOW_EN_MASK; in PRG_EnableShadowLoad()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h56 pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK; in CLOCK_PllInit()
68 pll->CTRL.SET = PLL_CTRL_POWERUP_MASK; in CLOCK_PllInit()
74 pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK; in CLOCK_PllInit()
90 pll->NO_OF_DFS[pfd_n].DFS_CTRL.SET = PLL_NO_OF_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
96 pll->NO_OF_DFS[pfd_n].DFS_CTRL.SET = PLL_NO_OF_DFS_CLKOUT_EN_MASK; in CLOCK_PllPfdInit()
99 pll->NO_OF_DFS[pfd_n].DFS_CTRL.SET = PLL_NO_OF_DFS_CLKOUT_DIVBY2_EN_MASK; in CLOCK_PllPfdInit()
101 pll->NO_OF_DFS[pfd_n].DFS_CTRL.SET = PLL_NO_OF_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
Dfsl_clock.c75 ccm_base->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK; in CLOCK_PowerOffRootClock()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_soc_mipi_csi2rx.c59 …VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK… in MIPI_CSI2RX_InitInterface()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/lpc_gpio/
Dfsl_gpio.h188 base->SET[port] = mask; in GPIO_PortSet()
Dfsl_gpio.c118 base->SET[port] = (1UL << pin); in GPIO_PinInit()
/hal_nxp-3.5.0/mcux/middleware/mcux-sdk-middleware-usb/phy/
Dusb_phy.c88 ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = in USB_EhciPhyInit()
/hal_nxp-3.5.0/mcux/mcux-sdk/CMSIS/DSP/Source/
DCMakeLists.txt2 cmake_policy(SET CMP0077 NEW)
6 SET(DSP ${ROOT}/CMSIS/DSP)
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/sctimer/
Dfsl_sctimer.c669 base->OUT[whichIO].SET |= (1UL << event); in SCTIMER_SetupOutputToggleAction()
Dfsl_sctimer.h897 base->OUT[whichIO].SET |= (1UL << event); in SCTIMER_SetupOutputSetAction()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h8905 __IO uint32_t SET; /**< Reset Control, offset: 0x4 */ member
8911 __IO uint32_t SET; /**< Control, offset: 0x14 */ member
8917 __IO uint32_t SET; /**< Spare Control0, offset: 0x24 */ member
8923 __IO uint32_t SET; /**< Spare Control1, offset: 0x34 */ member
8929 __I uint32_t SET; /**< Spare Status0, offset: 0x44 */ member
12210 …__IO uint32_t SET; /**< Control status register for Context Loader.,… member
17770 __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ member
17777 __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ member
17783 …__I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 … member
17789 __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ member
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h8905 __IO uint32_t SET; /**< Reset Control, offset: 0x4 */ member
8911 __IO uint32_t SET; /**< Control, offset: 0x14 */ member
8917 __IO uint32_t SET; /**< Spare Control0, offset: 0x24 */ member
8923 __IO uint32_t SET; /**< Spare Control1, offset: 0x34 */ member
8929 __I uint32_t SET; /**< Spare Status0, offset: 0x44 */ member
12210 …__IO uint32_t SET; /**< Control status register for Context Loader.,… member
17770 __IO uint32_t SET; /**< System Control 0, offset: 0x4 */ member
17777 __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */ member
17783 …__I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 … member
17789 __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */ member
[all …]

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