1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Wdg.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_WDG_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_WDG_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_WDG_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_WDG_SW_MAJOR_VERSION_C 0
39 #define SCHM_WDG_SW_MINOR_VERSION_C 9
40 #define SCHM_WDG_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_00) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_01) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_02) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_03) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_04) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_05) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_06) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_07) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_08) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_09) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_10) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_11) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_12) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_13) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_WDG_EXCLUSIVE_AREA_14) static volatile uint32 msr_WDG_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_WDG_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_WDG_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
127
128 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
129 #include "Rte_MemMap.h"
130 /*==================================================================================================
131 * GLOBAL CONSTANTS
132 ==================================================================================================*/
133
134
135 /*==================================================================================================
136 * GLOBAL VARIABLES
137 ==================================================================================================*/
138
139 /*==================================================================================================
140 * LOCAL FUNCTION PROTOTYPES
141 ==================================================================================================*/
142
143 #ifndef _COSMIC_C_S32ZE_
144 /*================================================================================================*/
145 /**
146 * @brief This function returns the MSR register value (32 bits).
147 * @details This function returns the MSR register value (32 bits).
148 *
149 * @param[in] void No input parameters
150 * @return uint32 msr This function returns the MSR register value (32 bits).
151 *
152 * @pre None
153 * @post None
154 *
155 */
156 uint32 Wdg_schm_read_msr(void);
157 #endif /*ifndef _COSMIC_C_S32ZE_*/
158 /*==================================================================================================
159 * LOCAL FUNCTIONS
160 ==================================================================================================*/
161 #define RTE_START_SEC_CODE
162 #include "Rte_MemMap.h"
163
164 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
165 /*================================================================================================*/
166 /**
167 * @brief This macro returns the MSR register value (32 bits).
168 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
169 *
170 * @pre None
171 * @post None
172 *
173 */
174 #ifdef MCAL_PLATFORM_ARM
175 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Wdg_schm_read_msr(void)176 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
177 {
178 mrs x0, S3_3_c4_c2_1
179 }
180 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Wdg_schm_read_msr(void)181 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
182 {
183 mrs r0, CPSR
184 }
185 #else
Wdg_schm_read_msr(void)186 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
187 {
188 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
189 mrs r0, BASEPRI
190 #else
191 mrs r0, PRIMASK
192 #endif
193 }
194 #endif
195 #else
196 #ifdef MCAL_PLATFORM_S12
Wdg_schm_read_msr(void)197 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
198 {
199 tfr ccr, d6
200 }
201 #else
Wdg_schm_read_msr(void)202 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
203 {
204 mfmsr r3
205 }
206 #endif
207 #endif
208 #endif /*#ifdef GHS||CW*/
209
210 #ifdef _DIABDATA_C_S32ZE_
211 /**
212 * @brief This function returns the MSR register value (32 bits).
213 * @details This function returns the MSR register value (32 bits).
214 *
215 * @param[in] void No input parameters
216 * @return uint32 msr This function returns the MSR register value (32 bits).
217 *
218 * @pre None
219 * @post None
220 *
221 */
222 #ifdef MCAL_PLATFORM_ARM
Wdg_schm_read_msr(void)223 uint32 Wdg_schm_read_msr(void)
224 {
225 register uint32 reg_tmp;
226 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
227 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
228 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
229 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
230 #else
231 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
232 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
233 #else
234 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
235 #endif
236 #endif
237 return (uint32)reg_tmp;
238 }
239 #else
Wdg_schm_read_msr(void)240 ASM_KEYWORD uint32 Wdg_schm_read_msr(void)
241 {
242 mfmsr r3
243 }
244 #endif /* MCAL_PLATFORM_ARM */
245
246 #endif /* _DIABDATA_C_S32ZE_*/
247
248 #ifdef _COSMIC_C_S32ZE_
249 /*================================================================================================*/
250 /**
251 * @brief This function returns the MSR register value (32 bits).
252 * @details This function returns the MSR register value (32 bits).
253 *
254 * @param[in] void No input parameters
255 * @return uint32 msr This function returns the MSR register value (32 bits).
256 *
257 * @pre None
258 * @post None
259 *
260 */
261
262 #ifdef MCAL_PLATFORM_S12
263 #define Wdg_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
264 #else
265 #define Wdg_schm_read_msr() ASM_KEYWORD("mfmsr r3")
266 #endif
267
268 #endif /*Cosmic compiler only*/
269
270
271 #ifdef _HITECH_C_S32ZE_
272 /*================================================================================================*/
273 /**
274 * @brief This function returns the MSR register value (32 bits).
275 * @details This function returns the MSR register value (32 bits).
276 *
277 * @param[in] void No input parameters
278 * @return uint32 msr This function returns the MSR register value (32 bits).
279 *
280 * @pre None
281 * @post None
282 *
283 */
Wdg_schm_read_msr(void)284 uint32 Wdg_schm_read_msr(void)
285 {
286 uint32 result;
287 __asm volatile("mfmsr %0" : "=r" (result) :);
288 return result;
289 }
290
291 #endif /*HighTec compiler only*/
292 /*================================================================================================*/
293 #ifdef _LINARO_C_S32ZE_
294 /**
295 * @brief This function returns the MSR register value (32 bits).
296 * @details This function returns the MSR register value (32 bits).
297 *
298 * @param[in] void No input parameters
299 * @return uint32 msr This function returns the MSR register value (32 bits).
300 *
301 * @pre None
302 * @post None
303 *
304 */
Wdg_schm_read_msr(void)305 uint32 Wdg_schm_read_msr(void)
306 {
307 register uint32 reg_tmp;
308 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
309 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
310 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
311 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
312 #else
313 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
314 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
315 #else
316 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
317 #endif
318 #endif
319 return (uint32)reg_tmp;
320 }
321 #endif /* _LINARO_C_S32ZE_*/
322 /*================================================================================================*/
323
324 #ifdef _ARM_DS5_C_S32ZE_
325 /**
326 * @brief This function returns the MSR register value (32 bits).
327 * @details This function returns the MSR register value (32 bits).
328 *
329 * @param[in] void No input parameters
330 * @return uint32 msr This function returns the MSR register value (32 bits).
331 *
332 * @pre None
333 * @post None
334 *
335 */
Wdg_schm_read_msr(void)336 uint32 Wdg_schm_read_msr(void)
337 {
338 register uint32 reg_tmp;
339 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
340 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
341 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
342 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
343 #else
344 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
345 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
346 #else
347 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
348 #endif
349 #endif
350 return (uint32)reg_tmp;
351 }
352 #endif /* _ARM_DS5_C_S32ZE_ */
353
354 #ifdef _IAR_C_S32ZE_
355 /**
356 * @brief This function returns the MSR register value (32 bits).
357 * @details This function returns the MSR register value (32 bits).
358 *
359 * @param[in] void No input parameters
360 * @return uint32 msr This function returns the MSR register value (32 bits).
361 *
362 * @pre None
363 * @post None
364 *
365 */
Wdg_schm_read_msr(void)366 uint32 Wdg_schm_read_msr(void)
367 {
368 register uint32 reg_tmp;
369
370 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
371 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
372 #else
373 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
374 #endif
375
376 return (uint32)reg_tmp;
377 }
378 #endif /* _IAR_C_S32ZE_ */
379
380 #define RTE_STOP_SEC_CODE
381 #include "Rte_MemMap.h"
382
383 /*==================================================================================================
384 * GLOBAL FUNCTIONS
385 ==================================================================================================*/
386 #define RTE_START_SEC_CODE
387 #include "Rte_MemMap.h"
388
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00(void)389 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_00(void)
390 {
391 uint32 msr;
392 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
393
394 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId])
395 {
396 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
397 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
398 #else
399 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
400 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
401 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
402 {
403 OsIf_SuspendAllInterrupts();
404 #ifdef _ARM_DS5_C_S32ZE_
405 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
406 #endif
407 }
408 msr_WDG_EXCLUSIVE_AREA_00[u32CoreId] = msr;
409 }
410 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]++;
411 }
412
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00(void)413 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_00(void)
414 {
415 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
416
417 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]--;
418 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
419 {
420 OsIf_ResumeAllInterrupts();
421 #ifdef _ARM_DS5_C_S32ZE_
422 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
423 #endif
424 }
425 }
426
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01(void)427 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_01(void)
428 {
429 uint32 msr;
430 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
431
432 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId])
433 {
434 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
435 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
436 #else
437 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
438 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
439 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
440 {
441 OsIf_SuspendAllInterrupts();
442 #ifdef _ARM_DS5_C_S32ZE_
443 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
444 #endif
445 }
446 msr_WDG_EXCLUSIVE_AREA_01[u32CoreId] = msr;
447 }
448 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]++;
449 }
450
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01(void)451 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_01(void)
452 {
453 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
454
455 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]--;
456 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
457 {
458 OsIf_ResumeAllInterrupts();
459 #ifdef _ARM_DS5_C_S32ZE_
460 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
461 #endif
462 }
463 }
464
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02(void)465 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_02(void)
466 {
467 uint32 msr;
468 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
469
470 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId])
471 {
472 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
473 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
474 #else
475 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
476 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
477 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
478 {
479 OsIf_SuspendAllInterrupts();
480 #ifdef _ARM_DS5_C_S32ZE_
481 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
482 #endif
483 }
484 msr_WDG_EXCLUSIVE_AREA_02[u32CoreId] = msr;
485 }
486 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]++;
487 }
488
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02(void)489 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_02(void)
490 {
491 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
492
493 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]--;
494 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
495 {
496 OsIf_ResumeAllInterrupts();
497 #ifdef _ARM_DS5_C_S32ZE_
498 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
499 #endif
500 }
501 }
502
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03(void)503 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_03(void)
504 {
505 uint32 msr;
506 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
507
508 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId])
509 {
510 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
511 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
512 #else
513 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
514 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
515 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
516 {
517 OsIf_SuspendAllInterrupts();
518 #ifdef _ARM_DS5_C_S32ZE_
519 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
520 #endif
521 }
522 msr_WDG_EXCLUSIVE_AREA_03[u32CoreId] = msr;
523 }
524 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]++;
525 }
526
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03(void)527 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_03(void)
528 {
529 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
530
531 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]--;
532 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
533 {
534 OsIf_ResumeAllInterrupts();
535 #ifdef _ARM_DS5_C_S32ZE_
536 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
537 #endif
538 }
539 }
540
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04(void)541 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_04(void)
542 {
543 uint32 msr;
544 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
545
546 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId])
547 {
548 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
549 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
550 #else
551 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
552 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
553 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
554 {
555 OsIf_SuspendAllInterrupts();
556 #ifdef _ARM_DS5_C_S32ZE_
557 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
558 #endif
559 }
560 msr_WDG_EXCLUSIVE_AREA_04[u32CoreId] = msr;
561 }
562 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]++;
563 }
564
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04(void)565 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_04(void)
566 {
567 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
568
569 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]--;
570 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
571 {
572 OsIf_ResumeAllInterrupts();
573 #ifdef _ARM_DS5_C_S32ZE_
574 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
575 #endif
576 }
577 }
578
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05(void)579 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_05(void)
580 {
581 uint32 msr;
582 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
583
584 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId])
585 {
586 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
587 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
588 #else
589 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
590 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
591 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
592 {
593 OsIf_SuspendAllInterrupts();
594 #ifdef _ARM_DS5_C_S32ZE_
595 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
596 #endif
597 }
598 msr_WDG_EXCLUSIVE_AREA_05[u32CoreId] = msr;
599 }
600 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]++;
601 }
602
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05(void)603 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_05(void)
604 {
605 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
606
607 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]--;
608 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
609 {
610 OsIf_ResumeAllInterrupts();
611 #ifdef _ARM_DS5_C_S32ZE_
612 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
613 #endif
614 }
615 }
616
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06(void)617 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_06(void)
618 {
619 uint32 msr;
620 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
621
622 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId])
623 {
624 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
625 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
626 #else
627 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
628 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
629 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
630 {
631 OsIf_SuspendAllInterrupts();
632 #ifdef _ARM_DS5_C_S32ZE_
633 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
634 #endif
635 }
636 msr_WDG_EXCLUSIVE_AREA_06[u32CoreId] = msr;
637 }
638 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]++;
639 }
640
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06(void)641 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_06(void)
642 {
643 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
644
645 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]--;
646 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
647 {
648 OsIf_ResumeAllInterrupts();
649 #ifdef _ARM_DS5_C_S32ZE_
650 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
651 #endif
652 }
653 }
654
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07(void)655 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_07(void)
656 {
657 uint32 msr;
658 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
659
660 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId])
661 {
662 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
663 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
664 #else
665 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
666 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
667 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
668 {
669 OsIf_SuspendAllInterrupts();
670 #ifdef _ARM_DS5_C_S32ZE_
671 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
672 #endif
673 }
674 msr_WDG_EXCLUSIVE_AREA_07[u32CoreId] = msr;
675 }
676 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]++;
677 }
678
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07(void)679 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_07(void)
680 {
681 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
682
683 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]--;
684 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
685 {
686 OsIf_ResumeAllInterrupts();
687 #ifdef _ARM_DS5_C_S32ZE_
688 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
689 #endif
690 }
691 }
692
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08(void)693 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_08(void)
694 {
695 uint32 msr;
696 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
697
698 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId])
699 {
700 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
701 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
702 #else
703 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
704 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
705 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
706 {
707 OsIf_SuspendAllInterrupts();
708 #ifdef _ARM_DS5_C_S32ZE_
709 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
710 #endif
711 }
712 msr_WDG_EXCLUSIVE_AREA_08[u32CoreId] = msr;
713 }
714 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]++;
715 }
716
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08(void)717 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_08(void)
718 {
719 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
720
721 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]--;
722 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
723 {
724 OsIf_ResumeAllInterrupts();
725 #ifdef _ARM_DS5_C_S32ZE_
726 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
727 #endif
728 }
729 }
730
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09(void)731 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09(void)
732 {
733 uint32 msr;
734 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
735
736 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId])
737 {
738 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
739 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
740 #else
741 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
742 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
743 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
744 {
745 OsIf_SuspendAllInterrupts();
746 #ifdef _ARM_DS5_C_S32ZE_
747 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
748 #endif
749 }
750 msr_WDG_EXCLUSIVE_AREA_09[u32CoreId] = msr;
751 }
752 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]++;
753 }
754
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09(void)755 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09(void)
756 {
757 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
758
759 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]--;
760 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
761 {
762 OsIf_ResumeAllInterrupts();
763 #ifdef _ARM_DS5_C_S32ZE_
764 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
765 #endif
766 }
767 }
768
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10(void)769 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_10(void)
770 {
771 uint32 msr;
772 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
773
774 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId])
775 {
776 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
777 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
778 #else
779 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
780 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
781 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
782 {
783 OsIf_SuspendAllInterrupts();
784 #ifdef _ARM_DS5_C_S32ZE_
785 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
786 #endif
787 }
788 msr_WDG_EXCLUSIVE_AREA_10[u32CoreId] = msr;
789 }
790 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]++;
791 }
792
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10(void)793 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_10(void)
794 {
795 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
796
797 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]--;
798 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
799 {
800 OsIf_ResumeAllInterrupts();
801 #ifdef _ARM_DS5_C_S32ZE_
802 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
803 #endif
804 }
805 }
806
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11(void)807 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_11(void)
808 {
809 uint32 msr;
810 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
811
812 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId])
813 {
814 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
815 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
816 #else
817 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
818 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
819 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
820 {
821 OsIf_SuspendAllInterrupts();
822 #ifdef _ARM_DS5_C_S32ZE_
823 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
824 #endif
825 }
826 msr_WDG_EXCLUSIVE_AREA_11[u32CoreId] = msr;
827 }
828 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]++;
829 }
830
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11(void)831 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_11(void)
832 {
833 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
834
835 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]--;
836 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
837 {
838 OsIf_ResumeAllInterrupts();
839 #ifdef _ARM_DS5_C_S32ZE_
840 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
841 #endif
842 }
843 }
844
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_12(void)845 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_12(void)
846 {
847 uint32 msr;
848 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
849
850 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId])
851 {
852 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
853 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
854 #else
855 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
856 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
857 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
858 {
859 OsIf_SuspendAllInterrupts();
860 #ifdef _ARM_DS5_C_S32ZE_
861 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
862 #endif
863 }
864 msr_WDG_EXCLUSIVE_AREA_12[u32CoreId] = msr;
865 }
866 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]++;
867 }
868
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_12(void)869 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_12(void)
870 {
871 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
872
873 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]--;
874 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
875 {
876 OsIf_ResumeAllInterrupts();
877 #ifdef _ARM_DS5_C_S32ZE_
878 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
879 #endif
880 }
881 }
882
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_13(void)883 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_13(void)
884 {
885 uint32 msr;
886 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
887
888 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId])
889 {
890 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
891 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
892 #else
893 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
894 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
895 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
896 {
897 OsIf_SuspendAllInterrupts();
898 #ifdef _ARM_DS5_C_S32ZE_
899 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
900 #endif
901 }
902 msr_WDG_EXCLUSIVE_AREA_13[u32CoreId] = msr;
903 }
904 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]++;
905 }
906
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_13(void)907 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_13(void)
908 {
909 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
910
911 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]--;
912 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
913 {
914 OsIf_ResumeAllInterrupts();
915 #ifdef _ARM_DS5_C_S32ZE_
916 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
917 #endif
918 }
919 }
920
SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_14(void)921 void SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_14(void)
922 {
923 uint32 msr;
924 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
925
926 if(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId])
927 {
928 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
929 msr = OsIf_Trusted_Call_Return(Wdg_schm_read_msr);
930 #else
931 msr = Wdg_schm_read_msr(); /*read MSR (to store interrupts state)*/
932 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
933 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
934 {
935 OsIf_SuspendAllInterrupts();
936 #ifdef _ARM_DS5_C_S32ZE_
937 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
938 #endif
939 }
940 msr_WDG_EXCLUSIVE_AREA_14[u32CoreId] = msr;
941 }
942 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]++;
943 }
944
SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_14(void)945 void SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_14(void)
946 {
947 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
948
949 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]--;
950 if ((ISR_ON(msr_WDG_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
951 {
952 OsIf_ResumeAllInterrupts();
953 #ifdef _ARM_DS5_C_S32ZE_
954 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
955 #endif
956 }
957 }
958
959
960 #ifdef MCAL_TESTING_ENVIRONMENT
961 /**
962 @brief This function checks that all entered exclusive areas were also exited.
963 @details This function checks that all entered exclusive areas were also exited. The check
964 is done by verifying that all reentry_guard_* static variables are back to the
965 zero value.
966
967 @param[in] void No input parameters
968 @return void This function does not return a value. Test asserts are used instead.
969
970 @pre None
971 @post None
972
973 @remarks Covers
974 @remarks Implements
975 */
SchM_Check_wdg(void)976 void SchM_Check_wdg(void)
977 {
978 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
979
980 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId]);
981 reentry_guard_WDG_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_00 for the next test in the suite*/
982
983 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId]);
984 reentry_guard_WDG_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_01 for the next test in the suite*/
985
986 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId]);
987 reentry_guard_WDG_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_02 for the next test in the suite*/
988
989 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId]);
990 reentry_guard_WDG_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_03 for the next test in the suite*/
991
992 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId]);
993 reentry_guard_WDG_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_04 for the next test in the suite*/
994
995 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId]);
996 reentry_guard_WDG_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_05 for the next test in the suite*/
997
998 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId]);
999 reentry_guard_WDG_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_06 for the next test in the suite*/
1000
1001 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId]);
1002 reentry_guard_WDG_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_07 for the next test in the suite*/
1003
1004 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId]);
1005 reentry_guard_WDG_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_08 for the next test in the suite*/
1006
1007 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId]);
1008 reentry_guard_WDG_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_09 for the next test in the suite*/
1009
1010 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId]);
1011 reentry_guard_WDG_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_10 for the next test in the suite*/
1012
1013 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId]);
1014 reentry_guard_WDG_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_11 for the next test in the suite*/
1015
1016 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId]);
1017 reentry_guard_WDG_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_12 for the next test in the suite*/
1018
1019 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId]);
1020 reentry_guard_WDG_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_13 for the next test in the suite*/
1021
1022 EU_ASSERT(0UL == reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId]);
1023 reentry_guard_WDG_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_WDG_EXCLUSIVE_AREA_14 for the next test in the suite*/
1024
1025
1026 }
1027 #endif /*MCAL_TESTING_ENVIRONMENT*/
1028
1029 #define RTE_STOP_SEC_CODE
1030 #include "Rte_MemMap.h"
1031
1032 #ifdef __cplusplus
1033 }
1034 #endif
1035
1036 /** @} */
1037
