1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Spi.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_SPI_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_SPI_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_SPI_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_SPI_SW_MAJOR_VERSION_C 0
39 #define SCHM_SPI_SW_MINOR_VERSION_C 9
40 #define SCHM_SPI_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_00) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_01) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_02) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_03) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_04) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_05) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_06) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_07) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_08) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_09) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_10) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_11) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_12) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_13) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_14) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_15) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_16) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_17) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(msr_SPI_EXCLUSIVE_AREA_18) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(reentry_guard_SPI_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
135
136 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
137 #include "Rte_MemMap.h"
138 /*==================================================================================================
139 * GLOBAL CONSTANTS
140 ==================================================================================================*/
141
142
143 /*==================================================================================================
144 * GLOBAL VARIABLES
145 ==================================================================================================*/
146
147 /*==================================================================================================
148 * LOCAL FUNCTION PROTOTYPES
149 ==================================================================================================*/
150
151 #ifndef _COSMIC_C_S32ZE_
152 /*================================================================================================*/
153 /**
154 * @brief This function returns the MSR register value (32 bits).
155 * @details This function returns the MSR register value (32 bits).
156 *
157 * @param[in] void No input parameters
158 * @return uint32 msr This function returns the MSR register value (32 bits).
159 *
160 * @pre None
161 * @post None
162 *
163 */
164 uint32 Spi_schm_read_msr(void);
165 #endif /*ifndef _COSMIC_C_S32ZE_*/
166 /*==================================================================================================
167 * LOCAL FUNCTIONS
168 ==================================================================================================*/
169 #define RTE_START_SEC_CODE
170 #include "Rte_MemMap.h"
171
172 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
173 /*================================================================================================*/
174 /**
175 * @brief This macro returns the MSR register value (32 bits).
176 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
177 *
178 * @pre None
179 * @post None
180 *
181 */
182 #ifdef MCAL_PLATFORM_ARM
183 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Spi_schm_read_msr(void)184 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
185 {
186 mrs x0, S3_3_c4_c2_1
187 }
188 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Spi_schm_read_msr(void)189 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
190 {
191 mrs r0, CPSR
192 }
193 #else
Spi_schm_read_msr(void)194 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
195 {
196 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
197 mrs r0, BASEPRI
198 #else
199 mrs r0, PRIMASK
200 #endif
201 }
202 #endif
203 #else
204 #ifdef MCAL_PLATFORM_S12
Spi_schm_read_msr(void)205 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
206 {
207 tfr ccr, d6
208 }
209 #else
Spi_schm_read_msr(void)210 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
211 {
212 mfmsr r3
213 }
214 #endif
215 #endif
216 #endif /*#ifdef GHS||CW*/
217
218 #ifdef _DIABDATA_C_S32ZE_
219 /**
220 * @brief This function returns the MSR register value (32 bits).
221 * @details This function returns the MSR register value (32 bits).
222 *
223 * @param[in] void No input parameters
224 * @return uint32 msr This function returns the MSR register value (32 bits).
225 *
226 * @pre None
227 * @post None
228 *
229 */
230 #ifdef MCAL_PLATFORM_ARM
Spi_schm_read_msr(void)231 uint32 Spi_schm_read_msr(void)
232 {
233 register uint32 reg_tmp;
234 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
235 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
236 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
237 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
238 #else
239 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
240 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
241 #else
242 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
243 #endif
244 #endif
245 return (uint32)reg_tmp;
246 }
247 #else
Spi_schm_read_msr(void)248 ASM_KEYWORD uint32 Spi_schm_read_msr(void)
249 {
250 mfmsr r3
251 }
252 #endif /* MCAL_PLATFORM_ARM */
253
254 #endif /* _DIABDATA_C_S32ZE_*/
255
256 #ifdef _COSMIC_C_S32ZE_
257 /*================================================================================================*/
258 /**
259 * @brief This function returns the MSR register value (32 bits).
260 * @details This function returns the MSR register value (32 bits).
261 *
262 * @param[in] void No input parameters
263 * @return uint32 msr This function returns the MSR register value (32 bits).
264 *
265 * @pre None
266 * @post None
267 *
268 */
269
270 #ifdef MCAL_PLATFORM_S12
271 #define Spi_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
272 #else
273 #define Spi_schm_read_msr() ASM_KEYWORD("mfmsr r3")
274 #endif
275
276 #endif /*Cosmic compiler only*/
277
278
279 #ifdef _HITECH_C_S32ZE_
280 /*================================================================================================*/
281 /**
282 * @brief This function returns the MSR register value (32 bits).
283 * @details This function returns the MSR register value (32 bits).
284 *
285 * @param[in] void No input parameters
286 * @return uint32 msr This function returns the MSR register value (32 bits).
287 *
288 * @pre None
289 * @post None
290 *
291 */
Spi_schm_read_msr(void)292 uint32 Spi_schm_read_msr(void)
293 {
294 uint32 result;
295 __asm volatile("mfmsr %0" : "=r" (result) :);
296 return result;
297 }
298
299 #endif /*HighTec compiler only*/
300 /*================================================================================================*/
301 #ifdef _LINARO_C_S32ZE_
302 /**
303 * @brief This function returns the MSR register value (32 bits).
304 * @details This function returns the MSR register value (32 bits).
305 *
306 * @param[in] void No input parameters
307 * @return uint32 msr This function returns the MSR register value (32 bits).
308 *
309 * @pre None
310 * @post None
311 *
312 */
Spi_schm_read_msr(void)313 uint32 Spi_schm_read_msr(void)
314 {
315 register uint32 reg_tmp;
316 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
317 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
318 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
319 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
320 #else
321 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
322 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
323 #else
324 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
325 #endif
326 #endif
327 return (uint32)reg_tmp;
328 }
329 #endif /* _LINARO_C_S32ZE_*/
330 /*================================================================================================*/
331
332 #ifdef _ARM_DS5_C_S32ZE_
333 /**
334 * @brief This function returns the MSR register value (32 bits).
335 * @details This function returns the MSR register value (32 bits).
336 *
337 * @param[in] void No input parameters
338 * @return uint32 msr This function returns the MSR register value (32 bits).
339 *
340 * @pre None
341 * @post None
342 *
343 */
Spi_schm_read_msr(void)344 uint32 Spi_schm_read_msr(void)
345 {
346 register uint32 reg_tmp;
347 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
348 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
349 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
350 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
351 #else
352 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
353 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
354 #else
355 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
356 #endif
357 #endif
358 return (uint32)reg_tmp;
359 }
360 #endif /* _ARM_DS5_C_S32ZE_ */
361
362 #ifdef _IAR_C_S32ZE_
363 /**
364 * @brief This function returns the MSR register value (32 bits).
365 * @details This function returns the MSR register value (32 bits).
366 *
367 * @param[in] void No input parameters
368 * @return uint32 msr This function returns the MSR register value (32 bits).
369 *
370 * @pre None
371 * @post None
372 *
373 */
Spi_schm_read_msr(void)374 uint32 Spi_schm_read_msr(void)
375 {
376 register uint32 reg_tmp;
377
378 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
379 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
380 #else
381 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
382 #endif
383
384 return (uint32)reg_tmp;
385 }
386 #endif /* _IAR_C_S32ZE_ */
387
388 #define RTE_STOP_SEC_CODE
389 #include "Rte_MemMap.h"
390
391 /*==================================================================================================
392 * GLOBAL FUNCTIONS
393 ==================================================================================================*/
394 #define RTE_START_SEC_CODE
395 #include "Rte_MemMap.h"
396
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void)397 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void)
398 {
399 uint32 msr;
400 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
401
402 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId])
403 {
404 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
405 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
406 #else
407 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
408 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
409 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
410 {
411 OsIf_SuspendAllInterrupts();
412 #ifdef _ARM_DS5_C_S32ZE_
413 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
414 #endif
415 }
416 msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = msr;
417 }
418 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]++;
419 }
420
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void)421 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void)
422 {
423 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
424
425 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]--;
426 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
427 {
428 OsIf_ResumeAllInterrupts();
429 #ifdef _ARM_DS5_C_S32ZE_
430 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
431 #endif
432 }
433 }
434
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void)435 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void)
436 {
437 uint32 msr;
438 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
439
440 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId])
441 {
442 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
443 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
444 #else
445 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
446 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
447 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
448 {
449 OsIf_SuspendAllInterrupts();
450 #ifdef _ARM_DS5_C_S32ZE_
451 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
452 #endif
453 }
454 msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = msr;
455 }
456 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]++;
457 }
458
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void)459 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void)
460 {
461 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
462
463 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]--;
464 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
465 {
466 OsIf_ResumeAllInterrupts();
467 #ifdef _ARM_DS5_C_S32ZE_
468 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
469 #endif
470 }
471 }
472
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void)473 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void)
474 {
475 uint32 msr;
476 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
477
478 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId])
479 {
480 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
481 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
482 #else
483 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
484 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
485 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
486 {
487 OsIf_SuspendAllInterrupts();
488 #ifdef _ARM_DS5_C_S32ZE_
489 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
490 #endif
491 }
492 msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = msr;
493 }
494 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]++;
495 }
496
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void)497 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void)
498 {
499 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
500
501 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]--;
502 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
503 {
504 OsIf_ResumeAllInterrupts();
505 #ifdef _ARM_DS5_C_S32ZE_
506 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
507 #endif
508 }
509 }
510
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void)511 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void)
512 {
513 uint32 msr;
514 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
515
516 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId])
517 {
518 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
519 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
520 #else
521 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
522 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
523 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
524 {
525 OsIf_SuspendAllInterrupts();
526 #ifdef _ARM_DS5_C_S32ZE_
527 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
528 #endif
529 }
530 msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = msr;
531 }
532 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]++;
533 }
534
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void)535 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void)
536 {
537 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
538
539 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]--;
540 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
541 {
542 OsIf_ResumeAllInterrupts();
543 #ifdef _ARM_DS5_C_S32ZE_
544 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
545 #endif
546 }
547 }
548
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void)549 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void)
550 {
551 uint32 msr;
552 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
553
554 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId])
555 {
556 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
557 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
558 #else
559 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
560 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
561 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
562 {
563 OsIf_SuspendAllInterrupts();
564 #ifdef _ARM_DS5_C_S32ZE_
565 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
566 #endif
567 }
568 msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = msr;
569 }
570 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]++;
571 }
572
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void)573 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void)
574 {
575 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
576
577 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]--;
578 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
579 {
580 OsIf_ResumeAllInterrupts();
581 #ifdef _ARM_DS5_C_S32ZE_
582 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
583 #endif
584 }
585 }
586
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void)587 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void)
588 {
589 uint32 msr;
590 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
591
592 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId])
593 {
594 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
595 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
596 #else
597 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
598 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
599 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
600 {
601 OsIf_SuspendAllInterrupts();
602 #ifdef _ARM_DS5_C_S32ZE_
603 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
604 #endif
605 }
606 msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = msr;
607 }
608 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]++;
609 }
610
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void)611 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void)
612 {
613 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
614
615 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]--;
616 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
617 {
618 OsIf_ResumeAllInterrupts();
619 #ifdef _ARM_DS5_C_S32ZE_
620 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
621 #endif
622 }
623 }
624
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void)625 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void)
626 {
627 uint32 msr;
628 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
629
630 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId])
631 {
632 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
633 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
634 #else
635 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
636 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
637 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
638 {
639 OsIf_SuspendAllInterrupts();
640 #ifdef _ARM_DS5_C_S32ZE_
641 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
642 #endif
643 }
644 msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = msr;
645 }
646 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]++;
647 }
648
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void)649 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void)
650 {
651 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
652
653 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]--;
654 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
655 {
656 OsIf_ResumeAllInterrupts();
657 #ifdef _ARM_DS5_C_S32ZE_
658 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
659 #endif
660 }
661 }
662
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void)663 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void)
664 {
665 uint32 msr;
666 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
667
668 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId])
669 {
670 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
671 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
672 #else
673 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
674 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
675 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
676 {
677 OsIf_SuspendAllInterrupts();
678 #ifdef _ARM_DS5_C_S32ZE_
679 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
680 #endif
681 }
682 msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = msr;
683 }
684 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]++;
685 }
686
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void)687 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void)
688 {
689 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
690
691 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]--;
692 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
693 {
694 OsIf_ResumeAllInterrupts();
695 #ifdef _ARM_DS5_C_S32ZE_
696 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
697 #endif
698 }
699 }
700
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void)701 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void)
702 {
703 uint32 msr;
704 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
705
706 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId])
707 {
708 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
709 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
710 #else
711 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
712 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
713 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
714 {
715 OsIf_SuspendAllInterrupts();
716 #ifdef _ARM_DS5_C_S32ZE_
717 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
718 #endif
719 }
720 msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = msr;
721 }
722 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]++;
723 }
724
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void)725 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void)
726 {
727 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
728
729 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]--;
730 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
731 {
732 OsIf_ResumeAllInterrupts();
733 #ifdef _ARM_DS5_C_S32ZE_
734 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
735 #endif
736 }
737 }
738
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void)739 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void)
740 {
741 uint32 msr;
742 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
743
744 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId])
745 {
746 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
747 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
748 #else
749 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
750 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
751 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
752 {
753 OsIf_SuspendAllInterrupts();
754 #ifdef _ARM_DS5_C_S32ZE_
755 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
756 #endif
757 }
758 msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = msr;
759 }
760 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]++;
761 }
762
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void)763 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void)
764 {
765 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
766
767 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]--;
768 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
769 {
770 OsIf_ResumeAllInterrupts();
771 #ifdef _ARM_DS5_C_S32ZE_
772 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
773 #endif
774 }
775 }
776
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void)777 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void)
778 {
779 uint32 msr;
780 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
781
782 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId])
783 {
784 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
785 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
786 #else
787 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
788 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
789 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
790 {
791 OsIf_SuspendAllInterrupts();
792 #ifdef _ARM_DS5_C_S32ZE_
793 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
794 #endif
795 }
796 msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = msr;
797 }
798 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]++;
799 }
800
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void)801 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void)
802 {
803 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
804
805 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]--;
806 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
807 {
808 OsIf_ResumeAllInterrupts();
809 #ifdef _ARM_DS5_C_S32ZE_
810 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
811 #endif
812 }
813 }
814
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void)815 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void)
816 {
817 uint32 msr;
818 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
819
820 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId])
821 {
822 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
823 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
824 #else
825 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
826 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
827 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
828 {
829 OsIf_SuspendAllInterrupts();
830 #ifdef _ARM_DS5_C_S32ZE_
831 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
832 #endif
833 }
834 msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = msr;
835 }
836 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]++;
837 }
838
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void)839 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void)
840 {
841 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
842
843 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]--;
844 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
845 {
846 OsIf_ResumeAllInterrupts();
847 #ifdef _ARM_DS5_C_S32ZE_
848 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
849 #endif
850 }
851 }
852
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void)853 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void)
854 {
855 uint32 msr;
856 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
857
858 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId])
859 {
860 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
861 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
862 #else
863 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
864 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
865 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
866 {
867 OsIf_SuspendAllInterrupts();
868 #ifdef _ARM_DS5_C_S32ZE_
869 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
870 #endif
871 }
872 msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = msr;
873 }
874 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]++;
875 }
876
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void)877 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void)
878 {
879 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
880
881 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]--;
882 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
883 {
884 OsIf_ResumeAllInterrupts();
885 #ifdef _ARM_DS5_C_S32ZE_
886 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
887 #endif
888 }
889 }
890
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void)891 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void)
892 {
893 uint32 msr;
894 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
895
896 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId])
897 {
898 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
899 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
900 #else
901 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
902 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
903 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
904 {
905 OsIf_SuspendAllInterrupts();
906 #ifdef _ARM_DS5_C_S32ZE_
907 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
908 #endif
909 }
910 msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = msr;
911 }
912 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]++;
913 }
914
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void)915 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void)
916 {
917 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
918
919 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]--;
920 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
921 {
922 OsIf_ResumeAllInterrupts();
923 #ifdef _ARM_DS5_C_S32ZE_
924 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
925 #endif
926 }
927 }
928
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void)929 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void)
930 {
931 uint32 msr;
932 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
933
934 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId])
935 {
936 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
937 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
938 #else
939 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
940 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
941 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
942 {
943 OsIf_SuspendAllInterrupts();
944 #ifdef _ARM_DS5_C_S32ZE_
945 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
946 #endif
947 }
948 msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = msr;
949 }
950 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]++;
951 }
952
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void)953 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void)
954 {
955 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
956
957 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]--;
958 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
959 {
960 OsIf_ResumeAllInterrupts();
961 #ifdef _ARM_DS5_C_S32ZE_
962 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
963 #endif
964 }
965 }
966
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void)967 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void)
968 {
969 uint32 msr;
970 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
971
972 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId])
973 {
974 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
975 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
976 #else
977 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
978 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
979 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
980 {
981 OsIf_SuspendAllInterrupts();
982 #ifdef _ARM_DS5_C_S32ZE_
983 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
984 #endif
985 }
986 msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = msr;
987 }
988 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]++;
989 }
990
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void)991 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void)
992 {
993 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
994
995 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]--;
996 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
997 {
998 OsIf_ResumeAllInterrupts();
999 #ifdef _ARM_DS5_C_S32ZE_
1000 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1001 #endif
1002 }
1003 }
1004
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void)1005 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void)
1006 {
1007 uint32 msr;
1008 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1009
1010 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId])
1011 {
1012 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1013 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1014 #else
1015 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1016 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1017 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1018 {
1019 OsIf_SuspendAllInterrupts();
1020 #ifdef _ARM_DS5_C_S32ZE_
1021 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1022 #endif
1023 }
1024 msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1025 }
1026 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]++;
1027 }
1028
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void)1029 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void)
1030 {
1031 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1032
1033 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]--;
1034 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1035 {
1036 OsIf_ResumeAllInterrupts();
1037 #ifdef _ARM_DS5_C_S32ZE_
1038 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1039 #endif
1040 }
1041 }
1042
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void)1043 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void)
1044 {
1045 uint32 msr;
1046 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1047
1048 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId])
1049 {
1050 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1051 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1052 #else
1053 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1054 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1055 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1056 {
1057 OsIf_SuspendAllInterrupts();
1058 #ifdef _ARM_DS5_C_S32ZE_
1059 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1060 #endif
1061 }
1062 msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1063 }
1064 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]++;
1065 }
1066
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void)1067 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void)
1068 {
1069 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1070
1071 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]--;
1072 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1073 {
1074 OsIf_ResumeAllInterrupts();
1075 #ifdef _ARM_DS5_C_S32ZE_
1076 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1077 #endif
1078 }
1079 }
1080
SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void)1081 void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void)
1082 {
1083 uint32 msr;
1084 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1085
1086 if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId])
1087 {
1088 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1089 msr = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
1090 #else
1091 msr = Spi_schm_read_msr(); /*read MSR (to store interrupts state)*/
1092 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1093 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1094 {
1095 OsIf_SuspendAllInterrupts();
1096 #ifdef _ARM_DS5_C_S32ZE_
1097 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1098 #endif
1099 }
1100 msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1101 }
1102 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]++;
1103 }
1104
SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void)1105 void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void)
1106 {
1107 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1108
1109 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]--;
1110 if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1111 {
1112 OsIf_ResumeAllInterrupts();
1113 #ifdef _ARM_DS5_C_S32ZE_
1114 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1115 #endif
1116 }
1117 }
1118
1119
1120 #ifdef MCAL_TESTING_ENVIRONMENT
1121 /**
1122 @brief This function checks that all entered exclusive areas were also exited.
1123 @details This function checks that all entered exclusive areas were also exited. The check
1124 is done by verifying that all reentry_guard_* static variables are back to the
1125 zero value.
1126
1127 @param[in] void No input parameters
1128 @return void This function does not return a value. Test asserts are used instead.
1129
1130 @pre None
1131 @post None
1132
1133 @remarks Covers
1134 @remarks Implements
1135 */
SchM_Check_spi(void)1136 void SchM_Check_spi(void)
1137 {
1138 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1139
1140 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]);
1141 reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_00 for the next test in the suite*/
1142
1143 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]);
1144 reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_01 for the next test in the suite*/
1145
1146 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]);
1147 reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_02 for the next test in the suite*/
1148
1149 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]);
1150 reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_03 for the next test in the suite*/
1151
1152 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]);
1153 reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_04 for the next test in the suite*/
1154
1155 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]);
1156 reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_05 for the next test in the suite*/
1157
1158 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]);
1159 reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_06 for the next test in the suite*/
1160
1161 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]);
1162 reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_07 for the next test in the suite*/
1163
1164 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]);
1165 reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_08 for the next test in the suite*/
1166
1167 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]);
1168 reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_09 for the next test in the suite*/
1169
1170 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]);
1171 reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_10 for the next test in the suite*/
1172
1173 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]);
1174 reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_11 for the next test in the suite*/
1175
1176 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]);
1177 reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_12 for the next test in the suite*/
1178
1179 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]);
1180 reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_13 for the next test in the suite*/
1181
1182 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]);
1183 reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_14 for the next test in the suite*/
1184
1185 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]);
1186 reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_15 for the next test in the suite*/
1187
1188 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]);
1189 reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_16 for the next test in the suite*/
1190
1191 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]);
1192 reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_17 for the next test in the suite*/
1193
1194 EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]);
1195 reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_18 for the next test in the suite*/
1196
1197
1198 }
1199 #endif /*MCAL_TESTING_ENVIRONMENT*/
1200
1201 #define RTE_STOP_SEC_CODE
1202 #include "Rte_MemMap.h"
1203
1204 #ifdef __cplusplus
1205 }
1206 #endif
1207
1208 /** @} */
1209
