1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Mcl.c
9 * @version 3.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Mcl.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_MCL_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_MCL_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_MCL_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_MCL_SW_MAJOR_VERSION_C 3
44 #define SCHM_MCL_SW_MINOR_VERSION_C 0
45 #define SCHM_MCL_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_03) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_04) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_05) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_06) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_07) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_08) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_09) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_10) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_11) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_12) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_13) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_14) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_15) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_16) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_17) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_18) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_19) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_20) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_21) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_22) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_23) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_24) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_25) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_26) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_27) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_28) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_29) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_30) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_31) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_32) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_33) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_34) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_34) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_35) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_35) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_36) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_36) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_37) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_37) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_38) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_38) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_39) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_39) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_40) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_40) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_41) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_41) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_42) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_42) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
188 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_43) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
189 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_43) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
190 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_44) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
191 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
192 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_45) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
193 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
194 VAR_SEC_NOCACHE(msr_MCL_EXCLUSIVE_AREA_46) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
195 VAR_SEC_NOCACHE(reentry_guard_MCL_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
196
197 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
198 #include "Rte_MemMap.h"
199 /*==================================================================================================
200 * GLOBAL CONSTANTS
201 ==================================================================================================*/
202
203
204 /*==================================================================================================
205 * GLOBAL VARIABLES
206 ==================================================================================================*/
207
208 /*==================================================================================================
209 * LOCAL FUNCTION PROTOTYPES
210 ==================================================================================================*/
211
212 #ifndef _COSMIC_C_S32K3XX_
213 /*================================================================================================*/
214 /**
215 * @brief This function returns the MSR register value (32 bits).
216 * @details This function returns the MSR register value (32 bits).
217 *
218 * @param[in] void No input parameters
219 * @return uint32 msr This function returns the MSR register value (32 bits).
220 *
221 * @pre None
222 * @post None
223 *
224 */
225 uint32 Mcl_schm_read_msr(void);
226 #endif /*ifndef _COSMIC_C_S32K3XX_*/
227 /*==================================================================================================
228 * LOCAL FUNCTIONS
229 ==================================================================================================*/
230 #define RTE_START_SEC_CODE
231 #include "Rte_MemMap.h"
232
233 #if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
234 /*================================================================================================*/
235 /**
236 * @brief This macro returns the MSR register value (32 bits).
237 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
238 *
239 * @pre None
240 * @post None
241 *
242 */
243 #ifdef MCAL_PLATFORM_ARM
244 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Mcl_schm_read_msr(void)245 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
246 {
247 mrs x0, S3_3_c4_c2_1
248 }
249 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Mcl_schm_read_msr(void)250 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
251 {
252 mrs r0, CPSR
253 }
254 #else
Mcl_schm_read_msr(void)255 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
256 {
257 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
258 mrs r0, BASEPRI
259 #else
260 mrs r0, PRIMASK
261 #endif
262 }
263 #endif
264 #else
265 #ifdef MCAL_PLATFORM_S12
Mcl_schm_read_msr(void)266 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
267 {
268 tfr ccr, d6
269 }
270 #else
Mcl_schm_read_msr(void)271 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
272 {
273 mfmsr r3
274 }
275 #endif
276 #endif
277 #endif /*#ifdef GHS||CW*/
278
279 #ifdef _DIABDATA_C_S32K3XX_
280 /**
281 * @brief This function returns the MSR register value (32 bits).
282 * @details This function returns the MSR register value (32 bits).
283 *
284 * @param[in] void No input parameters
285 * @return uint32 msr This function returns the MSR register value (32 bits).
286 *
287 * @pre None
288 * @post None
289 *
290 */
291 #ifdef MCAL_PLATFORM_ARM
Mcl_schm_read_msr(void)292 uint32 Mcl_schm_read_msr(void)
293 {
294 register uint32 reg_tmp;
295 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
296 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
297 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
298 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
299 #else
300 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
301 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
302 #else
303 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
304 #endif
305 #endif
306 return (uint32)reg_tmp;
307 }
308 #else
Mcl_schm_read_msr(void)309 ASM_KEYWORD uint32 Mcl_schm_read_msr(void)
310 {
311 mfmsr r3
312 }
313 #endif /* MCAL_PLATFORM_ARM */
314
315 #endif /* _DIABDATA_C_S32K3XX_*/
316
317 #ifdef _COSMIC_C_S32K3XX_
318 /*================================================================================================*/
319 /**
320 * @brief This function returns the MSR register value (32 bits).
321 * @details This function returns the MSR register value (32 bits).
322 *
323 * @param[in] void No input parameters
324 * @return uint32 msr This function returns the MSR register value (32 bits).
325 *
326 * @pre None
327 * @post None
328 *
329 */
330
331 #ifdef MCAL_PLATFORM_S12
332 #define Mcl_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
333 #else
334 #define Mcl_schm_read_msr() ASM_KEYWORD("mfmsr r3")
335 #endif
336
337 #endif /*Cosmic compiler only*/
338
339
340 #ifdef _HITECH_C_S32K3XX_
341 /*================================================================================================*/
342 /**
343 * @brief This function returns the MSR register value (32 bits).
344 * @details This function returns the MSR register value (32 bits).
345 *
346 * @param[in] void No input parameters
347 * @return uint32 msr This function returns the MSR register value (32 bits).
348 *
349 * @pre None
350 * @post None
351 *
352 */
Mcl_schm_read_msr(void)353 uint32 Mcl_schm_read_msr(void)
354 {
355 uint32 result;
356 __asm volatile("mfmsr %0" : "=r" (result) :);
357 return result;
358 }
359
360 #endif /*HighTec compiler only*/
361 /*================================================================================================*/
362 #ifdef _LINARO_C_S32K3XX_
363 /**
364 * @brief This function returns the MSR register value (32 bits).
365 * @details This function returns the MSR register value (32 bits).
366 *
367 * @param[in] void No input parameters
368 * @return uint32 msr This function returns the MSR register value (32 bits).
369 *
370 * @pre None
371 * @post None
372 *
373 */
Mcl_schm_read_msr(void)374 uint32 Mcl_schm_read_msr(void)
375 {
376 register uint32 reg_tmp;
377 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
378 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
379 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
380 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
381 #else
382 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
383 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
384 #else
385 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
386 #endif
387 #endif
388 return (uint32)reg_tmp;
389 }
390 #endif /* _LINARO_C_S32K3XX_*/
391 /*================================================================================================*/
392
393 #ifdef _ARM_DS5_C_S32K3XX_
394 /**
395 * @brief This function returns the MSR register value (32 bits).
396 * @details This function returns the MSR register value (32 bits).
397 *
398 * @param[in] void No input parameters
399 * @return uint32 msr This function returns the MSR register value (32 bits).
400 *
401 * @pre None
402 * @post None
403 *
404 */
Mcl_schm_read_msr(void)405 uint32 Mcl_schm_read_msr(void)
406 {
407 register uint32 reg_tmp;
408 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
409 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
410 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
411 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
412 #else
413 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
414 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
415 #else
416 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
417 #endif
418 #endif
419 return (uint32)reg_tmp;
420 }
421 #endif /* _ARM_DS5_C_S32K3XX_ */
422
423 #ifdef _IAR_C_S32K3XX_
424 /**
425 * @brief This function returns the MSR register value (32 bits).
426 * @details This function returns the MSR register value (32 bits).
427 *
428 * @param[in] void No input parameters
429 * @return uint32 msr This function returns the MSR register value (32 bits).
430 *
431 * @pre None
432 * @post None
433 *
434 */
Mcl_schm_read_msr(void)435 uint32 Mcl_schm_read_msr(void)
436 {
437 register uint32 reg_tmp;
438
439 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
440 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
441 #else
442 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
443 #endif
444
445 return (uint32)reg_tmp;
446 }
447 #endif /* _IAR_C_S32K3XX_ */
448
449 #define RTE_STOP_SEC_CODE
450 #include "Rte_MemMap.h"
451
452 /*==================================================================================================
453 * GLOBAL FUNCTIONS
454 ==================================================================================================*/
455 #define RTE_START_SEC_CODE
456 #include "Rte_MemMap.h"
457
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_00(void)458 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_00(void)
459 {
460 uint32 msr;
461 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
462
463 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId])
464 {
465 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
466 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
467 #else
468 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
469 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
470 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
471 {
472 OsIf_SuspendAllInterrupts();
473 #ifdef _ARM_DS5_C_S32K3XX_
474 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
475 #endif
476 }
477 msr_MCL_EXCLUSIVE_AREA_00[u32CoreId] = msr;
478 }
479 reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId]++;
480 }
481
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_00(void)482 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_00(void)
483 {
484 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
485
486 reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId]--;
487 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
488 {
489 OsIf_ResumeAllInterrupts();
490 #ifdef _ARM_DS5_C_S32K3XX_
491 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
492 #endif
493 }
494 }
495
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_01(void)496 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_01(void)
497 {
498 uint32 msr;
499 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
500
501 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId])
502 {
503 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
504 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
505 #else
506 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
507 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
508 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
509 {
510 OsIf_SuspendAllInterrupts();
511 #ifdef _ARM_DS5_C_S32K3XX_
512 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
513 #endif
514 }
515 msr_MCL_EXCLUSIVE_AREA_01[u32CoreId] = msr;
516 }
517 reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId]++;
518 }
519
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_01(void)520 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_01(void)
521 {
522 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
523
524 reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId]--;
525 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
526 {
527 OsIf_ResumeAllInterrupts();
528 #ifdef _ARM_DS5_C_S32K3XX_
529 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
530 #endif
531 }
532 }
533
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_02(void)534 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_02(void)
535 {
536 uint32 msr;
537 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
538
539 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId])
540 {
541 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
542 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
543 #else
544 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
545 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
546 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
547 {
548 OsIf_SuspendAllInterrupts();
549 #ifdef _ARM_DS5_C_S32K3XX_
550 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
551 #endif
552 }
553 msr_MCL_EXCLUSIVE_AREA_02[u32CoreId] = msr;
554 }
555 reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId]++;
556 }
557
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_02(void)558 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_02(void)
559 {
560 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
561
562 reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId]--;
563 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
564 {
565 OsIf_ResumeAllInterrupts();
566 #ifdef _ARM_DS5_C_S32K3XX_
567 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
568 #endif
569 }
570 }
571
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_03(void)572 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_03(void)
573 {
574 uint32 msr;
575 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
576
577 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId])
578 {
579 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
580 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
581 #else
582 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
583 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
584 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
585 {
586 OsIf_SuspendAllInterrupts();
587 #ifdef _ARM_DS5_C_S32K3XX_
588 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
589 #endif
590 }
591 msr_MCL_EXCLUSIVE_AREA_03[u32CoreId] = msr;
592 }
593 reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId]++;
594 }
595
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_03(void)596 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_03(void)
597 {
598 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
599
600 reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId]--;
601 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
602 {
603 OsIf_ResumeAllInterrupts();
604 #ifdef _ARM_DS5_C_S32K3XX_
605 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
606 #endif
607 }
608 }
609
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_04(void)610 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_04(void)
611 {
612 uint32 msr;
613 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
614
615 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId])
616 {
617 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
618 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
619 #else
620 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
621 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
622 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
623 {
624 OsIf_SuspendAllInterrupts();
625 #ifdef _ARM_DS5_C_S32K3XX_
626 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
627 #endif
628 }
629 msr_MCL_EXCLUSIVE_AREA_04[u32CoreId] = msr;
630 }
631 reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId]++;
632 }
633
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_04(void)634 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_04(void)
635 {
636 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
637
638 reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId]--;
639 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
640 {
641 OsIf_ResumeAllInterrupts();
642 #ifdef _ARM_DS5_C_S32K3XX_
643 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
644 #endif
645 }
646 }
647
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_05(void)648 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_05(void)
649 {
650 uint32 msr;
651 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
652
653 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId])
654 {
655 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
656 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
657 #else
658 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
659 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
660 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
661 {
662 OsIf_SuspendAllInterrupts();
663 #ifdef _ARM_DS5_C_S32K3XX_
664 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
665 #endif
666 }
667 msr_MCL_EXCLUSIVE_AREA_05[u32CoreId] = msr;
668 }
669 reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId]++;
670 }
671
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_05(void)672 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_05(void)
673 {
674 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
675
676 reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId]--;
677 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
678 {
679 OsIf_ResumeAllInterrupts();
680 #ifdef _ARM_DS5_C_S32K3XX_
681 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
682 #endif
683 }
684 }
685
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_06(void)686 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_06(void)
687 {
688 uint32 msr;
689 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
690
691 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId])
692 {
693 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
694 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
695 #else
696 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
697 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
698 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
699 {
700 OsIf_SuspendAllInterrupts();
701 #ifdef _ARM_DS5_C_S32K3XX_
702 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
703 #endif
704 }
705 msr_MCL_EXCLUSIVE_AREA_06[u32CoreId] = msr;
706 }
707 reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId]++;
708 }
709
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_06(void)710 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_06(void)
711 {
712 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
713
714 reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId]--;
715 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
716 {
717 OsIf_ResumeAllInterrupts();
718 #ifdef _ARM_DS5_C_S32K3XX_
719 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
720 #endif
721 }
722 }
723
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_07(void)724 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_07(void)
725 {
726 uint32 msr;
727 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
728
729 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId])
730 {
731 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
732 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
733 #else
734 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
735 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
736 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
737 {
738 OsIf_SuspendAllInterrupts();
739 #ifdef _ARM_DS5_C_S32K3XX_
740 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
741 #endif
742 }
743 msr_MCL_EXCLUSIVE_AREA_07[u32CoreId] = msr;
744 }
745 reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId]++;
746 }
747
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_07(void)748 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_07(void)
749 {
750 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
751
752 reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId]--;
753 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
754 {
755 OsIf_ResumeAllInterrupts();
756 #ifdef _ARM_DS5_C_S32K3XX_
757 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
758 #endif
759 }
760 }
761
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_08(void)762 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_08(void)
763 {
764 uint32 msr;
765 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
766
767 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId])
768 {
769 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
770 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
771 #else
772 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
773 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
774 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
775 {
776 OsIf_SuspendAllInterrupts();
777 #ifdef _ARM_DS5_C_S32K3XX_
778 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
779 #endif
780 }
781 msr_MCL_EXCLUSIVE_AREA_08[u32CoreId] = msr;
782 }
783 reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId]++;
784 }
785
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_08(void)786 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_08(void)
787 {
788 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
789
790 reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId]--;
791 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
792 {
793 OsIf_ResumeAllInterrupts();
794 #ifdef _ARM_DS5_C_S32K3XX_
795 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
796 #endif
797 }
798 }
799
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_09(void)800 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_09(void)
801 {
802 uint32 msr;
803 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
804
805 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId])
806 {
807 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
808 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
809 #else
810 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
811 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
812 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
813 {
814 OsIf_SuspendAllInterrupts();
815 #ifdef _ARM_DS5_C_S32K3XX_
816 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
817 #endif
818 }
819 msr_MCL_EXCLUSIVE_AREA_09[u32CoreId] = msr;
820 }
821 reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId]++;
822 }
823
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_09(void)824 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_09(void)
825 {
826 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
827
828 reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId]--;
829 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
830 {
831 OsIf_ResumeAllInterrupts();
832 #ifdef _ARM_DS5_C_S32K3XX_
833 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
834 #endif
835 }
836 }
837
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_10(void)838 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_10(void)
839 {
840 uint32 msr;
841 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
842
843 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId])
844 {
845 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
846 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
847 #else
848 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
849 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
850 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
851 {
852 OsIf_SuspendAllInterrupts();
853 #ifdef _ARM_DS5_C_S32K3XX_
854 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
855 #endif
856 }
857 msr_MCL_EXCLUSIVE_AREA_10[u32CoreId] = msr;
858 }
859 reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId]++;
860 }
861
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_10(void)862 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_10(void)
863 {
864 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
865
866 reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId]--;
867 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
868 {
869 OsIf_ResumeAllInterrupts();
870 #ifdef _ARM_DS5_C_S32K3XX_
871 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
872 #endif
873 }
874 }
875
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_11(void)876 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_11(void)
877 {
878 uint32 msr;
879 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
880
881 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId])
882 {
883 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
884 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
885 #else
886 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
887 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
888 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
889 {
890 OsIf_SuspendAllInterrupts();
891 #ifdef _ARM_DS5_C_S32K3XX_
892 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
893 #endif
894 }
895 msr_MCL_EXCLUSIVE_AREA_11[u32CoreId] = msr;
896 }
897 reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId]++;
898 }
899
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_11(void)900 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_11(void)
901 {
902 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
903
904 reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId]--;
905 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
906 {
907 OsIf_ResumeAllInterrupts();
908 #ifdef _ARM_DS5_C_S32K3XX_
909 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
910 #endif
911 }
912 }
913
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_12(void)914 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_12(void)
915 {
916 uint32 msr;
917 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
918
919 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId])
920 {
921 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
922 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
923 #else
924 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
925 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
926 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
927 {
928 OsIf_SuspendAllInterrupts();
929 #ifdef _ARM_DS5_C_S32K3XX_
930 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
931 #endif
932 }
933 msr_MCL_EXCLUSIVE_AREA_12[u32CoreId] = msr;
934 }
935 reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId]++;
936 }
937
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_12(void)938 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_12(void)
939 {
940 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
941
942 reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId]--;
943 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
944 {
945 OsIf_ResumeAllInterrupts();
946 #ifdef _ARM_DS5_C_S32K3XX_
947 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
948 #endif
949 }
950 }
951
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_13(void)952 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_13(void)
953 {
954 uint32 msr;
955 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
956
957 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId])
958 {
959 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
960 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
961 #else
962 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
963 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
964 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
965 {
966 OsIf_SuspendAllInterrupts();
967 #ifdef _ARM_DS5_C_S32K3XX_
968 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
969 #endif
970 }
971 msr_MCL_EXCLUSIVE_AREA_13[u32CoreId] = msr;
972 }
973 reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId]++;
974 }
975
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_13(void)976 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_13(void)
977 {
978 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
979
980 reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId]--;
981 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
982 {
983 OsIf_ResumeAllInterrupts();
984 #ifdef _ARM_DS5_C_S32K3XX_
985 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
986 #endif
987 }
988 }
989
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_14(void)990 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_14(void)
991 {
992 uint32 msr;
993 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
994
995 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId])
996 {
997 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
998 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
999 #else
1000 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1001 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1002 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1003 {
1004 OsIf_SuspendAllInterrupts();
1005 #ifdef _ARM_DS5_C_S32K3XX_
1006 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1007 #endif
1008 }
1009 msr_MCL_EXCLUSIVE_AREA_14[u32CoreId] = msr;
1010 }
1011 reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId]++;
1012 }
1013
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_14(void)1014 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_14(void)
1015 {
1016 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1017
1018 reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId]--;
1019 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
1020 {
1021 OsIf_ResumeAllInterrupts();
1022 #ifdef _ARM_DS5_C_S32K3XX_
1023 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1024 #endif
1025 }
1026 }
1027
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_15(void)1028 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_15(void)
1029 {
1030 uint32 msr;
1031 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1032
1033 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId])
1034 {
1035 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1036 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1037 #else
1038 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1039 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1040 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1041 {
1042 OsIf_SuspendAllInterrupts();
1043 #ifdef _ARM_DS5_C_S32K3XX_
1044 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1045 #endif
1046 }
1047 msr_MCL_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1048 }
1049 reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId]++;
1050 }
1051
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_15(void)1052 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_15(void)
1053 {
1054 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1055
1056 reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId]--;
1057 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1058 {
1059 OsIf_ResumeAllInterrupts();
1060 #ifdef _ARM_DS5_C_S32K3XX_
1061 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1062 #endif
1063 }
1064 }
1065
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_16(void)1066 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_16(void)
1067 {
1068 uint32 msr;
1069 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1070
1071 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId])
1072 {
1073 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1074 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1075 #else
1076 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1077 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1078 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1079 {
1080 OsIf_SuspendAllInterrupts();
1081 #ifdef _ARM_DS5_C_S32K3XX_
1082 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1083 #endif
1084 }
1085 msr_MCL_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1086 }
1087 reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId]++;
1088 }
1089
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_16(void)1090 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_16(void)
1091 {
1092 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1093
1094 reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId]--;
1095 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1096 {
1097 OsIf_ResumeAllInterrupts();
1098 #ifdef _ARM_DS5_C_S32K3XX_
1099 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1100 #endif
1101 }
1102 }
1103
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_17(void)1104 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_17(void)
1105 {
1106 uint32 msr;
1107 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1108
1109 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId])
1110 {
1111 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1112 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1113 #else
1114 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1115 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1116 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1117 {
1118 OsIf_SuspendAllInterrupts();
1119 #ifdef _ARM_DS5_C_S32K3XX_
1120 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1121 #endif
1122 }
1123 msr_MCL_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1124 }
1125 reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId]++;
1126 }
1127
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_17(void)1128 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_17(void)
1129 {
1130 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1131
1132 reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId]--;
1133 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1134 {
1135 OsIf_ResumeAllInterrupts();
1136 #ifdef _ARM_DS5_C_S32K3XX_
1137 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1138 #endif
1139 }
1140 }
1141
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_18(void)1142 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_18(void)
1143 {
1144 uint32 msr;
1145 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1146
1147 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId])
1148 {
1149 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1150 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1151 #else
1152 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1153 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1154 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1155 {
1156 OsIf_SuspendAllInterrupts();
1157 #ifdef _ARM_DS5_C_S32K3XX_
1158 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1159 #endif
1160 }
1161 msr_MCL_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1162 }
1163 reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId]++;
1164 }
1165
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_18(void)1166 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_18(void)
1167 {
1168 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1169
1170 reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId]--;
1171 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1172 {
1173 OsIf_ResumeAllInterrupts();
1174 #ifdef _ARM_DS5_C_S32K3XX_
1175 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1176 #endif
1177 }
1178 }
1179
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_19(void)1180 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_19(void)
1181 {
1182 uint32 msr;
1183 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1184
1185 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId])
1186 {
1187 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1188 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1189 #else
1190 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1191 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1192 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1193 {
1194 OsIf_SuspendAllInterrupts();
1195 #ifdef _ARM_DS5_C_S32K3XX_
1196 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1197 #endif
1198 }
1199 msr_MCL_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1200 }
1201 reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId]++;
1202 }
1203
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_19(void)1204 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_19(void)
1205 {
1206 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1207
1208 reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId]--;
1209 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1210 {
1211 OsIf_ResumeAllInterrupts();
1212 #ifdef _ARM_DS5_C_S32K3XX_
1213 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1214 #endif
1215 }
1216 }
1217
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_20(void)1218 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_20(void)
1219 {
1220 uint32 msr;
1221 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1222
1223 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId])
1224 {
1225 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1226 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1227 #else
1228 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1229 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1230 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1231 {
1232 OsIf_SuspendAllInterrupts();
1233 #ifdef _ARM_DS5_C_S32K3XX_
1234 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1235 #endif
1236 }
1237 msr_MCL_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1238 }
1239 reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId]++;
1240 }
1241
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_20(void)1242 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_20(void)
1243 {
1244 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1245
1246 reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId]--;
1247 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1248 {
1249 OsIf_ResumeAllInterrupts();
1250 #ifdef _ARM_DS5_C_S32K3XX_
1251 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1252 #endif
1253 }
1254 }
1255
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_21(void)1256 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_21(void)
1257 {
1258 uint32 msr;
1259 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1260
1261 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId])
1262 {
1263 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1264 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1265 #else
1266 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1267 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1268 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1269 {
1270 OsIf_SuspendAllInterrupts();
1271 #ifdef _ARM_DS5_C_S32K3XX_
1272 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1273 #endif
1274 }
1275 msr_MCL_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1276 }
1277 reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId]++;
1278 }
1279
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_21(void)1280 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_21(void)
1281 {
1282 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1283
1284 reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId]--;
1285 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1286 {
1287 OsIf_ResumeAllInterrupts();
1288 #ifdef _ARM_DS5_C_S32K3XX_
1289 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1290 #endif
1291 }
1292 }
1293
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_22(void)1294 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_22(void)
1295 {
1296 uint32 msr;
1297 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1298
1299 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId])
1300 {
1301 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1302 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1303 #else
1304 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1305 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1306 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1307 {
1308 OsIf_SuspendAllInterrupts();
1309 #ifdef _ARM_DS5_C_S32K3XX_
1310 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1311 #endif
1312 }
1313 msr_MCL_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1314 }
1315 reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId]++;
1316 }
1317
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_22(void)1318 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_22(void)
1319 {
1320 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1321
1322 reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId]--;
1323 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1324 {
1325 OsIf_ResumeAllInterrupts();
1326 #ifdef _ARM_DS5_C_S32K3XX_
1327 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1328 #endif
1329 }
1330 }
1331
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_23(void)1332 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_23(void)
1333 {
1334 uint32 msr;
1335 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1336
1337 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId])
1338 {
1339 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1340 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1341 #else
1342 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1343 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1344 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1345 {
1346 OsIf_SuspendAllInterrupts();
1347 #ifdef _ARM_DS5_C_S32K3XX_
1348 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1349 #endif
1350 }
1351 msr_MCL_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1352 }
1353 reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId]++;
1354 }
1355
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_23(void)1356 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_23(void)
1357 {
1358 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1359
1360 reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId]--;
1361 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1362 {
1363 OsIf_ResumeAllInterrupts();
1364 #ifdef _ARM_DS5_C_S32K3XX_
1365 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1366 #endif
1367 }
1368 }
1369
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_24(void)1370 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_24(void)
1371 {
1372 uint32 msr;
1373 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1374
1375 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId])
1376 {
1377 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1378 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1379 #else
1380 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1381 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1382 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1383 {
1384 OsIf_SuspendAllInterrupts();
1385 #ifdef _ARM_DS5_C_S32K3XX_
1386 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1387 #endif
1388 }
1389 msr_MCL_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1390 }
1391 reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId]++;
1392 }
1393
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_24(void)1394 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_24(void)
1395 {
1396 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1397
1398 reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId]--;
1399 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1400 {
1401 OsIf_ResumeAllInterrupts();
1402 #ifdef _ARM_DS5_C_S32K3XX_
1403 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1404 #endif
1405 }
1406 }
1407
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_25(void)1408 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_25(void)
1409 {
1410 uint32 msr;
1411 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1412
1413 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId])
1414 {
1415 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1416 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1417 #else
1418 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1419 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1420 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1421 {
1422 OsIf_SuspendAllInterrupts();
1423 #ifdef _ARM_DS5_C_S32K3XX_
1424 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1425 #endif
1426 }
1427 msr_MCL_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1428 }
1429 reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId]++;
1430 }
1431
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_25(void)1432 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_25(void)
1433 {
1434 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1435
1436 reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId]--;
1437 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1438 {
1439 OsIf_ResumeAllInterrupts();
1440 #ifdef _ARM_DS5_C_S32K3XX_
1441 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1442 #endif
1443 }
1444 }
1445
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_26(void)1446 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_26(void)
1447 {
1448 uint32 msr;
1449 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1450
1451 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId])
1452 {
1453 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1454 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1455 #else
1456 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1457 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1458 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1459 {
1460 OsIf_SuspendAllInterrupts();
1461 #ifdef _ARM_DS5_C_S32K3XX_
1462 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1463 #endif
1464 }
1465 msr_MCL_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1466 }
1467 reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId]++;
1468 }
1469
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_26(void)1470 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_26(void)
1471 {
1472 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1473
1474 reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId]--;
1475 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1476 {
1477 OsIf_ResumeAllInterrupts();
1478 #ifdef _ARM_DS5_C_S32K3XX_
1479 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1480 #endif
1481 }
1482 }
1483
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_27(void)1484 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_27(void)
1485 {
1486 uint32 msr;
1487 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1488
1489 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId])
1490 {
1491 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1492 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1493 #else
1494 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1495 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1496 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1497 {
1498 OsIf_SuspendAllInterrupts();
1499 #ifdef _ARM_DS5_C_S32K3XX_
1500 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1501 #endif
1502 }
1503 msr_MCL_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1504 }
1505 reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId]++;
1506 }
1507
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_27(void)1508 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_27(void)
1509 {
1510 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1511
1512 reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId]--;
1513 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1514 {
1515 OsIf_ResumeAllInterrupts();
1516 #ifdef _ARM_DS5_C_S32K3XX_
1517 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1518 #endif
1519 }
1520 }
1521
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_28(void)1522 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_28(void)
1523 {
1524 uint32 msr;
1525 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1526
1527 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId])
1528 {
1529 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1530 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1531 #else
1532 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1533 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1534 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1535 {
1536 OsIf_SuspendAllInterrupts();
1537 #ifdef _ARM_DS5_C_S32K3XX_
1538 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1539 #endif
1540 }
1541 msr_MCL_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1542 }
1543 reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId]++;
1544 }
1545
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_28(void)1546 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_28(void)
1547 {
1548 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1549
1550 reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId]--;
1551 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1552 {
1553 OsIf_ResumeAllInterrupts();
1554 #ifdef _ARM_DS5_C_S32K3XX_
1555 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1556 #endif
1557 }
1558 }
1559
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_29(void)1560 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_29(void)
1561 {
1562 uint32 msr;
1563 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1564
1565 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId])
1566 {
1567 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1568 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1569 #else
1570 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1571 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1572 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1573 {
1574 OsIf_SuspendAllInterrupts();
1575 #ifdef _ARM_DS5_C_S32K3XX_
1576 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1577 #endif
1578 }
1579 msr_MCL_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1580 }
1581 reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId]++;
1582 }
1583
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_29(void)1584 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_29(void)
1585 {
1586 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1587
1588 reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId]--;
1589 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1590 {
1591 OsIf_ResumeAllInterrupts();
1592 #ifdef _ARM_DS5_C_S32K3XX_
1593 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1594 #endif
1595 }
1596 }
1597
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_30(void)1598 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_30(void)
1599 {
1600 uint32 msr;
1601 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1602
1603 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId])
1604 {
1605 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1606 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1607 #else
1608 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1609 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1610 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1611 {
1612 OsIf_SuspendAllInterrupts();
1613 #ifdef _ARM_DS5_C_S32K3XX_
1614 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1615 #endif
1616 }
1617 msr_MCL_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1618 }
1619 reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId]++;
1620 }
1621
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_30(void)1622 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_30(void)
1623 {
1624 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1625
1626 reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId]--;
1627 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1628 {
1629 OsIf_ResumeAllInterrupts();
1630 #ifdef _ARM_DS5_C_S32K3XX_
1631 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1632 #endif
1633 }
1634 }
1635
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_31(void)1636 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_31(void)
1637 {
1638 uint32 msr;
1639 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1640
1641 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId])
1642 {
1643 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1644 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1645 #else
1646 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1647 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1648 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1649 {
1650 OsIf_SuspendAllInterrupts();
1651 #ifdef _ARM_DS5_C_S32K3XX_
1652 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1653 #endif
1654 }
1655 msr_MCL_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1656 }
1657 reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId]++;
1658 }
1659
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_31(void)1660 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_31(void)
1661 {
1662 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1663
1664 reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId]--;
1665 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1666 {
1667 OsIf_ResumeAllInterrupts();
1668 #ifdef _ARM_DS5_C_S32K3XX_
1669 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1670 #endif
1671 }
1672 }
1673
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_32(void)1674 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_32(void)
1675 {
1676 uint32 msr;
1677 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1678
1679 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId])
1680 {
1681 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1682 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1683 #else
1684 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1685 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1686 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1687 {
1688 OsIf_SuspendAllInterrupts();
1689 #ifdef _ARM_DS5_C_S32K3XX_
1690 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1691 #endif
1692 }
1693 msr_MCL_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1694 }
1695 reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId]++;
1696 }
1697
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_32(void)1698 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_32(void)
1699 {
1700 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1701
1702 reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId]--;
1703 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1704 {
1705 OsIf_ResumeAllInterrupts();
1706 #ifdef _ARM_DS5_C_S32K3XX_
1707 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1708 #endif
1709 }
1710 }
1711
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_33(void)1712 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_33(void)
1713 {
1714 uint32 msr;
1715 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1716
1717 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId])
1718 {
1719 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1720 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1721 #else
1722 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1723 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1724 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1725 {
1726 OsIf_SuspendAllInterrupts();
1727 #ifdef _ARM_DS5_C_S32K3XX_
1728 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1729 #endif
1730 }
1731 msr_MCL_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1732 }
1733 reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId]++;
1734 }
1735
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_33(void)1736 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_33(void)
1737 {
1738 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1739
1740 reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId]--;
1741 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1742 {
1743 OsIf_ResumeAllInterrupts();
1744 #ifdef _ARM_DS5_C_S32K3XX_
1745 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1746 #endif
1747 }
1748 }
1749
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_34(void)1750 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_34(void)
1751 {
1752 uint32 msr;
1753 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1754
1755 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId])
1756 {
1757 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1758 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1759 #else
1760 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1761 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1762 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1763 {
1764 OsIf_SuspendAllInterrupts();
1765 #ifdef _ARM_DS5_C_S32K3XX_
1766 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1767 #endif
1768 }
1769 msr_MCL_EXCLUSIVE_AREA_34[u32CoreId] = msr;
1770 }
1771 reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId]++;
1772 }
1773
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_34(void)1774 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_34(void)
1775 {
1776 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1777
1778 reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId]--;
1779 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId])) /*if interrupts were enabled*/
1780 {
1781 OsIf_ResumeAllInterrupts();
1782 #ifdef _ARM_DS5_C_S32K3XX_
1783 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1784 #endif
1785 }
1786 }
1787
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_35(void)1788 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_35(void)
1789 {
1790 uint32 msr;
1791 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1792
1793 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId])
1794 {
1795 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1796 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1797 #else
1798 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1799 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1800 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1801 {
1802 OsIf_SuspendAllInterrupts();
1803 #ifdef _ARM_DS5_C_S32K3XX_
1804 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1805 #endif
1806 }
1807 msr_MCL_EXCLUSIVE_AREA_35[u32CoreId] = msr;
1808 }
1809 reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId]++;
1810 }
1811
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_35(void)1812 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_35(void)
1813 {
1814 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1815
1816 reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId]--;
1817 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId])) /*if interrupts were enabled*/
1818 {
1819 OsIf_ResumeAllInterrupts();
1820 #ifdef _ARM_DS5_C_S32K3XX_
1821 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1822 #endif
1823 }
1824 }
1825
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_36(void)1826 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_36(void)
1827 {
1828 uint32 msr;
1829 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1830
1831 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId])
1832 {
1833 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1834 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1835 #else
1836 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1837 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1838 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1839 {
1840 OsIf_SuspendAllInterrupts();
1841 #ifdef _ARM_DS5_C_S32K3XX_
1842 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1843 #endif
1844 }
1845 msr_MCL_EXCLUSIVE_AREA_36[u32CoreId] = msr;
1846 }
1847 reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId]++;
1848 }
1849
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_36(void)1850 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_36(void)
1851 {
1852 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1853
1854 reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId]--;
1855 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId])) /*if interrupts were enabled*/
1856 {
1857 OsIf_ResumeAllInterrupts();
1858 #ifdef _ARM_DS5_C_S32K3XX_
1859 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1860 #endif
1861 }
1862 }
1863
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_37(void)1864 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_37(void)
1865 {
1866 uint32 msr;
1867 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1868
1869 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId])
1870 {
1871 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1872 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1873 #else
1874 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1875 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1876 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1877 {
1878 OsIf_SuspendAllInterrupts();
1879 #ifdef _ARM_DS5_C_S32K3XX_
1880 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1881 #endif
1882 }
1883 msr_MCL_EXCLUSIVE_AREA_37[u32CoreId] = msr;
1884 }
1885 reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId]++;
1886 }
1887
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_37(void)1888 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_37(void)
1889 {
1890 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1891
1892 reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId]--;
1893 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_37[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId])) /*if interrupts were enabled*/
1894 {
1895 OsIf_ResumeAllInterrupts();
1896 #ifdef _ARM_DS5_C_S32K3XX_
1897 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1898 #endif
1899 }
1900 }
1901
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_38(void)1902 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_38(void)
1903 {
1904 uint32 msr;
1905 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1906
1907 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId])
1908 {
1909 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1910 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1911 #else
1912 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1913 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1914 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1915 {
1916 OsIf_SuspendAllInterrupts();
1917 #ifdef _ARM_DS5_C_S32K3XX_
1918 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1919 #endif
1920 }
1921 msr_MCL_EXCLUSIVE_AREA_38[u32CoreId] = msr;
1922 }
1923 reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId]++;
1924 }
1925
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_38(void)1926 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_38(void)
1927 {
1928 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1929
1930 reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId]--;
1931 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId])) /*if interrupts were enabled*/
1932 {
1933 OsIf_ResumeAllInterrupts();
1934 #ifdef _ARM_DS5_C_S32K3XX_
1935 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1936 #endif
1937 }
1938 }
1939
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_39(void)1940 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_39(void)
1941 {
1942 uint32 msr;
1943 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1944
1945 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId])
1946 {
1947 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1948 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1949 #else
1950 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1951 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1952 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1953 {
1954 OsIf_SuspendAllInterrupts();
1955 #ifdef _ARM_DS5_C_S32K3XX_
1956 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1957 #endif
1958 }
1959 msr_MCL_EXCLUSIVE_AREA_39[u32CoreId] = msr;
1960 }
1961 reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId]++;
1962 }
1963
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_39(void)1964 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_39(void)
1965 {
1966 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1967
1968 reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId]--;
1969 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId])) /*if interrupts were enabled*/
1970 {
1971 OsIf_ResumeAllInterrupts();
1972 #ifdef _ARM_DS5_C_S32K3XX_
1973 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1974 #endif
1975 }
1976 }
1977
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_40(void)1978 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_40(void)
1979 {
1980 uint32 msr;
1981 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1982
1983 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId])
1984 {
1985 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1986 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
1987 #else
1988 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
1989 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1990 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1991 {
1992 OsIf_SuspendAllInterrupts();
1993 #ifdef _ARM_DS5_C_S32K3XX_
1994 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1995 #endif
1996 }
1997 msr_MCL_EXCLUSIVE_AREA_40[u32CoreId] = msr;
1998 }
1999 reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId]++;
2000 }
2001
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_40(void)2002 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_40(void)
2003 {
2004 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2005
2006 reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId]--;
2007 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId])) /*if interrupts were enabled*/
2008 {
2009 OsIf_ResumeAllInterrupts();
2010 #ifdef _ARM_DS5_C_S32K3XX_
2011 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2012 #endif
2013 }
2014 }
2015
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_41(void)2016 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_41(void)
2017 {
2018 uint32 msr;
2019 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2020
2021 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId])
2022 {
2023 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2024 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2025 #else
2026 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2027 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2028 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2029 {
2030 OsIf_SuspendAllInterrupts();
2031 #ifdef _ARM_DS5_C_S32K3XX_
2032 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2033 #endif
2034 }
2035 msr_MCL_EXCLUSIVE_AREA_41[u32CoreId] = msr;
2036 }
2037 reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId]++;
2038 }
2039
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_41(void)2040 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_41(void)
2041 {
2042 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2043
2044 reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId]--;
2045 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId])) /*if interrupts were enabled*/
2046 {
2047 OsIf_ResumeAllInterrupts();
2048 #ifdef _ARM_DS5_C_S32K3XX_
2049 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2050 #endif
2051 }
2052 }
2053
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_42(void)2054 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_42(void)
2055 {
2056 uint32 msr;
2057 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2058
2059 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId])
2060 {
2061 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2062 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2063 #else
2064 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2065 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2066 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2067 {
2068 OsIf_SuspendAllInterrupts();
2069 #ifdef _ARM_DS5_C_S32K3XX_
2070 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2071 #endif
2072 }
2073 msr_MCL_EXCLUSIVE_AREA_42[u32CoreId] = msr;
2074 }
2075 reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId]++;
2076 }
2077
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_42(void)2078 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_42(void)
2079 {
2080 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2081
2082 reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId]--;
2083 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId])) /*if interrupts were enabled*/
2084 {
2085 OsIf_ResumeAllInterrupts();
2086 #ifdef _ARM_DS5_C_S32K3XX_
2087 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2088 #endif
2089 }
2090 }
2091
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_43(void)2092 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_43(void)
2093 {
2094 uint32 msr;
2095 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2096
2097 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId])
2098 {
2099 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2100 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2101 #else
2102 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2103 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2104 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2105 {
2106 OsIf_SuspendAllInterrupts();
2107 #ifdef _ARM_DS5_C_S32K3XX_
2108 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2109 #endif
2110 }
2111 msr_MCL_EXCLUSIVE_AREA_43[u32CoreId] = msr;
2112 }
2113 reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId]++;
2114 }
2115
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_43(void)2116 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_43(void)
2117 {
2118 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2119
2120 reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId]--;
2121 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId])) /*if interrupts were enabled*/
2122 {
2123 OsIf_ResumeAllInterrupts();
2124 #ifdef _ARM_DS5_C_S32K3XX_
2125 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2126 #endif
2127 }
2128 }
2129
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_44(void)2130 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_44(void)
2131 {
2132 uint32 msr;
2133 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2134
2135 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId])
2136 {
2137 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2138 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2139 #else
2140 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2141 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2142 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2143 {
2144 OsIf_SuspendAllInterrupts();
2145 #ifdef _ARM_DS5_C_S32K3XX_
2146 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2147 #endif
2148 }
2149 msr_MCL_EXCLUSIVE_AREA_44[u32CoreId] = msr;
2150 }
2151 reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId]++;
2152 }
2153
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_44(void)2154 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_44(void)
2155 {
2156 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2157
2158 reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId]--;
2159 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
2160 {
2161 OsIf_ResumeAllInterrupts();
2162 #ifdef _ARM_DS5_C_S32K3XX_
2163 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2164 #endif
2165 }
2166 }
2167
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_45(void)2168 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_45(void)
2169 {
2170 uint32 msr;
2171 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2172
2173 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId])
2174 {
2175 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2176 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2177 #else
2178 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2179 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2180 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2181 {
2182 OsIf_SuspendAllInterrupts();
2183 #ifdef _ARM_DS5_C_S32K3XX_
2184 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2185 #endif
2186 }
2187 msr_MCL_EXCLUSIVE_AREA_45[u32CoreId] = msr;
2188 }
2189 reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId]++;
2190 }
2191
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_45(void)2192 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_45(void)
2193 {
2194 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2195
2196 reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId]--;
2197 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
2198 {
2199 OsIf_ResumeAllInterrupts();
2200 #ifdef _ARM_DS5_C_S32K3XX_
2201 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2202 #endif
2203 }
2204 }
2205
SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_46(void)2206 void SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_46(void)
2207 {
2208 uint32 msr;
2209 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2210
2211 if(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId])
2212 {
2213 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2214 msr = OsIf_Trusted_Call_Return(Mcl_schm_read_msr);
2215 #else
2216 msr = Mcl_schm_read_msr(); /*read MSR (to store interrupts state)*/
2217 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2218 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2219 {
2220 OsIf_SuspendAllInterrupts();
2221 #ifdef _ARM_DS5_C_S32K3XX_
2222 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2223 #endif
2224 }
2225 msr_MCL_EXCLUSIVE_AREA_46[u32CoreId] = msr;
2226 }
2227 reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId]++;
2228 }
2229
SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_46(void)2230 void SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_46(void)
2231 {
2232 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2233
2234 reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId]--;
2235 if ((ISR_ON(msr_MCL_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
2236 {
2237 OsIf_ResumeAllInterrupts();
2238 #ifdef _ARM_DS5_C_S32K3XX_
2239 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2240 #endif
2241 }
2242 }
2243
2244
2245 #ifdef MCAL_TESTING_ENVIRONMENT
2246 /**
2247 @brief This function checks that all entered exclusive areas were also exited.
2248 @details This function checks that all entered exclusive areas were also exited. The check
2249 is done by verifying that all reentry_guard_* static variables are back to the
2250 zero value.
2251
2252 @param[in] void No input parameters
2253 @return void This function does not return a value. Test asserts are used instead.
2254
2255 @pre None
2256 @post None
2257
2258 @remarks Covers
2259 @remarks Implements
2260 */
SchM_Check_mcl(void)2261 void SchM_Check_mcl(void)
2262 {
2263 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2264
2265 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId]);
2266 reentry_guard_MCL_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_00 for the next test in the suite*/
2267
2268 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId]);
2269 reentry_guard_MCL_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_01 for the next test in the suite*/
2270
2271 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId]);
2272 reentry_guard_MCL_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_02 for the next test in the suite*/
2273
2274 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId]);
2275 reentry_guard_MCL_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_03 for the next test in the suite*/
2276
2277 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId]);
2278 reentry_guard_MCL_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_04 for the next test in the suite*/
2279
2280 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId]);
2281 reentry_guard_MCL_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_05 for the next test in the suite*/
2282
2283 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId]);
2284 reentry_guard_MCL_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_06 for the next test in the suite*/
2285
2286 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId]);
2287 reentry_guard_MCL_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_07 for the next test in the suite*/
2288
2289 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId]);
2290 reentry_guard_MCL_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_08 for the next test in the suite*/
2291
2292 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId]);
2293 reentry_guard_MCL_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_09 for the next test in the suite*/
2294
2295 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId]);
2296 reentry_guard_MCL_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_10 for the next test in the suite*/
2297
2298 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId]);
2299 reentry_guard_MCL_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_11 for the next test in the suite*/
2300
2301 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId]);
2302 reentry_guard_MCL_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_12 for the next test in the suite*/
2303
2304 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId]);
2305 reentry_guard_MCL_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_13 for the next test in the suite*/
2306
2307 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId]);
2308 reentry_guard_MCL_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_14 for the next test in the suite*/
2309
2310 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId]);
2311 reentry_guard_MCL_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_15 for the next test in the suite*/
2312
2313 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId]);
2314 reentry_guard_MCL_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_16 for the next test in the suite*/
2315
2316 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId]);
2317 reentry_guard_MCL_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_17 for the next test in the suite*/
2318
2319 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId]);
2320 reentry_guard_MCL_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_18 for the next test in the suite*/
2321
2322 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId]);
2323 reentry_guard_MCL_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_19 for the next test in the suite*/
2324
2325 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId]);
2326 reentry_guard_MCL_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_20 for the next test in the suite*/
2327
2328 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId]);
2329 reentry_guard_MCL_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_21 for the next test in the suite*/
2330
2331 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId]);
2332 reentry_guard_MCL_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_22 for the next test in the suite*/
2333
2334 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId]);
2335 reentry_guard_MCL_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_23 for the next test in the suite*/
2336
2337 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId]);
2338 reentry_guard_MCL_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_24 for the next test in the suite*/
2339
2340 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId]);
2341 reentry_guard_MCL_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_25 for the next test in the suite*/
2342
2343 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId]);
2344 reentry_guard_MCL_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_26 for the next test in the suite*/
2345
2346 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId]);
2347 reentry_guard_MCL_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_27 for the next test in the suite*/
2348
2349 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId]);
2350 reentry_guard_MCL_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_28 for the next test in the suite*/
2351
2352 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId]);
2353 reentry_guard_MCL_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_29 for the next test in the suite*/
2354
2355 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId]);
2356 reentry_guard_MCL_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_30 for the next test in the suite*/
2357
2358 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId]);
2359 reentry_guard_MCL_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_31 for the next test in the suite*/
2360
2361 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId]);
2362 reentry_guard_MCL_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_32 for the next test in the suite*/
2363
2364 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId]);
2365 reentry_guard_MCL_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_33 for the next test in the suite*/
2366
2367 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId]);
2368 reentry_guard_MCL_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_34 for the next test in the suite*/
2369
2370 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId]);
2371 reentry_guard_MCL_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_35 for the next test in the suite*/
2372
2373 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId]);
2374 reentry_guard_MCL_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_36 for the next test in the suite*/
2375
2376 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId]);
2377 reentry_guard_MCL_EXCLUSIVE_AREA_37[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_37 for the next test in the suite*/
2378
2379 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId]);
2380 reentry_guard_MCL_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_38 for the next test in the suite*/
2381
2382 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId]);
2383 reentry_guard_MCL_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_39 for the next test in the suite*/
2384
2385 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId]);
2386 reentry_guard_MCL_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_40 for the next test in the suite*/
2387
2388 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId]);
2389 reentry_guard_MCL_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_41 for the next test in the suite*/
2390
2391 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId]);
2392 reentry_guard_MCL_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_42 for the next test in the suite*/
2393
2394 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId]);
2395 reentry_guard_MCL_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_43 for the next test in the suite*/
2396
2397 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId]);
2398 reentry_guard_MCL_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_44 for the next test in the suite*/
2399
2400 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId]);
2401 reentry_guard_MCL_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_45 for the next test in the suite*/
2402
2403 EU_ASSERT(0UL == reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId]);
2404 reentry_guard_MCL_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_MCL_EXCLUSIVE_AREA_46 for the next test in the suite*/
2405
2406
2407 }
2408 #endif /*MCAL_TESTING_ENVIRONMENT*/
2409
2410 #define RTE_STOP_SEC_CODE
2411 #include "Rte_MemMap.h"
2412
2413 #ifdef __cplusplus
2414 }
2415 #endif
2416
2417 /** @} */
2418
