1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_Gpt.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_GPT_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_GPT_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_GPT_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_GPT_SW_MAJOR_VERSION_C 0
39 #define SCHM_GPT_SW_MINOR_VERSION_C 9
40 #define SCHM_GPT_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_00) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
98 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
99 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_01) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
100 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
101 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_02) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
102 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_03) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_04) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_05) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_06) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_07) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_10) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_11) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_12) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_17) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_21) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_22) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_23) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_24) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_25) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_26) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_27) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_28) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_29) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_30) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_31) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_35) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_35) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_36) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_36) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_38) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_38) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_40) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_40) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_41) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_41) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_42) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_42) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_43) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_43) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_44) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_45) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_46) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_50) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_51) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_52) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_52) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_53) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_53) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_54) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_54) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_55) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_55) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_56) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_56) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_60) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_60) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_61) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_61) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_62) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_62) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_63) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_63) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_64) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_64) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_65) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
188 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_65) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
189 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_66) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
190 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_66) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
191 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_67) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
192 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_67) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
193 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_68) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
194 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_68) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
195 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_69) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
196 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_69) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
197 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_70) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
198 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_70) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
199 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_71) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
200 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_71) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
201 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_72) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
202 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_72) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
203 VAR_SEC_NOCACHE(msr_GPT_EXCLUSIVE_AREA_73) static volatile uint32 msr_GPT_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
204 VAR_SEC_NOCACHE(reentry_guard_GPT_EXCLUSIVE_AREA_73) static volatile uint32 reentry_guard_GPT_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
205
206 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
207 #include "Rte_MemMap.h"
208 /*==================================================================================================
209 * GLOBAL CONSTANTS
210 ==================================================================================================*/
211
212
213 /*==================================================================================================
214 * GLOBAL VARIABLES
215 ==================================================================================================*/
216
217 /*==================================================================================================
218 * LOCAL FUNCTION PROTOTYPES
219 ==================================================================================================*/
220
221 #ifndef _COSMIC_C_S32ZE_
222 /*================================================================================================*/
223 /**
224 * @brief This function returns the MSR register value (32 bits).
225 * @details This function returns the MSR register value (32 bits).
226 *
227 * @param[in] void No input parameters
228 * @return uint32 msr This function returns the MSR register value (32 bits).
229 *
230 * @pre None
231 * @post None
232 *
233 */
234 uint32 Gpt_schm_read_msr(void);
235 #endif /*ifndef _COSMIC_C_S32ZE_*/
236 /*==================================================================================================
237 * LOCAL FUNCTIONS
238 ==================================================================================================*/
239 #define RTE_START_SEC_CODE
240 #include "Rte_MemMap.h"
241
242 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
243 /*================================================================================================*/
244 /**
245 * @brief This macro returns the MSR register value (32 bits).
246 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
247 *
248 * @pre None
249 * @post None
250 *
251 */
252 #ifdef MCAL_PLATFORM_ARM
253 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Gpt_schm_read_msr(void)254 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
255 {
256 mrs x0, S3_3_c4_c2_1
257 }
258 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Gpt_schm_read_msr(void)259 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
260 {
261 mrs r0, CPSR
262 }
263 #else
Gpt_schm_read_msr(void)264 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
265 {
266 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
267 mrs r0, BASEPRI
268 #else
269 mrs r0, PRIMASK
270 #endif
271 }
272 #endif
273 #else
274 #ifdef MCAL_PLATFORM_S12
Gpt_schm_read_msr(void)275 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
276 {
277 tfr ccr, d6
278 }
279 #else
Gpt_schm_read_msr(void)280 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
281 {
282 mfmsr r3
283 }
284 #endif
285 #endif
286 #endif /*#ifdef GHS||CW*/
287
288 #ifdef _DIABDATA_C_S32ZE_
289 /**
290 * @brief This function returns the MSR register value (32 bits).
291 * @details This function returns the MSR register value (32 bits).
292 *
293 * @param[in] void No input parameters
294 * @return uint32 msr This function returns the MSR register value (32 bits).
295 *
296 * @pre None
297 * @post None
298 *
299 */
300 #ifdef MCAL_PLATFORM_ARM
Gpt_schm_read_msr(void)301 uint32 Gpt_schm_read_msr(void)
302 {
303 register uint32 reg_tmp;
304 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
305 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
306 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
307 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
308 #else
309 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
310 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
311 #else
312 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
313 #endif
314 #endif
315 return (uint32)reg_tmp;
316 }
317 #else
Gpt_schm_read_msr(void)318 ASM_KEYWORD uint32 Gpt_schm_read_msr(void)
319 {
320 mfmsr r3
321 }
322 #endif /* MCAL_PLATFORM_ARM */
323
324 #endif /* _DIABDATA_C_S32ZE_*/
325
326 #ifdef _COSMIC_C_S32ZE_
327 /*================================================================================================*/
328 /**
329 * @brief This function returns the MSR register value (32 bits).
330 * @details This function returns the MSR register value (32 bits).
331 *
332 * @param[in] void No input parameters
333 * @return uint32 msr This function returns the MSR register value (32 bits).
334 *
335 * @pre None
336 * @post None
337 *
338 */
339
340 #ifdef MCAL_PLATFORM_S12
341 #define Gpt_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
342 #else
343 #define Gpt_schm_read_msr() ASM_KEYWORD("mfmsr r3")
344 #endif
345
346 #endif /*Cosmic compiler only*/
347
348
349 #ifdef _HITECH_C_S32ZE_
350 /*================================================================================================*/
351 /**
352 * @brief This function returns the MSR register value (32 bits).
353 * @details This function returns the MSR register value (32 bits).
354 *
355 * @param[in] void No input parameters
356 * @return uint32 msr This function returns the MSR register value (32 bits).
357 *
358 * @pre None
359 * @post None
360 *
361 */
Gpt_schm_read_msr(void)362 uint32 Gpt_schm_read_msr(void)
363 {
364 uint32 result;
365 __asm volatile("mfmsr %0" : "=r" (result) :);
366 return result;
367 }
368
369 #endif /*HighTec compiler only*/
370 /*================================================================================================*/
371 #ifdef _LINARO_C_S32ZE_
372 /**
373 * @brief This function returns the MSR register value (32 bits).
374 * @details This function returns the MSR register value (32 bits).
375 *
376 * @param[in] void No input parameters
377 * @return uint32 msr This function returns the MSR register value (32 bits).
378 *
379 * @pre None
380 * @post None
381 *
382 */
Gpt_schm_read_msr(void)383 uint32 Gpt_schm_read_msr(void)
384 {
385 register uint32 reg_tmp;
386 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
387 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
388 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
389 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
390 #else
391 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
392 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
393 #else
394 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
395 #endif
396 #endif
397 return (uint32)reg_tmp;
398 }
399 #endif /* _LINARO_C_S32ZE_*/
400 /*================================================================================================*/
401
402 #ifdef _ARM_DS5_C_S32ZE_
403 /**
404 * @brief This function returns the MSR register value (32 bits).
405 * @details This function returns the MSR register value (32 bits).
406 *
407 * @param[in] void No input parameters
408 * @return uint32 msr This function returns the MSR register value (32 bits).
409 *
410 * @pre None
411 * @post None
412 *
413 */
Gpt_schm_read_msr(void)414 uint32 Gpt_schm_read_msr(void)
415 {
416 register uint32 reg_tmp;
417 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
418 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
419 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
420 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
421 #else
422 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
423 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
424 #else
425 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
426 #endif
427 #endif
428 return (uint32)reg_tmp;
429 }
430 #endif /* _ARM_DS5_C_S32ZE_ */
431
432 #ifdef _IAR_C_S32ZE_
433 /**
434 * @brief This function returns the MSR register value (32 bits).
435 * @details This function returns the MSR register value (32 bits).
436 *
437 * @param[in] void No input parameters
438 * @return uint32 msr This function returns the MSR register value (32 bits).
439 *
440 * @pre None
441 * @post None
442 *
443 */
Gpt_schm_read_msr(void)444 uint32 Gpt_schm_read_msr(void)
445 {
446 register uint32 reg_tmp;
447
448 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
449 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
450 #else
451 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
452 #endif
453
454 return (uint32)reg_tmp;
455 }
456 #endif /* _IAR_C_S32ZE_ */
457
458 #define RTE_STOP_SEC_CODE
459 #include "Rte_MemMap.h"
460
461 /*==================================================================================================
462 * GLOBAL FUNCTIONS
463 ==================================================================================================*/
464 #define RTE_START_SEC_CODE
465 #include "Rte_MemMap.h"
466
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_00(void)467 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_00(void)
468 {
469 uint32 msr;
470 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
471
472 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId])
473 {
474 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
475 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
476 #else
477 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
478 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
479 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
480 {
481 OsIf_SuspendAllInterrupts();
482 #ifdef _ARM_DS5_C_S32ZE_
483 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
484 #endif
485 }
486 msr_GPT_EXCLUSIVE_AREA_00[u32CoreId] = msr;
487 }
488 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]++;
489 }
490
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_00(void)491 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_00(void)
492 {
493 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
494
495 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]--;
496 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
497 {
498 OsIf_ResumeAllInterrupts();
499 #ifdef _ARM_DS5_C_S32ZE_
500 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
501 #endif
502 }
503 }
504
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_01(void)505 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_01(void)
506 {
507 uint32 msr;
508 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
509
510 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId])
511 {
512 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
513 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
514 #else
515 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
516 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
517 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
518 {
519 OsIf_SuspendAllInterrupts();
520 #ifdef _ARM_DS5_C_S32ZE_
521 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
522 #endif
523 }
524 msr_GPT_EXCLUSIVE_AREA_01[u32CoreId] = msr;
525 }
526 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]++;
527 }
528
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_01(void)529 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_01(void)
530 {
531 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
532
533 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]--;
534 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
535 {
536 OsIf_ResumeAllInterrupts();
537 #ifdef _ARM_DS5_C_S32ZE_
538 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
539 #endif
540 }
541 }
542
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_02(void)543 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_02(void)
544 {
545 uint32 msr;
546 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
547
548 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId])
549 {
550 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
551 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
552 #else
553 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
554 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
555 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
556 {
557 OsIf_SuspendAllInterrupts();
558 #ifdef _ARM_DS5_C_S32ZE_
559 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
560 #endif
561 }
562 msr_GPT_EXCLUSIVE_AREA_02[u32CoreId] = msr;
563 }
564 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]++;
565 }
566
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_02(void)567 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_02(void)
568 {
569 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
570
571 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]--;
572 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
573 {
574 OsIf_ResumeAllInterrupts();
575 #ifdef _ARM_DS5_C_S32ZE_
576 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
577 #endif
578 }
579 }
580
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_03(void)581 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_03(void)
582 {
583 uint32 msr;
584 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
585
586 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId])
587 {
588 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
589 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
590 #else
591 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
592 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
593 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
594 {
595 OsIf_SuspendAllInterrupts();
596 #ifdef _ARM_DS5_C_S32ZE_
597 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
598 #endif
599 }
600 msr_GPT_EXCLUSIVE_AREA_03[u32CoreId] = msr;
601 }
602 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]++;
603 }
604
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_03(void)605 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_03(void)
606 {
607 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
608
609 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]--;
610 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
611 {
612 OsIf_ResumeAllInterrupts();
613 #ifdef _ARM_DS5_C_S32ZE_
614 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
615 #endif
616 }
617 }
618
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_04(void)619 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_04(void)
620 {
621 uint32 msr;
622 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
623
624 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId])
625 {
626 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
627 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
628 #else
629 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
630 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
631 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
632 {
633 OsIf_SuspendAllInterrupts();
634 #ifdef _ARM_DS5_C_S32ZE_
635 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
636 #endif
637 }
638 msr_GPT_EXCLUSIVE_AREA_04[u32CoreId] = msr;
639 }
640 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]++;
641 }
642
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_04(void)643 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_04(void)
644 {
645 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
646
647 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]--;
648 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
649 {
650 OsIf_ResumeAllInterrupts();
651 #ifdef _ARM_DS5_C_S32ZE_
652 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
653 #endif
654 }
655 }
656
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_05(void)657 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_05(void)
658 {
659 uint32 msr;
660 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
661
662 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId])
663 {
664 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
665 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
666 #else
667 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
668 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
669 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
670 {
671 OsIf_SuspendAllInterrupts();
672 #ifdef _ARM_DS5_C_S32ZE_
673 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
674 #endif
675 }
676 msr_GPT_EXCLUSIVE_AREA_05[u32CoreId] = msr;
677 }
678 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]++;
679 }
680
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_05(void)681 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_05(void)
682 {
683 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
684
685 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]--;
686 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
687 {
688 OsIf_ResumeAllInterrupts();
689 #ifdef _ARM_DS5_C_S32ZE_
690 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
691 #endif
692 }
693 }
694
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_06(void)695 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_06(void)
696 {
697 uint32 msr;
698 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
699
700 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId])
701 {
702 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
703 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
704 #else
705 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
706 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
707 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
708 {
709 OsIf_SuspendAllInterrupts();
710 #ifdef _ARM_DS5_C_S32ZE_
711 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
712 #endif
713 }
714 msr_GPT_EXCLUSIVE_AREA_06[u32CoreId] = msr;
715 }
716 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]++;
717 }
718
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_06(void)719 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_06(void)
720 {
721 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
722
723 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]--;
724 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
725 {
726 OsIf_ResumeAllInterrupts();
727 #ifdef _ARM_DS5_C_S32ZE_
728 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
729 #endif
730 }
731 }
732
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_07(void)733 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_07(void)
734 {
735 uint32 msr;
736 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
737
738 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId])
739 {
740 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
741 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
742 #else
743 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
744 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
745 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
746 {
747 OsIf_SuspendAllInterrupts();
748 #ifdef _ARM_DS5_C_S32ZE_
749 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
750 #endif
751 }
752 msr_GPT_EXCLUSIVE_AREA_07[u32CoreId] = msr;
753 }
754 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]++;
755 }
756
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_07(void)757 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_07(void)
758 {
759 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
760
761 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]--;
762 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
763 {
764 OsIf_ResumeAllInterrupts();
765 #ifdef _ARM_DS5_C_S32ZE_
766 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
767 #endif
768 }
769 }
770
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_10(void)771 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_10(void)
772 {
773 uint32 msr;
774 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
775
776 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId])
777 {
778 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
779 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
780 #else
781 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
782 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
783 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
784 {
785 OsIf_SuspendAllInterrupts();
786 #ifdef _ARM_DS5_C_S32ZE_
787 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
788 #endif
789 }
790 msr_GPT_EXCLUSIVE_AREA_10[u32CoreId] = msr;
791 }
792 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]++;
793 }
794
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_10(void)795 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_10(void)
796 {
797 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
798
799 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]--;
800 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
801 {
802 OsIf_ResumeAllInterrupts();
803 #ifdef _ARM_DS5_C_S32ZE_
804 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
805 #endif
806 }
807 }
808
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_11(void)809 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_11(void)
810 {
811 uint32 msr;
812 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
813
814 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId])
815 {
816 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
817 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
818 #else
819 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
820 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
821 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
822 {
823 OsIf_SuspendAllInterrupts();
824 #ifdef _ARM_DS5_C_S32ZE_
825 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
826 #endif
827 }
828 msr_GPT_EXCLUSIVE_AREA_11[u32CoreId] = msr;
829 }
830 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]++;
831 }
832
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_11(void)833 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_11(void)
834 {
835 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
836
837 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]--;
838 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
839 {
840 OsIf_ResumeAllInterrupts();
841 #ifdef _ARM_DS5_C_S32ZE_
842 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
843 #endif
844 }
845 }
846
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_12(void)847 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_12(void)
848 {
849 uint32 msr;
850 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
851
852 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId])
853 {
854 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
855 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
856 #else
857 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
858 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
859 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
860 {
861 OsIf_SuspendAllInterrupts();
862 #ifdef _ARM_DS5_C_S32ZE_
863 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
864 #endif
865 }
866 msr_GPT_EXCLUSIVE_AREA_12[u32CoreId] = msr;
867 }
868 reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId]++;
869 }
870
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_12(void)871 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_12(void)
872 {
873 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
874
875 reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId]--;
876 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
877 {
878 OsIf_ResumeAllInterrupts();
879 #ifdef _ARM_DS5_C_S32ZE_
880 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
881 #endif
882 }
883 }
884
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_17(void)885 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_17(void)
886 {
887 uint32 msr;
888 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
889
890 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId])
891 {
892 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
893 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
894 #else
895 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
896 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
897 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
898 {
899 OsIf_SuspendAllInterrupts();
900 #ifdef _ARM_DS5_C_S32ZE_
901 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
902 #endif
903 }
904 msr_GPT_EXCLUSIVE_AREA_17[u32CoreId] = msr;
905 }
906 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]++;
907 }
908
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_17(void)909 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_17(void)
910 {
911 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
912
913 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]--;
914 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
915 {
916 OsIf_ResumeAllInterrupts();
917 #ifdef _ARM_DS5_C_S32ZE_
918 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
919 #endif
920 }
921 }
922
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_21(void)923 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_21(void)
924 {
925 uint32 msr;
926 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
927
928 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId])
929 {
930 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
931 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
932 #else
933 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
934 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
935 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
936 {
937 OsIf_SuspendAllInterrupts();
938 #ifdef _ARM_DS5_C_S32ZE_
939 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
940 #endif
941 }
942 msr_GPT_EXCLUSIVE_AREA_21[u32CoreId] = msr;
943 }
944 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]++;
945 }
946
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_21(void)947 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_21(void)
948 {
949 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
950
951 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]--;
952 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
953 {
954 OsIf_ResumeAllInterrupts();
955 #ifdef _ARM_DS5_C_S32ZE_
956 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
957 #endif
958 }
959 }
960
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_22(void)961 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_22(void)
962 {
963 uint32 msr;
964 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
965
966 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId])
967 {
968 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
969 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
970 #else
971 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
972 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
973 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
974 {
975 OsIf_SuspendAllInterrupts();
976 #ifdef _ARM_DS5_C_S32ZE_
977 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
978 #endif
979 }
980 msr_GPT_EXCLUSIVE_AREA_22[u32CoreId] = msr;
981 }
982 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]++;
983 }
984
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_22(void)985 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_22(void)
986 {
987 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
988
989 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]--;
990 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
991 {
992 OsIf_ResumeAllInterrupts();
993 #ifdef _ARM_DS5_C_S32ZE_
994 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
995 #endif
996 }
997 }
998
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_23(void)999 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_23(void)
1000 {
1001 uint32 msr;
1002 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1003
1004 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId])
1005 {
1006 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1007 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1008 #else
1009 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1010 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1011 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1012 {
1013 OsIf_SuspendAllInterrupts();
1014 #ifdef _ARM_DS5_C_S32ZE_
1015 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1016 #endif
1017 }
1018 msr_GPT_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1019 }
1020 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]++;
1021 }
1022
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_23(void)1023 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_23(void)
1024 {
1025 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1026
1027 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]--;
1028 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1029 {
1030 OsIf_ResumeAllInterrupts();
1031 #ifdef _ARM_DS5_C_S32ZE_
1032 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1033 #endif
1034 }
1035 }
1036
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_24(void)1037 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_24(void)
1038 {
1039 uint32 msr;
1040 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1041
1042 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId])
1043 {
1044 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1045 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1046 #else
1047 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1048 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1049 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1050 {
1051 OsIf_SuspendAllInterrupts();
1052 #ifdef _ARM_DS5_C_S32ZE_
1053 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1054 #endif
1055 }
1056 msr_GPT_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1057 }
1058 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]++;
1059 }
1060
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_24(void)1061 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_24(void)
1062 {
1063 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1064
1065 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]--;
1066 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1067 {
1068 OsIf_ResumeAllInterrupts();
1069 #ifdef _ARM_DS5_C_S32ZE_
1070 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1071 #endif
1072 }
1073 }
1074
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_25(void)1075 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_25(void)
1076 {
1077 uint32 msr;
1078 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1079
1080 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId])
1081 {
1082 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1083 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1084 #else
1085 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1086 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1087 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1088 {
1089 OsIf_SuspendAllInterrupts();
1090 #ifdef _ARM_DS5_C_S32ZE_
1091 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1092 #endif
1093 }
1094 msr_GPT_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1095 }
1096 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]++;
1097 }
1098
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_25(void)1099 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_25(void)
1100 {
1101 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1102
1103 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]--;
1104 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1105 {
1106 OsIf_ResumeAllInterrupts();
1107 #ifdef _ARM_DS5_C_S32ZE_
1108 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1109 #endif
1110 }
1111 }
1112
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_26(void)1113 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_26(void)
1114 {
1115 uint32 msr;
1116 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1117
1118 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId])
1119 {
1120 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1121 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1122 #else
1123 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1124 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1125 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1126 {
1127 OsIf_SuspendAllInterrupts();
1128 #ifdef _ARM_DS5_C_S32ZE_
1129 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1130 #endif
1131 }
1132 msr_GPT_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1133 }
1134 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]++;
1135 }
1136
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_26(void)1137 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_26(void)
1138 {
1139 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1140
1141 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]--;
1142 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1143 {
1144 OsIf_ResumeAllInterrupts();
1145 #ifdef _ARM_DS5_C_S32ZE_
1146 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1147 #endif
1148 }
1149 }
1150
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_27(void)1151 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_27(void)
1152 {
1153 uint32 msr;
1154 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1155
1156 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId])
1157 {
1158 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1159 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1160 #else
1161 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1162 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1163 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1164 {
1165 OsIf_SuspendAllInterrupts();
1166 #ifdef _ARM_DS5_C_S32ZE_
1167 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1168 #endif
1169 }
1170 msr_GPT_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1171 }
1172 reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId]++;
1173 }
1174
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_27(void)1175 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_27(void)
1176 {
1177 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1178
1179 reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId]--;
1180 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1181 {
1182 OsIf_ResumeAllInterrupts();
1183 #ifdef _ARM_DS5_C_S32ZE_
1184 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1185 #endif
1186 }
1187 }
1188
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_28(void)1189 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_28(void)
1190 {
1191 uint32 msr;
1192 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1193
1194 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId])
1195 {
1196 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1197 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1198 #else
1199 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1200 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1201 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1202 {
1203 OsIf_SuspendAllInterrupts();
1204 #ifdef _ARM_DS5_C_S32ZE_
1205 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1206 #endif
1207 }
1208 msr_GPT_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1209 }
1210 reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId]++;
1211 }
1212
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_28(void)1213 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_28(void)
1214 {
1215 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1216
1217 reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId]--;
1218 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1219 {
1220 OsIf_ResumeAllInterrupts();
1221 #ifdef _ARM_DS5_C_S32ZE_
1222 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1223 #endif
1224 }
1225 }
1226
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_29(void)1227 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_29(void)
1228 {
1229 uint32 msr;
1230 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1231
1232 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId])
1233 {
1234 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1235 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1236 #else
1237 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1238 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1239 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1240 {
1241 OsIf_SuspendAllInterrupts();
1242 #ifdef _ARM_DS5_C_S32ZE_
1243 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1244 #endif
1245 }
1246 msr_GPT_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1247 }
1248 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]++;
1249 }
1250
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_29(void)1251 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_29(void)
1252 {
1253 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1254
1255 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]--;
1256 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1257 {
1258 OsIf_ResumeAllInterrupts();
1259 #ifdef _ARM_DS5_C_S32ZE_
1260 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1261 #endif
1262 }
1263 }
1264
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_30(void)1265 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_30(void)
1266 {
1267 uint32 msr;
1268 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1269
1270 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId])
1271 {
1272 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1273 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1274 #else
1275 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1276 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1277 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1278 {
1279 OsIf_SuspendAllInterrupts();
1280 #ifdef _ARM_DS5_C_S32ZE_
1281 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1282 #endif
1283 }
1284 msr_GPT_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1285 }
1286 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]++;
1287 }
1288
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_30(void)1289 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_30(void)
1290 {
1291 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1292
1293 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]--;
1294 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1295 {
1296 OsIf_ResumeAllInterrupts();
1297 #ifdef _ARM_DS5_C_S32ZE_
1298 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1299 #endif
1300 }
1301 }
1302
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_31(void)1303 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_31(void)
1304 {
1305 uint32 msr;
1306 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1307
1308 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId])
1309 {
1310 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1311 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1312 #else
1313 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1314 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1315 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1316 {
1317 OsIf_SuspendAllInterrupts();
1318 #ifdef _ARM_DS5_C_S32ZE_
1319 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1320 #endif
1321 }
1322 msr_GPT_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1323 }
1324 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]++;
1325 }
1326
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_31(void)1327 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_31(void)
1328 {
1329 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1330
1331 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]--;
1332 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1333 {
1334 OsIf_ResumeAllInterrupts();
1335 #ifdef _ARM_DS5_C_S32ZE_
1336 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1337 #endif
1338 }
1339 }
1340
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_35(void)1341 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_35(void)
1342 {
1343 uint32 msr;
1344 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1345
1346 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId])
1347 {
1348 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1349 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1350 #else
1351 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1352 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1353 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1354 {
1355 OsIf_SuspendAllInterrupts();
1356 #ifdef _ARM_DS5_C_S32ZE_
1357 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1358 #endif
1359 }
1360 msr_GPT_EXCLUSIVE_AREA_35[u32CoreId] = msr;
1361 }
1362 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]++;
1363 }
1364
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_35(void)1365 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_35(void)
1366 {
1367 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1368
1369 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]--;
1370 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId])) /*if interrupts were enabled*/
1371 {
1372 OsIf_ResumeAllInterrupts();
1373 #ifdef _ARM_DS5_C_S32ZE_
1374 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1375 #endif
1376 }
1377 }
1378
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_36(void)1379 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_36(void)
1380 {
1381 uint32 msr;
1382 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1383
1384 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId])
1385 {
1386 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1387 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1388 #else
1389 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1390 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1391 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1392 {
1393 OsIf_SuspendAllInterrupts();
1394 #ifdef _ARM_DS5_C_S32ZE_
1395 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1396 #endif
1397 }
1398 msr_GPT_EXCLUSIVE_AREA_36[u32CoreId] = msr;
1399 }
1400 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]++;
1401 }
1402
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_36(void)1403 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_36(void)
1404 {
1405 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1406
1407 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]--;
1408 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId])) /*if interrupts were enabled*/
1409 {
1410 OsIf_ResumeAllInterrupts();
1411 #ifdef _ARM_DS5_C_S32ZE_
1412 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1413 #endif
1414 }
1415 }
1416
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_38(void)1417 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_38(void)
1418 {
1419 uint32 msr;
1420 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1421
1422 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId])
1423 {
1424 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1425 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1426 #else
1427 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1428 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1429 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1430 {
1431 OsIf_SuspendAllInterrupts();
1432 #ifdef _ARM_DS5_C_S32ZE_
1433 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1434 #endif
1435 }
1436 msr_GPT_EXCLUSIVE_AREA_38[u32CoreId] = msr;
1437 }
1438 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]++;
1439 }
1440
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_38(void)1441 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_38(void)
1442 {
1443 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1444
1445 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]--;
1446 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId])) /*if interrupts were enabled*/
1447 {
1448 OsIf_ResumeAllInterrupts();
1449 #ifdef _ARM_DS5_C_S32ZE_
1450 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1451 #endif
1452 }
1453 }
1454
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_40(void)1455 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_40(void)
1456 {
1457 uint32 msr;
1458 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1459
1460 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId])
1461 {
1462 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1463 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1464 #else
1465 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1466 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1467 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1468 {
1469 OsIf_SuspendAllInterrupts();
1470 #ifdef _ARM_DS5_C_S32ZE_
1471 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1472 #endif
1473 }
1474 msr_GPT_EXCLUSIVE_AREA_40[u32CoreId] = msr;
1475 }
1476 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]++;
1477 }
1478
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_40(void)1479 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_40(void)
1480 {
1481 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1482
1483 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]--;
1484 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId])) /*if interrupts were enabled*/
1485 {
1486 OsIf_ResumeAllInterrupts();
1487 #ifdef _ARM_DS5_C_S32ZE_
1488 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1489 #endif
1490 }
1491 }
1492
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_41(void)1493 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_41(void)
1494 {
1495 uint32 msr;
1496 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1497
1498 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId])
1499 {
1500 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1501 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1502 #else
1503 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1504 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1505 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1506 {
1507 OsIf_SuspendAllInterrupts();
1508 #ifdef _ARM_DS5_C_S32ZE_
1509 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1510 #endif
1511 }
1512 msr_GPT_EXCLUSIVE_AREA_41[u32CoreId] = msr;
1513 }
1514 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]++;
1515 }
1516
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_41(void)1517 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_41(void)
1518 {
1519 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1520
1521 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]--;
1522 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId])) /*if interrupts were enabled*/
1523 {
1524 OsIf_ResumeAllInterrupts();
1525 #ifdef _ARM_DS5_C_S32ZE_
1526 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1527 #endif
1528 }
1529 }
1530
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_42(void)1531 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_42(void)
1532 {
1533 uint32 msr;
1534 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1535
1536 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId])
1537 {
1538 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1539 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1540 #else
1541 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1542 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1543 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1544 {
1545 OsIf_SuspendAllInterrupts();
1546 #ifdef _ARM_DS5_C_S32ZE_
1547 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1548 #endif
1549 }
1550 msr_GPT_EXCLUSIVE_AREA_42[u32CoreId] = msr;
1551 }
1552 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]++;
1553 }
1554
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_42(void)1555 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_42(void)
1556 {
1557 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1558
1559 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]--;
1560 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId])) /*if interrupts were enabled*/
1561 {
1562 OsIf_ResumeAllInterrupts();
1563 #ifdef _ARM_DS5_C_S32ZE_
1564 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1565 #endif
1566 }
1567 }
1568
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_43(void)1569 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_43(void)
1570 {
1571 uint32 msr;
1572 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1573
1574 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId])
1575 {
1576 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1577 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1578 #else
1579 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1580 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1581 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1582 {
1583 OsIf_SuspendAllInterrupts();
1584 #ifdef _ARM_DS5_C_S32ZE_
1585 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1586 #endif
1587 }
1588 msr_GPT_EXCLUSIVE_AREA_43[u32CoreId] = msr;
1589 }
1590 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]++;
1591 }
1592
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_43(void)1593 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_43(void)
1594 {
1595 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1596
1597 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]--;
1598 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId])) /*if interrupts were enabled*/
1599 {
1600 OsIf_ResumeAllInterrupts();
1601 #ifdef _ARM_DS5_C_S32ZE_
1602 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1603 #endif
1604 }
1605 }
1606
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_44(void)1607 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_44(void)
1608 {
1609 uint32 msr;
1610 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1611
1612 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId])
1613 {
1614 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1615 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1616 #else
1617 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1618 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1619 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1620 {
1621 OsIf_SuspendAllInterrupts();
1622 #ifdef _ARM_DS5_C_S32ZE_
1623 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1624 #endif
1625 }
1626 msr_GPT_EXCLUSIVE_AREA_44[u32CoreId] = msr;
1627 }
1628 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]++;
1629 }
1630
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_44(void)1631 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_44(void)
1632 {
1633 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1634
1635 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]--;
1636 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
1637 {
1638 OsIf_ResumeAllInterrupts();
1639 #ifdef _ARM_DS5_C_S32ZE_
1640 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1641 #endif
1642 }
1643 }
1644
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_45(void)1645 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_45(void)
1646 {
1647 uint32 msr;
1648 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1649
1650 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId])
1651 {
1652 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1653 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1654 #else
1655 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1656 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1657 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1658 {
1659 OsIf_SuspendAllInterrupts();
1660 #ifdef _ARM_DS5_C_S32ZE_
1661 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1662 #endif
1663 }
1664 msr_GPT_EXCLUSIVE_AREA_45[u32CoreId] = msr;
1665 }
1666 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]++;
1667 }
1668
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_45(void)1669 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_45(void)
1670 {
1671 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1672
1673 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]--;
1674 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
1675 {
1676 OsIf_ResumeAllInterrupts();
1677 #ifdef _ARM_DS5_C_S32ZE_
1678 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1679 #endif
1680 }
1681 }
1682
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_46(void)1683 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_46(void)
1684 {
1685 uint32 msr;
1686 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1687
1688 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId])
1689 {
1690 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1691 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1692 #else
1693 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1694 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1695 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1696 {
1697 OsIf_SuspendAllInterrupts();
1698 #ifdef _ARM_DS5_C_S32ZE_
1699 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1700 #endif
1701 }
1702 msr_GPT_EXCLUSIVE_AREA_46[u32CoreId] = msr;
1703 }
1704 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]++;
1705 }
1706
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_46(void)1707 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_46(void)
1708 {
1709 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1710
1711 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]--;
1712 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
1713 {
1714 OsIf_ResumeAllInterrupts();
1715 #ifdef _ARM_DS5_C_S32ZE_
1716 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1717 #endif
1718 }
1719 }
1720
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_50(void)1721 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_50(void)
1722 {
1723 uint32 msr;
1724 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1725
1726 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId])
1727 {
1728 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1729 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1730 #else
1731 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1732 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1733 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1734 {
1735 OsIf_SuspendAllInterrupts();
1736 #ifdef _ARM_DS5_C_S32ZE_
1737 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1738 #endif
1739 }
1740 msr_GPT_EXCLUSIVE_AREA_50[u32CoreId] = msr;
1741 }
1742 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]++;
1743 }
1744
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_50(void)1745 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_50(void)
1746 {
1747 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1748
1749 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]--;
1750 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
1751 {
1752 OsIf_ResumeAllInterrupts();
1753 #ifdef _ARM_DS5_C_S32ZE_
1754 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1755 #endif
1756 }
1757 }
1758
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_51(void)1759 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_51(void)
1760 {
1761 uint32 msr;
1762 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1763
1764 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId])
1765 {
1766 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1767 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1768 #else
1769 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1770 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1771 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1772 {
1773 OsIf_SuspendAllInterrupts();
1774 #ifdef _ARM_DS5_C_S32ZE_
1775 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1776 #endif
1777 }
1778 msr_GPT_EXCLUSIVE_AREA_51[u32CoreId] = msr;
1779 }
1780 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]++;
1781 }
1782
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_51(void)1783 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_51(void)
1784 {
1785 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1786
1787 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]--;
1788 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
1789 {
1790 OsIf_ResumeAllInterrupts();
1791 #ifdef _ARM_DS5_C_S32ZE_
1792 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1793 #endif
1794 }
1795 }
1796
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_52(void)1797 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_52(void)
1798 {
1799 uint32 msr;
1800 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1801
1802 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId])
1803 {
1804 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1805 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1806 #else
1807 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1808 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1809 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1810 {
1811 OsIf_SuspendAllInterrupts();
1812 #ifdef _ARM_DS5_C_S32ZE_
1813 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1814 #endif
1815 }
1816 msr_GPT_EXCLUSIVE_AREA_52[u32CoreId] = msr;
1817 }
1818 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]++;
1819 }
1820
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_52(void)1821 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_52(void)
1822 {
1823 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1824
1825 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]--;
1826 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_52[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId])) /*if interrupts were enabled*/
1827 {
1828 OsIf_ResumeAllInterrupts();
1829 #ifdef _ARM_DS5_C_S32ZE_
1830 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1831 #endif
1832 }
1833 }
1834
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_53(void)1835 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_53(void)
1836 {
1837 uint32 msr;
1838 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1839
1840 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId])
1841 {
1842 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1843 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1844 #else
1845 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1846 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1847 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1848 {
1849 OsIf_SuspendAllInterrupts();
1850 #ifdef _ARM_DS5_C_S32ZE_
1851 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1852 #endif
1853 }
1854 msr_GPT_EXCLUSIVE_AREA_53[u32CoreId] = msr;
1855 }
1856 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]++;
1857 }
1858
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_53(void)1859 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_53(void)
1860 {
1861 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1862
1863 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]--;
1864 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_53[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId])) /*if interrupts were enabled*/
1865 {
1866 OsIf_ResumeAllInterrupts();
1867 #ifdef _ARM_DS5_C_S32ZE_
1868 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1869 #endif
1870 }
1871 }
1872
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_54(void)1873 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_54(void)
1874 {
1875 uint32 msr;
1876 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1877
1878 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId])
1879 {
1880 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1881 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1882 #else
1883 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1884 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1885 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1886 {
1887 OsIf_SuspendAllInterrupts();
1888 #ifdef _ARM_DS5_C_S32ZE_
1889 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1890 #endif
1891 }
1892 msr_GPT_EXCLUSIVE_AREA_54[u32CoreId] = msr;
1893 }
1894 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]++;
1895 }
1896
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_54(void)1897 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_54(void)
1898 {
1899 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1900
1901 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]--;
1902 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId])) /*if interrupts were enabled*/
1903 {
1904 OsIf_ResumeAllInterrupts();
1905 #ifdef _ARM_DS5_C_S32ZE_
1906 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1907 #endif
1908 }
1909 }
1910
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_55(void)1911 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_55(void)
1912 {
1913 uint32 msr;
1914 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1915
1916 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId])
1917 {
1918 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1919 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1920 #else
1921 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1922 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1923 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1924 {
1925 OsIf_SuspendAllInterrupts();
1926 #ifdef _ARM_DS5_C_S32ZE_
1927 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1928 #endif
1929 }
1930 msr_GPT_EXCLUSIVE_AREA_55[u32CoreId] = msr;
1931 }
1932 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]++;
1933 }
1934
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_55(void)1935 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_55(void)
1936 {
1937 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1938
1939 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]--;
1940 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId])) /*if interrupts were enabled*/
1941 {
1942 OsIf_ResumeAllInterrupts();
1943 #ifdef _ARM_DS5_C_S32ZE_
1944 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1945 #endif
1946 }
1947 }
1948
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_56(void)1949 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_56(void)
1950 {
1951 uint32 msr;
1952 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1953
1954 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId])
1955 {
1956 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1957 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1958 #else
1959 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1960 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1961 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1962 {
1963 OsIf_SuspendAllInterrupts();
1964 #ifdef _ARM_DS5_C_S32ZE_
1965 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1966 #endif
1967 }
1968 msr_GPT_EXCLUSIVE_AREA_56[u32CoreId] = msr;
1969 }
1970 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]++;
1971 }
1972
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_56(void)1973 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_56(void)
1974 {
1975 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1976
1977 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]--;
1978 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId])) /*if interrupts were enabled*/
1979 {
1980 OsIf_ResumeAllInterrupts();
1981 #ifdef _ARM_DS5_C_S32ZE_
1982 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1983 #endif
1984 }
1985 }
1986
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_60(void)1987 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_60(void)
1988 {
1989 uint32 msr;
1990 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1991
1992 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId])
1993 {
1994 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1995 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
1996 #else
1997 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
1998 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1999 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2000 {
2001 OsIf_SuspendAllInterrupts();
2002 #ifdef _ARM_DS5_C_S32ZE_
2003 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2004 #endif
2005 }
2006 msr_GPT_EXCLUSIVE_AREA_60[u32CoreId] = msr;
2007 }
2008 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]++;
2009 }
2010
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_60(void)2011 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_60(void)
2012 {
2013 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2014
2015 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]--;
2016 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId])) /*if interrupts were enabled*/
2017 {
2018 OsIf_ResumeAllInterrupts();
2019 #ifdef _ARM_DS5_C_S32ZE_
2020 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2021 #endif
2022 }
2023 }
2024
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_61(void)2025 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_61(void)
2026 {
2027 uint32 msr;
2028 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2029
2030 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId])
2031 {
2032 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2033 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2034 #else
2035 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2036 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2037 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2038 {
2039 OsIf_SuspendAllInterrupts();
2040 #ifdef _ARM_DS5_C_S32ZE_
2041 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2042 #endif
2043 }
2044 msr_GPT_EXCLUSIVE_AREA_61[u32CoreId] = msr;
2045 }
2046 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]++;
2047 }
2048
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_61(void)2049 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_61(void)
2050 {
2051 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2052
2053 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]--;
2054 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId])) /*if interrupts were enabled*/
2055 {
2056 OsIf_ResumeAllInterrupts();
2057 #ifdef _ARM_DS5_C_S32ZE_
2058 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2059 #endif
2060 }
2061 }
2062
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_62(void)2063 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_62(void)
2064 {
2065 uint32 msr;
2066 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2067
2068 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId])
2069 {
2070 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2071 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2072 #else
2073 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2074 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2075 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2076 {
2077 OsIf_SuspendAllInterrupts();
2078 #ifdef _ARM_DS5_C_S32ZE_
2079 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2080 #endif
2081 }
2082 msr_GPT_EXCLUSIVE_AREA_62[u32CoreId] = msr;
2083 }
2084 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]++;
2085 }
2086
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_62(void)2087 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_62(void)
2088 {
2089 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2090
2091 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]--;
2092 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId])) /*if interrupts were enabled*/
2093 {
2094 OsIf_ResumeAllInterrupts();
2095 #ifdef _ARM_DS5_C_S32ZE_
2096 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2097 #endif
2098 }
2099 }
2100
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_63(void)2101 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_63(void)
2102 {
2103 uint32 msr;
2104 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2105
2106 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId])
2107 {
2108 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2109 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2110 #else
2111 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2112 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2113 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2114 {
2115 OsIf_SuspendAllInterrupts();
2116 #ifdef _ARM_DS5_C_S32ZE_
2117 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2118 #endif
2119 }
2120 msr_GPT_EXCLUSIVE_AREA_63[u32CoreId] = msr;
2121 }
2122 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]++;
2123 }
2124
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_63(void)2125 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_63(void)
2126 {
2127 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2128
2129 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]--;
2130 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId])) /*if interrupts were enabled*/
2131 {
2132 OsIf_ResumeAllInterrupts();
2133 #ifdef _ARM_DS5_C_S32ZE_
2134 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2135 #endif
2136 }
2137 }
2138
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_64(void)2139 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_64(void)
2140 {
2141 uint32 msr;
2142 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2143
2144 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId])
2145 {
2146 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2147 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2148 #else
2149 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2150 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2151 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2152 {
2153 OsIf_SuspendAllInterrupts();
2154 #ifdef _ARM_DS5_C_S32ZE_
2155 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2156 #endif
2157 }
2158 msr_GPT_EXCLUSIVE_AREA_64[u32CoreId] = msr;
2159 }
2160 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]++;
2161 }
2162
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_64(void)2163 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_64(void)
2164 {
2165 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2166
2167 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]--;
2168 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_64[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId])) /*if interrupts were enabled*/
2169 {
2170 OsIf_ResumeAllInterrupts();
2171 #ifdef _ARM_DS5_C_S32ZE_
2172 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2173 #endif
2174 }
2175 }
2176
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_65(void)2177 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_65(void)
2178 {
2179 uint32 msr;
2180 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2181
2182 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId])
2183 {
2184 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2185 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2186 #else
2187 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2188 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2189 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2190 {
2191 OsIf_SuspendAllInterrupts();
2192 #ifdef _ARM_DS5_C_S32ZE_
2193 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2194 #endif
2195 }
2196 msr_GPT_EXCLUSIVE_AREA_65[u32CoreId] = msr;
2197 }
2198 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]++;
2199 }
2200
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_65(void)2201 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_65(void)
2202 {
2203 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2204
2205 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]--;
2206 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_65[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId])) /*if interrupts were enabled*/
2207 {
2208 OsIf_ResumeAllInterrupts();
2209 #ifdef _ARM_DS5_C_S32ZE_
2210 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2211 #endif
2212 }
2213 }
2214
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_66(void)2215 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_66(void)
2216 {
2217 uint32 msr;
2218 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2219
2220 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId])
2221 {
2222 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2223 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2224 #else
2225 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2226 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2227 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2228 {
2229 OsIf_SuspendAllInterrupts();
2230 #ifdef _ARM_DS5_C_S32ZE_
2231 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2232 #endif
2233 }
2234 msr_GPT_EXCLUSIVE_AREA_66[u32CoreId] = msr;
2235 }
2236 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]++;
2237 }
2238
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_66(void)2239 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_66(void)
2240 {
2241 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2242
2243 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]--;
2244 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_66[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId])) /*if interrupts were enabled*/
2245 {
2246 OsIf_ResumeAllInterrupts();
2247 #ifdef _ARM_DS5_C_S32ZE_
2248 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2249 #endif
2250 }
2251 }
2252
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_67(void)2253 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_67(void)
2254 {
2255 uint32 msr;
2256 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2257
2258 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId])
2259 {
2260 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2261 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2262 #else
2263 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2264 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2265 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2266 {
2267 OsIf_SuspendAllInterrupts();
2268 #ifdef _ARM_DS5_C_S32ZE_
2269 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2270 #endif
2271 }
2272 msr_GPT_EXCLUSIVE_AREA_67[u32CoreId] = msr;
2273 }
2274 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]++;
2275 }
2276
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_67(void)2277 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_67(void)
2278 {
2279 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2280
2281 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]--;
2282 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_67[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId])) /*if interrupts were enabled*/
2283 {
2284 OsIf_ResumeAllInterrupts();
2285 #ifdef _ARM_DS5_C_S32ZE_
2286 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2287 #endif
2288 }
2289 }
2290
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_68(void)2291 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_68(void)
2292 {
2293 uint32 msr;
2294 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2295
2296 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId])
2297 {
2298 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2299 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2300 #else
2301 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2302 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2303 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2304 {
2305 OsIf_SuspendAllInterrupts();
2306 #ifdef _ARM_DS5_C_S32ZE_
2307 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2308 #endif
2309 }
2310 msr_GPT_EXCLUSIVE_AREA_68[u32CoreId] = msr;
2311 }
2312 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]++;
2313 }
2314
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_68(void)2315 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_68(void)
2316 {
2317 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2318
2319 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]--;
2320 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_68[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId])) /*if interrupts were enabled*/
2321 {
2322 OsIf_ResumeAllInterrupts();
2323 #ifdef _ARM_DS5_C_S32ZE_
2324 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2325 #endif
2326 }
2327 }
2328
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_69(void)2329 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_69(void)
2330 {
2331 uint32 msr;
2332 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2333
2334 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId])
2335 {
2336 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2337 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2338 #else
2339 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2340 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2341 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2342 {
2343 OsIf_SuspendAllInterrupts();
2344 #ifdef _ARM_DS5_C_S32ZE_
2345 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2346 #endif
2347 }
2348 msr_GPT_EXCLUSIVE_AREA_69[u32CoreId] = msr;
2349 }
2350 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]++;
2351 }
2352
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_69(void)2353 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_69(void)
2354 {
2355 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2356
2357 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]--;
2358 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_69[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId])) /*if interrupts were enabled*/
2359 {
2360 OsIf_ResumeAllInterrupts();
2361 #ifdef _ARM_DS5_C_S32ZE_
2362 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2363 #endif
2364 }
2365 }
2366
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_70(void)2367 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_70(void)
2368 {
2369 uint32 msr;
2370 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2371
2372 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId])
2373 {
2374 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2375 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2376 #else
2377 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2378 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2379 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2380 {
2381 OsIf_SuspendAllInterrupts();
2382 #ifdef _ARM_DS5_C_S32ZE_
2383 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2384 #endif
2385 }
2386 msr_GPT_EXCLUSIVE_AREA_70[u32CoreId] = msr;
2387 }
2388 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]++;
2389 }
2390
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_70(void)2391 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_70(void)
2392 {
2393 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2394
2395 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]--;
2396 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_70[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId])) /*if interrupts were enabled*/
2397 {
2398 OsIf_ResumeAllInterrupts();
2399 #ifdef _ARM_DS5_C_S32ZE_
2400 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2401 #endif
2402 }
2403 }
2404
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_71(void)2405 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_71(void)
2406 {
2407 uint32 msr;
2408 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2409
2410 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId])
2411 {
2412 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2413 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2414 #else
2415 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2416 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2417 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2418 {
2419 OsIf_SuspendAllInterrupts();
2420 #ifdef _ARM_DS5_C_S32ZE_
2421 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2422 #endif
2423 }
2424 msr_GPT_EXCLUSIVE_AREA_71[u32CoreId] = msr;
2425 }
2426 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]++;
2427 }
2428
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_71(void)2429 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_71(void)
2430 {
2431 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2432
2433 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]--;
2434 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_71[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId])) /*if interrupts were enabled*/
2435 {
2436 OsIf_ResumeAllInterrupts();
2437 #ifdef _ARM_DS5_C_S32ZE_
2438 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2439 #endif
2440 }
2441 }
2442
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_72(void)2443 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_72(void)
2444 {
2445 uint32 msr;
2446 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2447
2448 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId])
2449 {
2450 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2451 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2452 #else
2453 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2454 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2455 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2456 {
2457 OsIf_SuspendAllInterrupts();
2458 #ifdef _ARM_DS5_C_S32ZE_
2459 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2460 #endif
2461 }
2462 msr_GPT_EXCLUSIVE_AREA_72[u32CoreId] = msr;
2463 }
2464 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]++;
2465 }
2466
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_72(void)2467 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_72(void)
2468 {
2469 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2470
2471 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]--;
2472 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_72[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId])) /*if interrupts were enabled*/
2473 {
2474 OsIf_ResumeAllInterrupts();
2475 #ifdef _ARM_DS5_C_S32ZE_
2476 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2477 #endif
2478 }
2479 }
2480
SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_73(void)2481 void SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_73(void)
2482 {
2483 uint32 msr;
2484 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2485
2486 if(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId])
2487 {
2488 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2489 msr = OsIf_Trusted_Call_Return(Gpt_schm_read_msr);
2490 #else
2491 msr = Gpt_schm_read_msr(); /*read MSR (to store interrupts state)*/
2492 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2493 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2494 {
2495 OsIf_SuspendAllInterrupts();
2496 #ifdef _ARM_DS5_C_S32ZE_
2497 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2498 #endif
2499 }
2500 msr_GPT_EXCLUSIVE_AREA_73[u32CoreId] = msr;
2501 }
2502 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]++;
2503 }
2504
SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_73(void)2505 void SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_73(void)
2506 {
2507 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2508
2509 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]--;
2510 if ((ISR_ON(msr_GPT_EXCLUSIVE_AREA_73[u32CoreId]))&&(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId])) /*if interrupts were enabled*/
2511 {
2512 OsIf_ResumeAllInterrupts();
2513 #ifdef _ARM_DS5_C_S32ZE_
2514 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2515 #endif
2516 }
2517 }
2518
2519
2520 #ifdef MCAL_TESTING_ENVIRONMENT
2521 /**
2522 @brief This function checks that all entered exclusive areas were also exited.
2523 @details This function checks that all entered exclusive areas were also exited. The check
2524 is done by verifying that all reentry_guard_* static variables are back to the
2525 zero value.
2526
2527 @param[in] void No input parameters
2528 @return void This function does not return a value. Test asserts are used instead.
2529
2530 @pre None
2531 @post None
2532
2533 @remarks Covers
2534 @remarks Implements
2535 */
SchM_Check_gpt(void)2536 void SchM_Check_gpt(void)
2537 {
2538 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2539
2540 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId]);
2541 reentry_guard_GPT_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_00 for the next test in the suite*/
2542
2543 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId]);
2544 reentry_guard_GPT_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_01 for the next test in the suite*/
2545
2546 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId]);
2547 reentry_guard_GPT_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_02 for the next test in the suite*/
2548
2549 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId]);
2550 reentry_guard_GPT_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_03 for the next test in the suite*/
2551
2552 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId]);
2553 reentry_guard_GPT_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_04 for the next test in the suite*/
2554
2555 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId]);
2556 reentry_guard_GPT_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_05 for the next test in the suite*/
2557
2558 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId]);
2559 reentry_guard_GPT_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_06 for the next test in the suite*/
2560
2561 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId]);
2562 reentry_guard_GPT_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_07 for the next test in the suite*/
2563
2564 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId]);
2565 reentry_guard_GPT_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_10 for the next test in the suite*/
2566
2567 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId]);
2568 reentry_guard_GPT_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_11 for the next test in the suite*/
2569
2570 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId]);
2571 reentry_guard_GPT_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_12 for the next test in the suite*/
2572
2573 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId]);
2574 reentry_guard_GPT_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_17 for the next test in the suite*/
2575
2576 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId]);
2577 reentry_guard_GPT_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_21 for the next test in the suite*/
2578
2579 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId]);
2580 reentry_guard_GPT_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_22 for the next test in the suite*/
2581
2582 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId]);
2583 reentry_guard_GPT_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_23 for the next test in the suite*/
2584
2585 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId]);
2586 reentry_guard_GPT_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_24 for the next test in the suite*/
2587
2588 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId]);
2589 reentry_guard_GPT_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_25 for the next test in the suite*/
2590
2591 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId]);
2592 reentry_guard_GPT_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_26 for the next test in the suite*/
2593
2594 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId]);
2595 reentry_guard_GPT_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_27 for the next test in the suite*/
2596
2597 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId]);
2598 reentry_guard_GPT_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_28 for the next test in the suite*/
2599
2600 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId]);
2601 reentry_guard_GPT_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_29 for the next test in the suite*/
2602
2603 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId]);
2604 reentry_guard_GPT_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_30 for the next test in the suite*/
2605
2606 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId]);
2607 reentry_guard_GPT_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_31 for the next test in the suite*/
2608
2609 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId]);
2610 reentry_guard_GPT_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_35 for the next test in the suite*/
2611
2612 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId]);
2613 reentry_guard_GPT_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_36 for the next test in the suite*/
2614
2615 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId]);
2616 reentry_guard_GPT_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_38 for the next test in the suite*/
2617
2618 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId]);
2619 reentry_guard_GPT_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_40 for the next test in the suite*/
2620
2621 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId]);
2622 reentry_guard_GPT_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_41 for the next test in the suite*/
2623
2624 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId]);
2625 reentry_guard_GPT_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_42 for the next test in the suite*/
2626
2627 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId]);
2628 reentry_guard_GPT_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_43 for the next test in the suite*/
2629
2630 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId]);
2631 reentry_guard_GPT_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_44 for the next test in the suite*/
2632
2633 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId]);
2634 reentry_guard_GPT_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_45 for the next test in the suite*/
2635
2636 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId]);
2637 reentry_guard_GPT_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_46 for the next test in the suite*/
2638
2639 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId]);
2640 reentry_guard_GPT_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_50 for the next test in the suite*/
2641
2642 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId]);
2643 reentry_guard_GPT_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_51 for the next test in the suite*/
2644
2645 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId]);
2646 reentry_guard_GPT_EXCLUSIVE_AREA_52[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_52 for the next test in the suite*/
2647
2648 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId]);
2649 reentry_guard_GPT_EXCLUSIVE_AREA_53[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_53 for the next test in the suite*/
2650
2651 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId]);
2652 reentry_guard_GPT_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_54 for the next test in the suite*/
2653
2654 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId]);
2655 reentry_guard_GPT_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_55 for the next test in the suite*/
2656
2657 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId]);
2658 reentry_guard_GPT_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_56 for the next test in the suite*/
2659
2660 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId]);
2661 reentry_guard_GPT_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_60 for the next test in the suite*/
2662
2663 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId]);
2664 reentry_guard_GPT_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_61 for the next test in the suite*/
2665
2666 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId]);
2667 reentry_guard_GPT_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_62 for the next test in the suite*/
2668
2669 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId]);
2670 reentry_guard_GPT_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_63 for the next test in the suite*/
2671
2672 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId]);
2673 reentry_guard_GPT_EXCLUSIVE_AREA_64[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_64 for the next test in the suite*/
2674
2675 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId]);
2676 reentry_guard_GPT_EXCLUSIVE_AREA_65[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_65 for the next test in the suite*/
2677
2678 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId]);
2679 reentry_guard_GPT_EXCLUSIVE_AREA_66[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_66 for the next test in the suite*/
2680
2681 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId]);
2682 reentry_guard_GPT_EXCLUSIVE_AREA_67[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_67 for the next test in the suite*/
2683
2684 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId]);
2685 reentry_guard_GPT_EXCLUSIVE_AREA_68[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_68 for the next test in the suite*/
2686
2687 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId]);
2688 reentry_guard_GPT_EXCLUSIVE_AREA_69[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_69 for the next test in the suite*/
2689
2690 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId]);
2691 reentry_guard_GPT_EXCLUSIVE_AREA_70[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_70 for the next test in the suite*/
2692
2693 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId]);
2694 reentry_guard_GPT_EXCLUSIVE_AREA_71[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_71 for the next test in the suite*/
2695
2696 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId]);
2697 reentry_guard_GPT_EXCLUSIVE_AREA_72[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_72 for the next test in the suite*/
2698
2699 EU_ASSERT(0UL == reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId]);
2700 reentry_guard_GPT_EXCLUSIVE_AREA_73[u32CoreId] = 0UL; /*reset reentry_guard_GPT_EXCLUSIVE_AREA_73 for the next test in the suite*/
2701
2702
2703 }
2704 #endif /*MCAL_TESTING_ENVIRONMENT*/
2705
2706 #define RTE_STOP_SEC_CODE
2707 #include "Rte_MemMap.h"
2708
2709 #ifdef __cplusplus
2710 }
2711 #endif
2712
2713 /** @} */
2714
