1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Fls.c
9 * @version 3.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Fls.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_FLS_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_FLS_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_FLS_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_FLS_SW_MAJOR_VERSION_C 3
44 #define SCHM_FLS_SW_MINOR_VERSION_C 0
45 #define SCHM_FLS_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_FLS_EXCLUSIVE_AREA_10) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_FLS_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_FLS_EXCLUSIVE_AREA_11) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_FLS_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_FLS_EXCLUSIVE_AREA_12) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_FLS_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_FLS_EXCLUSIVE_AREA_13) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_FLS_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_FLS_EXCLUSIVE_AREA_14) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_FLS_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
112
113 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
114 #include "Rte_MemMap.h"
115 /*==================================================================================================
116 * GLOBAL CONSTANTS
117 ==================================================================================================*/
118
119
120 /*==================================================================================================
121 * GLOBAL VARIABLES
122 ==================================================================================================*/
123
124 /*==================================================================================================
125 * LOCAL FUNCTION PROTOTYPES
126 ==================================================================================================*/
127
128 #ifndef _COSMIC_C_S32K3XX_
129 /*================================================================================================*/
130 /**
131 * @brief This function returns the MSR register value (32 bits).
132 * @details This function returns the MSR register value (32 bits).
133 *
134 * @param[in] void No input parameters
135 * @return uint32 msr This function returns the MSR register value (32 bits).
136 *
137 * @pre None
138 * @post None
139 *
140 */
141 uint32 Fls_schm_read_msr(void);
142 #endif /*ifndef _COSMIC_C_S32K3XX_*/
143 /*==================================================================================================
144 * LOCAL FUNCTIONS
145 ==================================================================================================*/
146 #define RTE_START_SEC_CODE
147 #include "Rte_MemMap.h"
148
149 #if (defined(_GREENHILLS_C_S32K3XX_) || defined(_CODEWARRIOR_C_S32K3XX_))
150 /*================================================================================================*/
151 /**
152 * @brief This macro returns the MSR register value (32 bits).
153 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
154 *
155 * @pre None
156 * @post None
157 *
158 */
159 #ifdef MCAL_PLATFORM_ARM
160 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Fls_schm_read_msr(void)161 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
162 {
163 mrs x0, S3_3_c4_c2_1
164 }
165 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Fls_schm_read_msr(void)166 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
167 {
168 mrs r0, CPSR
169 }
170 #else
Fls_schm_read_msr(void)171 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
172 {
173 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
174 mrs r0, BASEPRI
175 #else
176 mrs r0, PRIMASK
177 #endif
178 }
179 #endif
180 #else
181 #ifdef MCAL_PLATFORM_S12
Fls_schm_read_msr(void)182 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
183 {
184 tfr ccr, d6
185 }
186 #else
Fls_schm_read_msr(void)187 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
188 {
189 mfmsr r3
190 }
191 #endif
192 #endif
193 #endif /*#ifdef GHS||CW*/
194
195 #ifdef _DIABDATA_C_S32K3XX_
196 /**
197 * @brief This function returns the MSR register value (32 bits).
198 * @details This function returns the MSR register value (32 bits).
199 *
200 * @param[in] void No input parameters
201 * @return uint32 msr This function returns the MSR register value (32 bits).
202 *
203 * @pre None
204 * @post None
205 *
206 */
207 #ifdef MCAL_PLATFORM_ARM
Fls_schm_read_msr(void)208 uint32 Fls_schm_read_msr(void)
209 {
210 register uint32 reg_tmp;
211 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
212 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
213 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
214 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
215 #else
216 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
217 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
218 #else
219 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
220 #endif
221 #endif
222 return (uint32)reg_tmp;
223 }
224 #else
Fls_schm_read_msr(void)225 ASM_KEYWORD uint32 Fls_schm_read_msr(void)
226 {
227 mfmsr r3
228 }
229 #endif /* MCAL_PLATFORM_ARM */
230
231 #endif /* _DIABDATA_C_S32K3XX_*/
232
233 #ifdef _COSMIC_C_S32K3XX_
234 /*================================================================================================*/
235 /**
236 * @brief This function returns the MSR register value (32 bits).
237 * @details This function returns the MSR register value (32 bits).
238 *
239 * @param[in] void No input parameters
240 * @return uint32 msr This function returns the MSR register value (32 bits).
241 *
242 * @pre None
243 * @post None
244 *
245 */
246
247 #ifdef MCAL_PLATFORM_S12
248 #define Fls_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
249 #else
250 #define Fls_schm_read_msr() ASM_KEYWORD("mfmsr r3")
251 #endif
252
253 #endif /*Cosmic compiler only*/
254
255
256 #ifdef _HITECH_C_S32K3XX_
257 /*================================================================================================*/
258 /**
259 * @brief This function returns the MSR register value (32 bits).
260 * @details This function returns the MSR register value (32 bits).
261 *
262 * @param[in] void No input parameters
263 * @return uint32 msr This function returns the MSR register value (32 bits).
264 *
265 * @pre None
266 * @post None
267 *
268 */
Fls_schm_read_msr(void)269 uint32 Fls_schm_read_msr(void)
270 {
271 uint32 result;
272 __asm volatile("mfmsr %0" : "=r" (result) :);
273 return result;
274 }
275
276 #endif /*HighTec compiler only*/
277 /*================================================================================================*/
278 #ifdef _LINARO_C_S32K3XX_
279 /**
280 * @brief This function returns the MSR register value (32 bits).
281 * @details This function returns the MSR register value (32 bits).
282 *
283 * @param[in] void No input parameters
284 * @return uint32 msr This function returns the MSR register value (32 bits).
285 *
286 * @pre None
287 * @post None
288 *
289 */
Fls_schm_read_msr(void)290 uint32 Fls_schm_read_msr(void)
291 {
292 register uint32 reg_tmp;
293 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
294 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
295 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
296 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
297 #else
298 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
299 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
300 #else
301 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
302 #endif
303 #endif
304 return (uint32)reg_tmp;
305 }
306 #endif /* _LINARO_C_S32K3XX_*/
307 /*================================================================================================*/
308
309 #ifdef _ARM_DS5_C_S32K3XX_
310 /**
311 * @brief This function returns the MSR register value (32 bits).
312 * @details This function returns the MSR register value (32 bits).
313 *
314 * @param[in] void No input parameters
315 * @return uint32 msr This function returns the MSR register value (32 bits).
316 *
317 * @pre None
318 * @post None
319 *
320 */
Fls_schm_read_msr(void)321 uint32 Fls_schm_read_msr(void)
322 {
323 register uint32 reg_tmp;
324 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
325 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
326 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
327 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
328 #else
329 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
330 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
331 #else
332 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
333 #endif
334 #endif
335 return (uint32)reg_tmp;
336 }
337 #endif /* _ARM_DS5_C_S32K3XX_ */
338
339 #ifdef _IAR_C_S32K3XX_
340 /**
341 * @brief This function returns the MSR register value (32 bits).
342 * @details This function returns the MSR register value (32 bits).
343 *
344 * @param[in] void No input parameters
345 * @return uint32 msr This function returns the MSR register value (32 bits).
346 *
347 * @pre None
348 * @post None
349 *
350 */
Fls_schm_read_msr(void)351 uint32 Fls_schm_read_msr(void)
352 {
353 register uint32 reg_tmp;
354
355 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
356 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
357 #else
358 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
359 #endif
360
361 return (uint32)reg_tmp;
362 }
363 #endif /* _IAR_C_S32K3XX_ */
364
365 #define RTE_STOP_SEC_CODE
366 #include "Rte_MemMap.h"
367
368 /*==================================================================================================
369 * GLOBAL FUNCTIONS
370 ==================================================================================================*/
371 #define RTE_START_SEC_CODE
372 #include "Rte_MemMap.h"
373
SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_10(void)374 void SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_10(void)
375 {
376 uint32 msr;
377 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
378
379 if(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId])
380 {
381 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
382 msr = OsIf_Trusted_Call_Return(Fls_schm_read_msr);
383 #else
384 msr = Fls_schm_read_msr(); /*read MSR (to store interrupts state)*/
385 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
386 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
387 {
388 OsIf_SuspendAllInterrupts();
389 #ifdef _ARM_DS5_C_S32K3XX_
390 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
391 #endif
392 }
393 msr_FLS_EXCLUSIVE_AREA_10[u32CoreId] = msr;
394 }
395 reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId]++;
396 }
397
SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_10(void)398 void SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_10(void)
399 {
400 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
401
402 reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId]--;
403 if ((ISR_ON(msr_FLS_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
404 {
405 OsIf_ResumeAllInterrupts();
406 #ifdef _ARM_DS5_C_S32K3XX_
407 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
408 #endif
409 }
410 }
411
SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_11(void)412 void SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_11(void)
413 {
414 uint32 msr;
415 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
416
417 if(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId])
418 {
419 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
420 msr = OsIf_Trusted_Call_Return(Fls_schm_read_msr);
421 #else
422 msr = Fls_schm_read_msr(); /*read MSR (to store interrupts state)*/
423 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
424 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
425 {
426 OsIf_SuspendAllInterrupts();
427 #ifdef _ARM_DS5_C_S32K3XX_
428 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
429 #endif
430 }
431 msr_FLS_EXCLUSIVE_AREA_11[u32CoreId] = msr;
432 }
433 reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId]++;
434 }
435
SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_11(void)436 void SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_11(void)
437 {
438 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
439
440 reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId]--;
441 if ((ISR_ON(msr_FLS_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
442 {
443 OsIf_ResumeAllInterrupts();
444 #ifdef _ARM_DS5_C_S32K3XX_
445 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
446 #endif
447 }
448 }
449
SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_12(void)450 void SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_12(void)
451 {
452 uint32 msr;
453 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
454
455 if(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId])
456 {
457 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
458 msr = OsIf_Trusted_Call_Return(Fls_schm_read_msr);
459 #else
460 msr = Fls_schm_read_msr(); /*read MSR (to store interrupts state)*/
461 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
462 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
463 {
464 OsIf_SuspendAllInterrupts();
465 #ifdef _ARM_DS5_C_S32K3XX_
466 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
467 #endif
468 }
469 msr_FLS_EXCLUSIVE_AREA_12[u32CoreId] = msr;
470 }
471 reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId]++;
472 }
473
SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_12(void)474 void SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_12(void)
475 {
476 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
477
478 reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId]--;
479 if ((ISR_ON(msr_FLS_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
480 {
481 OsIf_ResumeAllInterrupts();
482 #ifdef _ARM_DS5_C_S32K3XX_
483 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
484 #endif
485 }
486 }
487
SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_13(void)488 void SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_13(void)
489 {
490 uint32 msr;
491 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
492
493 if(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId])
494 {
495 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
496 msr = OsIf_Trusted_Call_Return(Fls_schm_read_msr);
497 #else
498 msr = Fls_schm_read_msr(); /*read MSR (to store interrupts state)*/
499 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
500 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
501 {
502 OsIf_SuspendAllInterrupts();
503 #ifdef _ARM_DS5_C_S32K3XX_
504 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
505 #endif
506 }
507 msr_FLS_EXCLUSIVE_AREA_13[u32CoreId] = msr;
508 }
509 reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId]++;
510 }
511
SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_13(void)512 void SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_13(void)
513 {
514 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
515
516 reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId]--;
517 if ((ISR_ON(msr_FLS_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
518 {
519 OsIf_ResumeAllInterrupts();
520 #ifdef _ARM_DS5_C_S32K3XX_
521 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
522 #endif
523 }
524 }
525
SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_14(void)526 void SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_14(void)
527 {
528 uint32 msr;
529 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
530
531 if(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId])
532 {
533 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
534 msr = OsIf_Trusted_Call_Return(Fls_schm_read_msr);
535 #else
536 msr = Fls_schm_read_msr(); /*read MSR (to store interrupts state)*/
537 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
538 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
539 {
540 OsIf_SuspendAllInterrupts();
541 #ifdef _ARM_DS5_C_S32K3XX_
542 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
543 #endif
544 }
545 msr_FLS_EXCLUSIVE_AREA_14[u32CoreId] = msr;
546 }
547 reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId]++;
548 }
549
SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_14(void)550 void SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_14(void)
551 {
552 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
553
554 reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId]--;
555 if ((ISR_ON(msr_FLS_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
556 {
557 OsIf_ResumeAllInterrupts();
558 #ifdef _ARM_DS5_C_S32K3XX_
559 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
560 #endif
561 }
562 }
563
564
565 #ifdef MCAL_TESTING_ENVIRONMENT
566 /**
567 @brief This function checks that all entered exclusive areas were also exited.
568 @details This function checks that all entered exclusive areas were also exited. The check
569 is done by verifying that all reentry_guard_* static variables are back to the
570 zero value.
571
572 @param[in] void No input parameters
573 @return void This function does not return a value. Test asserts are used instead.
574
575 @pre None
576 @post None
577
578 @remarks Covers
579 @remarks Implements
580 */
SchM_Check_fls(void)581 void SchM_Check_fls(void)
582 {
583 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
584
585 EU_ASSERT(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId]);
586 reentry_guard_FLS_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_FLS_EXCLUSIVE_AREA_10 for the next test in the suite*/
587
588 EU_ASSERT(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId]);
589 reentry_guard_FLS_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_FLS_EXCLUSIVE_AREA_11 for the next test in the suite*/
590
591 EU_ASSERT(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId]);
592 reentry_guard_FLS_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_FLS_EXCLUSIVE_AREA_12 for the next test in the suite*/
593
594 EU_ASSERT(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId]);
595 reentry_guard_FLS_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_FLS_EXCLUSIVE_AREA_13 for the next test in the suite*/
596
597 EU_ASSERT(0UL == reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId]);
598 reentry_guard_FLS_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_FLS_EXCLUSIVE_AREA_14 for the next test in the suite*/
599
600
601 }
602 #endif /*MCAL_TESTING_ENVIRONMENT*/
603
604 #define RTE_STOP_SEC_CODE
605 #include "Rte_MemMap.h"
606
607 #ifdef __cplusplus
608 }
609 #endif
610
611 /** @} */
612
