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Searched refs:SCG_SPLLCFG_MULT_VAL (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.c65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1106 freq *= (SCG_SPLLCFG_MULT_VAL + SCG_SPLL_MULT_BASE_VALUE); /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1106 freq *= (SCG_SPLLCFG_MULT_VAL + SCG_SPLL_MULT_BASE_VALUE); /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.c65 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1106 freq *= (SCG_SPLLCFG_MULT_VAL + SCG_SPLL_MULT_BASE_VALUE); /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.c69 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1146 freq *= (SCG_SPLLCFG_MULT_VAL + SCG_SPLL_MULT_BASE_VALUE); /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.c69 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1146 freq *= (SCG_SPLLCFG_MULT_VAL + SCG_SPLL_MULT_BASE_VALUE); /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.c82 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1496 freq *= s_spllMulti[SCG_SPLLCFG_MULT_VAL]; /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.c82 #define SCG_SPLLCFG_MULT_VAL ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) macro
1496 freq *= s_spllMulti[SCG_SPLLCFG_MULT_VAL]; /* Multiplier. */ in CLOCK_GetSysPllCommonFreq()