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Searched refs:SCG_FIRCDIV_FIRCDIV1_VAL (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c39 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
653 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.c55 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
851 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.c55 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
851 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.c55 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
851 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.c57 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
892 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.c57 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
892 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.c70 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
1024 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.c70 #define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV… macro
1024 divider = SCG_FIRCDIV_FIRCDIV1_VAL; in CLOCK_GetFircAsyncFreq()