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Searched refs:SCG_APLLDIV_APLLDIV2_VAL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.c93 #define SCG_APLLDIV_APLLDIV2_VAL ((SCG->APLLDIV & SCG_APLLDIV_APLLDIV2_MASK) >> SCG_APLLDIV_APLLDIV… macro
1266 divider = SCG_APLLDIV_APLLDIV2_VAL; in CLOCK_GetAuxPllAsyncFreq()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.c93 #define SCG_APLLDIV_APLLDIV2_VAL ((SCG->APLLDIV & SCG_APLLDIV_APLLDIV2_MASK) >> SCG_APLLDIV_APLLDIV… macro
1266 divider = SCG_APLLDIV_APLLDIV2_VAL; in CLOCK_GetAuxPllAsyncFreq()