Searched refs:Reserved (Results 1 – 21 of 21) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/iar/ |
| D | startup_MIMX9352_cm33.s | 64 DCD 0 ;Reserved
65 DCD 0 ;Reserved
66 DCD 0 ;Reserved
69 DCD 0 ;Reserved
76 DCD Reserved18_IRQHandler ;Reserved interrupt
99 DCD Reserved41_IRQHandler ;Reserved interrupt
100 DCD Reserved42_IRQHandler ;Reserved interrupt
101 DCD Reserved43_IRQHandler ;Reserved interrupt
115 DCD Reserved57_IRQHandler ;Reserved interrupt
116 DCD Reserved58_IRQHandler ;Reserved interrupt
[all …]
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| /hal_nxp-3.5.0/mcux/middleware/mcux-sdk-middleware-usb/host/class/ |
| D | usb_host_cdc_rndis.c | 159 message->Reserved = 0U; in USB_HostRndisResetMsg()
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| D | usb_host_cdc_rndis.h | 203 uint32_t Reserved; member
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/gcc/ |
| D | MIMX8QM6xxxFF_cm4_core0_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| D | MIMX8QM6xxxFF_cm4_core0_flash.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| D | MIMX8QM6xxxFF_cm4_core1_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| D | MIMX8QM6xxxFF_cm4_core1_flash.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/gcc/ |
| D | MIMX8QX3xxxxx_cm4_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/gcc/ |
| D | MIMX8QX4xxxxx_cm4_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/gcc/ |
| D | MIMX8QX5xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/gcc/ |
| D | MIMX8UX6xxxxx_cm4_ddr_ram.ld | 33 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/gcc/ |
| D | MIMX8UX5xxxxx_cm4_ddr_ram.ld | 33 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/gcc/ |
| D | MIMX8QX6xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/gcc/ |
| D | MIMX8DX3xxxxx_cm4_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/gcc/ |
| D | MIMX8DX2xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/gcc/ |
| D | MIMX8DX5xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/gcc/ |
| D | MIMX8QX1xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/gcc/ |
| D | MIMX8DX4xxxxx_cm4_ddr_ram.ld | 30 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/gcc/ |
| D | MIMX8DX1xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/gcc/ |
| D | MIMX8QX2xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/gcc/ |
| D | MIMX8DX6xxxxx_cm4_ddr_ram.ld | 32 /* Reserved for PFU fetches, which is six 16-bit Thumb instructions */
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