Searched refs:RegValue (Results 1 – 10 of 10) sorted by relevance
91 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_GetClrTxStatus() local93 RegValue = (RegValue & QuadSPI_MCR_CLR_TXF_MASK) >> QuadSPI_MCR_CLR_TXF_SHIFT; in Qspi_Ip_GetClrTxStatus()94 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrTxStatus()113 uint32 RegValue = (uint32)BaseAddr->SPTRCLR; in Qspi_Ip_GetClrAhbStatus() local115 RegValue = (RegValue & QuadSPI_SPTRCLR_ABRT_CLR_MASK) >> QuadSPI_SPTRCLR_ABRT_CLR_SHIFT; in Qspi_Ip_GetClrAhbStatus()116 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrAhbStatus()247 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_SetIdleLineValuesA() local250 RegValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK)); in Qspi_Ip_SetIdleLineValuesA()251 RegValue |= (QuadSPI_MCR_ISD2FA(Iofa2IdleValue) | QuadSPI_MCR_ISD3FA(Iofa3IdleValue)); in Qspi_Ip_SetIdleLineValuesA()254 BaseAddr->MCR = (uint32)RegValue; in Qspi_Ip_SetIdleLineValuesA()[all …]
145 uint32 RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()164 RegValue &= ~DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()165 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()219 (void)RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()234 uint32 RegValue; in Clock_Ip_SetPllPll0divDeDivOutput() local245 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPllPll0divDeDivOutput()246 RegValue |= PLL_PLLODIV_DE_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()247 RegValue &= ~PLL_PLLODIV_DIV_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()[all …]
206 static void Power_Ip_MC_RGM_ClearFesResetFlags(uint32 RegValue);207 static void Power_Ip_MC_RGM_ClearDesResetFlags(uint32 RegValue);225 static void Power_Ip_MC_RGM_ClearFesResetFlags(uint32 RegValue) in Power_Ip_MC_RGM_ClearFesResetFlags() argument231 uint32 RegValueTemp = RegValue; in Power_Ip_MC_RGM_ClearFesResetFlags()266 static void Power_Ip_MC_RGM_ClearDesResetFlags(uint32 RegValue) in Power_Ip_MC_RGM_ClearDesResetFlags() argument272 uint32 RegValueTemp = RegValue; in Power_Ip_MC_RGM_ClearDesResetFlags()516 uint32 RegValue = 0U; in Power_Ip_MC_RGM_GetResetReason() local521 RegValue = Power_Ip_pxMC_RGM->DES & MC_RGM_DES_RWBITS_MASK32; in Power_Ip_MC_RGM_GetResetReason()524 if ((uint32)0U != RegValue) in Power_Ip_MC_RGM_GetResetReason()526 DesResetStatus = RegValue; in Power_Ip_MC_RGM_GetResetReason()[all …]
182 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() local209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()210 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()211 RegValue |= (SelectorValue << SelectorShift) & SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()212 RegValue |= (MC_CGM_MUX_CSC_CLK_SW_MASK); /* Clock switch operation is requested */ in Clock_Ip_SetCgmXCscCssClkswSwip()213 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()267 (void)RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()314 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip() local341 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()342 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()[all …]
208 uint32 RegValue; in Clock_Ip_SetFircDivSelHSEb() local254 RegValue = IP_CONFIGURATION_GPR->CONFIG_REG_GPR; in Clock_Ip_SetFircDivSelHSEb()255 RegValue &= ~CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL_MASK; in Clock_Ip_SetFircDivSelHSEb()256 RegValue |= CONFIGURATION_GPR_CONFIG_REG_GPR_FIRC_DIV_SEL(DividerValue); in Clock_Ip_SetFircDivSelHSEb()257 IP_CONFIGURATION_GPR->CONFIG_REG_GPR = RegValue; in Clock_Ip_SetFircDivSelHSEb()273 (void)RegValue; in Clock_Ip_SetFircDivSelHSEb()
375 uint32 RegValue; in Clock_Ip_CodeInRamSetFlashWaitStates() local421 RegValue = IP_FLASH->CTL; in Clock_Ip_CodeInRamSetFlashWaitStates()422 RegValue &= ~FLASH_CTL_RWSL_MASK; in Clock_Ip_CodeInRamSetFlashWaitStates()423 RegValue &= ~FLASH_CTL_RWSC_MASK; in Clock_Ip_CodeInRamSetFlashWaitStates()424 RegValue |= FLASH_CTL_RWSC(RwscSetting); in Clock_Ip_CodeInRamSetFlashWaitStates()434 IP_FLASH->CTL = RegValue; in Clock_Ip_CodeInRamSetFlashWaitStates()
437 uint32 RegValue; in Power_Ip_PMC_VoltageErrorIsr() local441 RegValue = IP_PMC->LVSC; in Power_Ip_PMC_VoltageErrorIsr()443 VoltageIsrEnabled = RegValue & PMC_LVSC_OV_UV_IRQ_FLAGS_MASK32; in Power_Ip_PMC_VoltageErrorIsr()448 VoltageIsrStatus = RegValue & PMC_LVSC_OV_UV_STATUS_FLAGS_MASK32; in Power_Ip_PMC_VoltageErrorIsr()450 RegValue = IP_PMC->CONFIG; in Power_Ip_PMC_VoltageErrorIsr()452 if (PMC_CONFIG_LVD_INTERRUPTS_DISABLE == (RegValue & PMC_CONFIG_LVDIE_MASK)) in Power_Ip_PMC_VoltageErrorIsr()461 if (PMC_CONFIG_HVD_INTERRUPTS_DISABLE == (RegValue & PMC_CONFIG_HVDIE_MASK)) in Power_Ip_PMC_VoltageErrorIsr()
143 uint32 RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local153 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()154 RegValue &= ~DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()155 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()156 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()214 uint32 RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() local224 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()225 RegValue &= ~DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()226 RegValue |= ((Config->Value-1U) << DividerShift) & DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()227 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()[all …]
172 uint32 RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip() local190 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()191 RegValue &= ~SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()192 RegValue |= (SelectorValue << SelectorShift) & SelectorMask; in Clock_Ip_SetCgmXCscCssClkswSwip()193 RegValue |= (MC_CGM_MUX_CSC_CLK_SW_MASK); /* Clock switch operation is requested */ in Clock_Ip_SetCgmXCscCssClkswSwip()194 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()253 uint32 RegValue; in Clock_Ip_ResetCgmXCscCssCsGrip() local271 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_ResetCgmXCscCssCsGrip()272 RegValue &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssCsGrip()273 RegValue |= (SelectorResetValue << SelectorShift) & SelectorMask; in Clock_Ip_ResetCgmXCscCssCsGrip()[all …]
2739 uint32 RegValue; in Netc_EthSwt_Ip_ConfigPortTimeGateScheduling() local2762 RegValue = Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PTGSCR; in Netc_EthSwt_Ip_ConfigPortTimeGateScheduling()2766 RegValue |= SW_PORT0_PTGSCR_TGE(1U); /* Enable time gating */ in Netc_EthSwt_Ip_ConfigPortTimeGateScheduling()2770 RegValue &= ~SW_PORT0_PTGSCR_TGE(1U); /* Disable time gating */ in Netc_EthSwt_Ip_ConfigPortTimeGateScheduling()2774 Netc_EthSwt_Ip_SW0_PortxBaseAddr[SwitchPortIdx]->PTGSCR = RegValue; in Netc_EthSwt_Ip_ConfigPortTimeGateScheduling()
