1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_RTC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_RTC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_RTC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_RTC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t RTCSUPV; /**< RTC Supervisor control register, offset: 0x0 */ 74 __IO uint32_t RTCC; /**< RTC Control register, offset: 0x4 */ 75 __IO uint32_t RTCS; /**< RTC Status register, offset: 0x8 */ 76 __I uint32_t RTCCNT; /**< RTC Counter register, offset: 0xC */ 77 __IO uint32_t APIVAL; /**< API Compare value register, offset: 0x10 */ 78 __IO uint32_t RTCVAL; /**< RTC Compare value register, offset: 0x14 */ 79 } RTC_Type, *RTC_MemMapPtr; 80 81 /** Number of instances of the RTC module. */ 82 #define RTC_INSTANCE_COUNT (1u) 83 84 /* RTC - Peripheral instance base addresses */ 85 /** Peripheral RTC base address */ 86 #define IP_RTC_BASE (0x40288000u) 87 /** Peripheral RTC base pointer */ 88 #define IP_RTC ((RTC_Type *)IP_RTC_BASE) 89 /** Array initializer of RTC peripheral base addresses */ 90 #define IP_RTC_BASE_ADDRS { IP_RTC_BASE } 91 /** Array initializer of RTC peripheral base pointers */ 92 #define IP_RTC_BASE_PTRS { IP_RTC } 93 94 /* ---------------------------------------------------------------------------- 95 -- RTC Register Masks 96 ---------------------------------------------------------------------------- */ 97 98 /*! 99 * @addtogroup RTC_Register_Masks RTC Register Masks 100 * @{ 101 */ 102 103 /*! @name RTCSUPV - RTC Supervisor control register */ 104 /*! @{ */ 105 106 #define RTC_RTCSUPV_SUPV_MASK (0x80000000U) 107 #define RTC_RTCSUPV_SUPV_SHIFT (31U) 108 #define RTC_RTCSUPV_SUPV_WIDTH (1U) 109 #define RTC_RTCSUPV_SUPV(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCSUPV_SUPV_SHIFT)) & RTC_RTCSUPV_SUPV_MASK) 110 /*! @} */ 111 112 /*! @name RTCC - RTC Control register */ 113 /*! @{ */ 114 115 #define RTC_RTCC_TRIG_EN_MASK (0x1U) 116 #define RTC_RTCC_TRIG_EN_SHIFT (0U) 117 #define RTC_RTCC_TRIG_EN_WIDTH (1U) 118 #define RTC_RTCC_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_TRIG_EN_SHIFT)) & RTC_RTCC_TRIG_EN_MASK) 119 120 #define RTC_RTCC_DIV32EN_MASK (0x400U) 121 #define RTC_RTCC_DIV32EN_SHIFT (10U) 122 #define RTC_RTCC_DIV32EN_WIDTH (1U) 123 #define RTC_RTCC_DIV32EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_DIV32EN_SHIFT)) & RTC_RTCC_DIV32EN_MASK) 124 125 #define RTC_RTCC_DIV512EN_MASK (0x800U) 126 #define RTC_RTCC_DIV512EN_SHIFT (11U) 127 #define RTC_RTCC_DIV512EN_WIDTH (1U) 128 #define RTC_RTCC_DIV512EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_DIV512EN_SHIFT)) & RTC_RTCC_DIV512EN_MASK) 129 130 #define RTC_RTCC_CLKSEL_MASK (0x3000U) 131 #define RTC_RTCC_CLKSEL_SHIFT (12U) 132 #define RTC_RTCC_CLKSEL_WIDTH (2U) 133 #define RTC_RTCC_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_CLKSEL_SHIFT)) & RTC_RTCC_CLKSEL_MASK) 134 135 #define RTC_RTCC_APIIE_MASK (0x4000U) 136 #define RTC_RTCC_APIIE_SHIFT (14U) 137 #define RTC_RTCC_APIIE_WIDTH (1U) 138 #define RTC_RTCC_APIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_APIIE_SHIFT)) & RTC_RTCC_APIIE_MASK) 139 140 #define RTC_RTCC_APIEN_MASK (0x8000U) 141 #define RTC_RTCC_APIEN_SHIFT (15U) 142 #define RTC_RTCC_APIEN_WIDTH (1U) 143 #define RTC_RTCC_APIEN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_APIEN_SHIFT)) & RTC_RTCC_APIEN_MASK) 144 145 #define RTC_RTCC_ROVREN_MASK (0x10000000U) 146 #define RTC_RTCC_ROVREN_SHIFT (28U) 147 #define RTC_RTCC_ROVREN_WIDTH (1U) 148 #define RTC_RTCC_ROVREN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_ROVREN_SHIFT)) & RTC_RTCC_ROVREN_MASK) 149 150 #define RTC_RTCC_FRZEN_MASK (0x20000000U) 151 #define RTC_RTCC_FRZEN_SHIFT (29U) 152 #define RTC_RTCC_FRZEN_WIDTH (1U) 153 #define RTC_RTCC_FRZEN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_FRZEN_SHIFT)) & RTC_RTCC_FRZEN_MASK) 154 155 #define RTC_RTCC_RTCIE_MASK (0x40000000U) 156 #define RTC_RTCC_RTCIE_SHIFT (30U) 157 #define RTC_RTCC_RTCIE_WIDTH (1U) 158 #define RTC_RTCC_RTCIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_RTCIE_SHIFT)) & RTC_RTCC_RTCIE_MASK) 159 160 #define RTC_RTCC_CNTEN_MASK (0x80000000U) 161 #define RTC_RTCC_CNTEN_SHIFT (31U) 162 #define RTC_RTCC_CNTEN_WIDTH (1U) 163 #define RTC_RTCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCC_CNTEN_SHIFT)) & RTC_RTCC_CNTEN_MASK) 164 /*! @} */ 165 166 /*! @name RTCS - RTC Status register */ 167 /*! @{ */ 168 169 #define RTC_RTCS_ROVRF_MASK (0x400U) 170 #define RTC_RTCS_ROVRF_SHIFT (10U) 171 #define RTC_RTCS_ROVRF_WIDTH (1U) 172 #define RTC_RTCS_ROVRF(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCS_ROVRF_SHIFT)) & RTC_RTCS_ROVRF_MASK) 173 174 #define RTC_RTCS_APIF_MASK (0x2000U) 175 #define RTC_RTCS_APIF_SHIFT (13U) 176 #define RTC_RTCS_APIF_WIDTH (1U) 177 #define RTC_RTCS_APIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCS_APIF_SHIFT)) & RTC_RTCS_APIF_MASK) 178 179 #define RTC_RTCS_INV_API_MASK (0x20000U) 180 #define RTC_RTCS_INV_API_SHIFT (17U) 181 #define RTC_RTCS_INV_API_WIDTH (1U) 182 #define RTC_RTCS_INV_API(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCS_INV_API_SHIFT)) & RTC_RTCS_INV_API_MASK) 183 184 #define RTC_RTCS_INV_RTC_MASK (0x40000U) 185 #define RTC_RTCS_INV_RTC_SHIFT (18U) 186 #define RTC_RTCS_INV_RTC_WIDTH (1U) 187 #define RTC_RTCS_INV_RTC(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCS_INV_RTC_SHIFT)) & RTC_RTCS_INV_RTC_MASK) 188 189 #define RTC_RTCS_RTCF_MASK (0x20000000U) 190 #define RTC_RTCS_RTCF_SHIFT (29U) 191 #define RTC_RTCS_RTCF_WIDTH (1U) 192 #define RTC_RTCS_RTCF(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCS_RTCF_SHIFT)) & RTC_RTCS_RTCF_MASK) 193 /*! @} */ 194 195 /*! @name RTCCNT - RTC Counter register */ 196 /*! @{ */ 197 198 #define RTC_RTCCNT_RTCCNT_MASK (0xFFFFFFFFU) 199 #define RTC_RTCCNT_RTCCNT_SHIFT (0U) 200 #define RTC_RTCCNT_RTCCNT_WIDTH (32U) 201 #define RTC_RTCCNT_RTCCNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCCNT_RTCCNT_SHIFT)) & RTC_RTCCNT_RTCCNT_MASK) 202 /*! @} */ 203 204 /*! @name APIVAL - API Compare value register */ 205 /*! @{ */ 206 207 #define RTC_APIVAL_APIVAL_MASK (0xFFFFFFFFU) 208 #define RTC_APIVAL_APIVAL_SHIFT (0U) 209 #define RTC_APIVAL_APIVAL_WIDTH (32U) 210 #define RTC_APIVAL_APIVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_APIVAL_APIVAL_SHIFT)) & RTC_APIVAL_APIVAL_MASK) 211 /*! @} */ 212 213 /*! @name RTCVAL - RTC Compare value register */ 214 /*! @{ */ 215 216 #define RTC_RTCVAL_RTCVAL_MASK (0xFFFFFFFFU) 217 #define RTC_RTCVAL_RTCVAL_SHIFT (0U) 218 #define RTC_RTCVAL_RTCVAL_WIDTH (32U) 219 #define RTC_RTCVAL_RTCVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_RTCVAL_RTCVAL_SHIFT)) & RTC_RTCVAL_RTCVAL_MASK) 220 /*! @} */ 221 222 /*! 223 * @} 224 */ /* end of group RTC_Register_Masks */ 225 226 /*! 227 * @} 228 */ /* end of group RTC_Peripheral_Access_Layer */ 229 230 #endif /* #if !defined(S32K344_RTC_H_) */ 231
