| /hal_nxp-3.5.0/mcux/mcux-sdk/components/css_pkc/src/comps/mcuxClPkc/src/ |
| D | mcuxClPkc_Initialize.c | 64 while (0u == PKC->CTRL_b.RESET) in MCUX_CSSL_FP_FUNCTION_DEF()
80 while (0u != PKC->CTRL_b.RESET) in MCUX_CSSL_FP_FUNCTION_DEF()
115 while (0u == PKC->CTRL_b.RESET) in MCUX_CSSL_FP_FUNCTION_DEF()
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/lpcxpresso55s06/project_template/ |
| D | pin_mux.h | 384 #define BOARD_INITBUTTONSPINS_RESET_SIGNAL RESET
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/lpcxpresso55s16/project_template/ |
| D | pin_mux.h | 456 #define BOARD_INITBUTTONSPINS_RESET_SIGNAL RESET
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/lpcxpresso55s69/project_template/ |
| D | pin_mux.h | 503 #define BOARD_INITBUTTONSPINS_S4_SIGNAL RESET
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| /hal_nxp-3.5.0/mcux/mcux-sdk/boards/lpcxpresso55s28/project_template/ |
| D | pin_mux.h | 499 #define BOARD_INITBUTTONSPINS_S4_SIGNAL RESET
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| /hal_nxp-3.5.0/mcux/mcux-sdk/components/css_pkc/src/platforms/crypto_ip/inc/fame/ |
| D | fame3.h | 207 …__IOM uint32_t RESET : 1; /*!< PKC reset control bit: RESET=1 enforces the PKC… member
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| /hal_nxp-3.5.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 32072 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
32116 #define SDMAARM_RESET_REG(base) ((base)->RESET)
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| /hal_nxp-3.5.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 39256 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
39300 #define SDMAARM_RESET_REG(base) ((base)->RESET)
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| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 52434 __IO uint32_t RESET; /**< RESET Control Register, offset: 0x0 */ member
66478 __IO uint32_t RESET; /**< RESET, offset: 0xC */ member
|
| D | MIMX9352_ca55.h | 46826 __IO uint32_t RESET; /**< RESET Control Register, offset: 0x0 */ member
58004 __IO uint32_t RESET; /**< RESET, offset: 0xC */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 46511 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 46509 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 46511 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_ca53.h | 46523 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| D | MIMX8MN6_cm7.h | 46509 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 46511 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 46509 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 47882 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 50055 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 50055 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 50055 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 50055 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 65006 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 65006 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 65006 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ member
|
