Home
last modified time | relevance | path

Searched refs:QuadSPI_MCR_ISD3FA_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h250 RegValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK)); in Qspi_Ip_SetIdleLineValuesA()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h246 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) macro
249 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17878 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) macro
17884 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17880 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) macro
17886 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25230 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) macro
25236 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25229 #define QuadSPI_MCR_ISD3FA_MASK (0x20000U) macro
25235 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_ISD3FA_SHIFT)) & QuadSPI_MCR_ISD3FA_MASK)