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Searched refs:QuadSPI_MCR_DQS_FA_SEL_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h175 #define QuadSPI_MCR_DQS_FA_SEL_MASK (0x3000000U) macro
178 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_FA_SEL_SHIFT)) & QuadSPI_MCR_DQS_FA_SEL_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h922 RegValue &= (uint32)(~QuadSPI_MCR_DQS_FA_SEL_MASK); in Qspi_Ip_SetDQSSourceA()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h261 #define QuadSPI_MCR_DQS_FA_SEL_MASK (0x3000000U) macro
264 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_FA_SEL_SHIFT)) & QuadSPI_MCR_DQS_FA_SEL_MASK)