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Searched refs:QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h423 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK (0x1000U) macro
426 …int32_t)(x)) << QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h480 …RegValue = RegValue & (QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK | QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK); in Qspi_Ip_DLLGetErrorStatusA()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h754 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK (0x1000U) macro
757 …int32_t)(x)) << QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK)