1 /*
2  * Copyright 2020-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef QUADSPI_HW_ACCESS_H
8 #define QUADSPI_HW_ACCESS_H
9 
10 /**
11 *   @file Qspi_Ip_HwAccess.h
12 *
13 *   @addtogroup IPV_QSPI QSPI IPV Driver
14 *   @{
15 */
16 
17 /* implements Qspi_Ip_HwAccess.h_Artifact */
18 
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22 
23 /*==================================================================================================
24 *                              SOURCE FILE VERSION INFORMATION
25 ==================================================================================================*/
26 #define QSPI_IP_HW_ACCESS_VENDOR_ID_H                       43
27 #define QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H        4
28 #define QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H        7
29 #define QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H     0
30 #define QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H                3
31 #define QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H                0
32 #define QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H                0
33 
34 
35 /*==================================================================================================
36 *                                     FILE VERSION CHECKS
37 ==================================================================================================*/
38 
39 #if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
40 
41 /*******************************************************************************
42  * Definitions
43  ******************************************************************************/
44 
45 #define QSPI_IP_RX_READOUT_IP   1U        /* RX Buffer content is read using the AHB Bus registers QSPI_ARDBn */
46 
47 /*******************************************************************************
48  * API
49  ******************************************************************************/
50 
51 
52 /*
53  * Triggers an IP transaction
54  */
Qspi_Ip_IpTrigger(QuadSPI_Type * BaseAddr,uint8 SeqID,uint16 DataSize)55 static inline void Qspi_Ip_IpTrigger(QuadSPI_Type *BaseAddr,
56                                      uint8 SeqID,
57                                      uint16 DataSize
58                                     )
59 {
60     BaseAddr->IPCR =  QuadSPI_IPCR_SEQID(SeqID)
61                     | QuadSPI_IPCR_IDATSZ(DataSize);
62 }
63 
64 
65 /*
66  * Clear Rx buffer
67  */
Qspi_Ip_ClearRxBuf(QuadSPI_Type * BaseAddr)68 static inline void Qspi_Ip_ClearRxBuf(QuadSPI_Type *BaseAddr)
69 {
70     BaseAddr->MCR |= QuadSPI_MCR_CLR_RXF_MASK;
71 
72 }
73 
74 
75 /*
76  * Clear Tx buffer
77  */
Qspi_Ip_ClearTxBuf(QuadSPI_Type * BaseAddr)78 static inline void Qspi_Ip_ClearTxBuf(QuadSPI_Type *BaseAddr)
79 {
80     BaseAddr->MCR |= QuadSPI_MCR_CLR_TXF_MASK;
81 
82 }
83 
84 
85 /*
86  * Checks the Tx buffer clear flag
87  * Returns TRUE if the Tx buffer content is invalidated.
88  */
Qspi_Ip_GetClrTxStatus(const QuadSPI_Type * BaseAddr)89 static inline boolean Qspi_Ip_GetClrTxStatus(const QuadSPI_Type *BaseAddr)
90 {
91     uint32 RegValue = (uint32)BaseAddr->MCR;
92 
93     RegValue = (RegValue & QuadSPI_MCR_CLR_TXF_MASK) >> QuadSPI_MCR_CLR_TXF_SHIFT;
94     return (0U == RegValue)? TRUE : FALSE;
95 }
96 
97 
98 #ifdef QuadSPI_SPTRCLR_ABRT_CLR_MASK
99 /*
100  * Clear AHB buffer
101  */
Qspi_Ip_ClearAhbBuf(QuadSPI_Type * BaseAddr)102 static inline void Qspi_Ip_ClearAhbBuf(QuadSPI_Type *BaseAddr)
103 {
104     BaseAddr->SPTRCLR |= QuadSPI_SPTRCLR_ABRT_CLR_MASK;
105 }
106 
107 /*
108  * Checks the Ahb buffer clear flag
109  * Returns TRUE if the Ahb buffer content is invalidated.
110  */
Qspi_Ip_GetClrAhbStatus(const QuadSPI_Type * BaseAddr)111 static inline boolean Qspi_Ip_GetClrAhbStatus(const QuadSPI_Type *BaseAddr)
112 {
113     uint32 RegValue = (uint32)BaseAddr->SPTRCLR;
114 
115     RegValue = (RegValue & QuadSPI_SPTRCLR_ABRT_CLR_MASK) >> QuadSPI_SPTRCLR_ABRT_CLR_SHIFT;
116     return (0U == RegValue)? TRUE : FALSE;
117 }
118 #endif
119 
120 
121 /*!
122  * @brief Clears IP sequence pointer
123  *
124  */
Qspi_Ip_ClearIpSeqPointer(QuadSPI_Type * BaseAddr)125 static inline void Qspi_Ip_ClearIpSeqPointer(QuadSPI_Type *BaseAddr)
126 {
127     BaseAddr->SPTRCLR = QuadSPI_SPTRCLR_IPPTRC_MASK;
128 }
129 
130 
131 /*!
132  * @brief Clears AHB sequence pointer
133  *
134  */
Qspi_Ip_ClearAHBSeqPointer(QuadSPI_Type * BaseAddr)135 static inline void Qspi_Ip_ClearAHBSeqPointer(QuadSPI_Type *BaseAddr)
136 {
137     BaseAddr->SPTRCLR = QuadSPI_SPTRCLR_BFPTRC_MASK;
138 }
139 
140 
141 /*
142  * Enable QuadSPI device
143  */
Qspi_Ip_Enable(QuadSPI_Type * BaseAddr)144 static inline void Qspi_Ip_Enable(QuadSPI_Type *BaseAddr)
145 {
146     BaseAddr->MCR &= ~QuadSPI_MCR_MDIS_MASK;
147 
148 }
149 
150 
151 /*
152  * Disable QuadSPI device
153  */
Qspi_Ip_Disable(QuadSPI_Type * BaseAddr)154 static inline void Qspi_Ip_Disable(QuadSPI_Type *BaseAddr)
155 {
156     BaseAddr->MCR |= QuadSPI_MCR_MDIS_MASK;
157 
158 }
159 
160 #ifdef QuadSPI_MCR_DDR_EN_MASK
161 /*
162  * Enable DDR mode
163  */
QSPI_DDR_Enable(QuadSPI_Type * BaseAddr)164 static inline void QSPI_DDR_Enable(QuadSPI_Type *BaseAddr)
165 {
166     BaseAddr->MCR |= QuadSPI_MCR_DDR_EN_MASK;
167 }
168 
169 /*
170  * Disable DDR mode
171  */
QSPI_DDR_Disable(QuadSPI_Type * BaseAddr)172 static inline void QSPI_DDR_Disable(QuadSPI_Type *BaseAddr)
173 {
174     BaseAddr->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
175 }
176 #endif
177 
178 
179 
180 
181 /*
182  * Enable DQS
183  */
184 #ifdef QuadSPI_MCR_DQS_EN_MASK
QSPI_DQS_Enable(QuadSPI_Type * BaseAddr)185 static inline void QSPI_DQS_Enable(QuadSPI_Type *BaseAddr)
186 {
187     /* Enable DQS */
188     BaseAddr->MCR |= QuadSPI_MCR_DQS_EN_MASK;
189 }
190 #else
QSPI_DQS_Enable(const QuadSPI_Type * BaseAddr)191 static inline void QSPI_DQS_Enable(const QuadSPI_Type *BaseAddr)
192 {
193     /* Unused variable */
194     (void)BaseAddr;
195 }
196 #endif
197 
198 /*
199  * Disable DQS
200  */
201 #ifdef QuadSPI_MCR_DQS_EN_MASK
QSPI_DQS_Disable(QuadSPI_Type * BaseAddr)202 static inline void QSPI_DQS_Disable(QuadSPI_Type *BaseAddr)
203 {
204     /* Disable DQS */
205     BaseAddr->MCR &= ~QuadSPI_MCR_DQS_EN_MASK;
206 }
207 #else
QSPI_DQS_Disable(const QuadSPI_Type * BaseAddr)208 static inline void QSPI_DQS_Disable(const QuadSPI_Type *BaseAddr)
209 {
210     /* Unused variable */
211     (void)BaseAddr;
212 }
213 #endif
214 
215 
216 /*
217  * Assert QuadSPI sw reset bits
218  */
Qspi_Ip_SwResetOn(QuadSPI_Type * BaseAddr)219 static inline void Qspi_Ip_SwResetOn(QuadSPI_Type *BaseAddr)
220 {
221     BaseAddr->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK;
222 
223 }
224 
225 
226 /*
227  * Deassert QuadSPI sw reset bits
228  */
Qspi_Ip_SwResetOff(QuadSPI_Type * BaseAddr)229 static inline void Qspi_Ip_SwResetOff(QuadSPI_Type *BaseAddr)
230 {
231     BaseAddr->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
232 
233 }
234 
235 
236 /*
237  * Configure idle values for data lines 2:3
238  */
239 
240 #ifdef QuadSPI_MCR_ISD2FA_MASK
Qspi_Ip_SetIdleLineValuesA(QuadSPI_Type * BaseAddr,uint8 Iofa2IdleValue,uint8 Iofa3IdleValue)241 static inline void Qspi_Ip_SetIdleLineValuesA(QuadSPI_Type *BaseAddr,
242                                              uint8 Iofa2IdleValue,
243                                              uint8 Iofa3IdleValue
244                                             )
245 {
246     /* get value MCR register */
247     uint32 RegValue = (uint32)BaseAddr->MCR;
248 
249     /* set mask for ISD2FA, ISD3FA */
250     RegValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK  | QuadSPI_MCR_ISD3FA_MASK));
251     RegValue |= (QuadSPI_MCR_ISD2FA(Iofa2IdleValue) | QuadSPI_MCR_ISD3FA(Iofa3IdleValue));
252 
253     /* set again the MCR register */
254     BaseAddr->MCR = (uint32)RegValue;
255 }
256 #else
Qspi_Ip_SetIdleLineValuesA(const QuadSPI_Type * BaseAddr,uint8 Iofa2IdleValue,uint8 Iofa3IdleValue)257 static inline void Qspi_Ip_SetIdleLineValuesA(const QuadSPI_Type *BaseAddr,
258                                               uint8 Iofa2IdleValue,
259                                               uint8 Iofa3IdleValue
260                                              )
261 {
262     /* Unused variable */
263     (void)BaseAddr;
264     (void)Iofa2IdleValue;
265     (void)Iofa3IdleValue;
266 }
267 #endif
268 
269 
270 
271 /*
272  * Enable/Disable DQS slave delay chain
273  */
Qspi_Ip_DLLSlaveEnA(QuadSPI_Type * BaseAddr,boolean Enable)274 static inline void Qspi_Ip_DLLSlaveEnA(QuadSPI_Type *BaseAddr,
275                                        boolean Enable
276                                       )
277 {
278     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
279 
280     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_EN_MASK));
281     RegValue |= QuadSPI_DLLCRA_SLV_EN(Enable? 1U : 0U);
282     BaseAddr->DLLCRA = (uint32)RegValue;
283 }
284 
285 /*
286  * Activates/Deactivates DQS slave delay chain update
287  */
Qspi_Ip_DLLSlaveUpdateA(QuadSPI_Type * BaseAddr,boolean Enable)288 static inline void Qspi_Ip_DLLSlaveUpdateA(QuadSPI_Type *BaseAddr,
289                                            boolean Enable
290                                           )
291 {
292     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
293 
294     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_UPD_MASK));
295     RegValue |= QuadSPI_DLLCRA_SLV_UPD(Enable? 1U : 0U);
296     BaseAddr->DLLCRA = (uint32)RegValue;
297 }
298 
299 #ifdef QuadSPI_DLLCRA_DLLEN_MASK
300 /*
301  * Activates/Deactivates DQS slave delay chain update
302  */
Qspi_Ip_DLLEnableA(QuadSPI_Type * BaseAddr,boolean Enable)303 static inline void Qspi_Ip_DLLEnableA(QuadSPI_Type *BaseAddr,
304                                       boolean Enable
305                                      )
306 {
307     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
308 
309     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_DLLEN_MASK));
310     RegValue |= QuadSPI_DLLCRA_DLLEN(Enable? 1U : 0U);
311     BaseAddr->DLLCRA = (uint32)RegValue;
312 }
313 #endif
314 
315 /*
316  * Activates/Deactivates slave DLL bypass
317  */
Qspi_Ip_DLLSlaveBypassA(QuadSPI_Type * BaseAddr,boolean Enable)318 static inline void Qspi_Ip_DLLSlaveBypassA(QuadSPI_Type *BaseAddr,
319                                            boolean Enable
320                                           )
321 {
322     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
323 
324     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK));
325     RegValue |= QuadSPI_DLLCRA_SLV_DLL_BYPASS(Enable? 1U : 0U);
326     BaseAddr->DLLCRA = (uint32)RegValue;
327 }
328 
329 
330 #ifdef QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK
331 /*
332  * Activates/Deactivates slave auto update
333  */
Qspi_Ip_DLLSlaveAutoUpdateA(QuadSPI_Type * BaseAddr,boolean Enable)334 static inline void Qspi_Ip_DLLSlaveAutoUpdateA(QuadSPI_Type *BaseAddr,
335                                                boolean Enable
336                                               )
337 {
338     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
339 
340     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK));
341     RegValue |= QuadSPI_DLLCRA_SLAVE_AUTO_UPDT(Enable? 1U : 0U);
342     BaseAddr->DLLCRA = (uint32)RegValue;
343 }
344 #endif /* QuadSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK */
345 
346 /*
347  * Activates/Deactivates delay-chain for high frequency of operation
348  */
Qspi_Ip_DLLFreqEnA(QuadSPI_Type * BaseAddr,boolean Enable)349 static inline void Qspi_Ip_DLLFreqEnA(QuadSPI_Type *BaseAddr,
350                                       boolean Enable
351                                      )
352 {
353     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
354 
355     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_FREQEN_MASK));
356     RegValue |= QuadSPI_DLLCRA_FREQEN(Enable? 1U : 0U);
357     BaseAddr->DLLCRA = (uint32)RegValue;
358 }
359 
360 /*
361  * Sets slave delay chain coarse delay for DLL bypass mode
362  */
Qspi_Ip_DLLSetCoarseDelayA(QuadSPI_Type * BaseAddr,uint8 CoarseDelay)363 static inline void Qspi_Ip_DLLSetCoarseDelayA(QuadSPI_Type *BaseAddr,
364                                               uint8 CoarseDelay
365                                              )
366 {
367     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
368 
369     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK));
370     RegValue |= QuadSPI_DLLCRA_SLV_DLY_COARSE(CoarseDelay);
371     BaseAddr->DLLCRA = (uint32)RegValue;
372 }
373 
374 
375 /*
376  * Sets reference counter
377  */
Qspi_Ip_DLLSetReferenceCounterA(QuadSPI_Type * BaseAddr,uint8 ReferenceCounter)378 static inline void Qspi_Ip_DLLSetReferenceCounterA(QuadSPI_Type *BaseAddr,
379                                                    uint8 ReferenceCounter
380                                                   )
381 {
382 #ifdef QuadSPI_DLLCRA_DLL_REFCNTR_MASK
383     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
384 
385     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_DLL_REFCNTR_MASK));
386     RegValue |= QuadSPI_DLLCRA_DLL_REFCNTR(ReferenceCounter);
387     BaseAddr->DLLCRA = (uint32)RegValue;
388 #else
389     (void)BaseAddr;
390     (void)ReferenceCounter;
391 #endif  /* QuadSPI_DLLCRA_DLL_REFCNTR_MASK */
392 }
393 
394 #ifdef QuadSPI_DLLCRA_DLLRES_MASK
395 /*
396  * Sets Resolution
397  */
Qspi_Ip_DLLSetResolutionA(QuadSPI_Type * BaseAddr,uint8 Resolution)398 static inline void Qspi_Ip_DLLSetResolutionA(QuadSPI_Type *BaseAddr,
399                                              uint8 Resolution
400                                             )
401 {
402     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
403 
404     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_DLLRES_MASK));
405     RegValue |= QuadSPI_DLLCRA_DLLRES(Resolution);
406     BaseAddr->DLLCRA = (uint32)RegValue;
407 }
408 #endif /* QuadSPI_DLLCRA_DLLRES_MASK */
409 
410 /*
411  * Sets slave delay chain coarse offset
412  */
Qspi_Ip_DLLSetCoarseOffsetA(QuadSPI_Type * BaseAddr,uint8 CoarseDelay)413 static inline void Qspi_Ip_DLLSetCoarseOffsetA(QuadSPI_Type *BaseAddr,
414                                                uint8 CoarseDelay
415                                               )
416 {
417     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
418 
419     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK));
420     RegValue |= QuadSPI_DLLCRA_SLV_DLY_OFFSET(CoarseDelay);
421     BaseAddr->DLLCRA = (uint32)RegValue;
422 }
423 
424 /*
425  * Sets slave delay chain fine offset
426  */
Qspi_Ip_DLLSetFineOffsetA(QuadSPI_Type * BaseAddr,uint8 FineDelay)427 static inline void Qspi_Ip_DLLSetFineOffsetA(QuadSPI_Type *BaseAddr,
428                                              uint8 FineDelay
429                                             )
430 {
431     uint32 RegValue = (uint32)BaseAddr->DLLCRA;
432 
433     RegValue &= (uint32)(~((uint32)QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK));
434     RegValue |= QuadSPI_DLLCRA_SLV_FINE_OFFSET(FineDelay);
435     BaseAddr->DLLCRA = (uint32)RegValue;
436 }
437 
438 
439 /*
440  * Checks high frequency slave delay chain lock status
441  */
Qspi_Ip_DLLGetSlaveLockStatusA(const QuadSPI_Type * BaseAddr)442 static inline boolean Qspi_Ip_DLLGetSlaveLockStatusA(const QuadSPI_Type *BaseAddr)
443 {
444 #ifdef QuadSPI_DLLSR_SLVA_LOCK_MASK
445     uint32 RegValue = (uint32)BaseAddr->DLLSR;
446 
447     RegValue = (RegValue & QuadSPI_DLLSR_SLVA_LOCK_MASK) >> QuadSPI_DLLSR_SLVA_LOCK_SHIFT;
448     return (RegValue != 0U)? TRUE : FALSE;
449 #else
450     (void)BaseAddr;
451     return FALSE;
452 #endif
453 }
454 
455 
456 /*
457  * Checks DLL lock status
458  */
Qspi_Ip_DLLGetLockStatusA(const QuadSPI_Type * BaseAddr)459 static inline boolean Qspi_Ip_DLLGetLockStatusA(const QuadSPI_Type *BaseAddr)
460 {
461 #ifdef QuadSPI_DLLSR_DLLA_LOCK_MASK
462     uint32 RegValue = (uint32)BaseAddr->DLLSR;
463 
464     RegValue = (RegValue & QuadSPI_DLLSR_DLLA_LOCK_MASK) >> QuadSPI_DLLSR_DLLA_LOCK_SHIFT;
465     return (RegValue != 0U)? TRUE : FALSE;
466 #else
467     (void)BaseAddr;
468     return FALSE;
469 #endif
470 }
471 
472 /*
473  * Checks high frequency slave delay chain error status
474  */
Qspi_Ip_DLLGetErrorStatusA(const QuadSPI_Type * BaseAddr)475 static inline boolean Qspi_Ip_DLLGetErrorStatusA(const QuadSPI_Type *BaseAddr)
476 {
477 #ifdef QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK
478     uint32 RegValue = (uint32)BaseAddr->DLLSR;
479 
480     RegValue = RegValue & (QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK | QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK);
481     return (RegValue != 0U)? TRUE : FALSE;
482 #else
483     (void)BaseAddr;
484     return FALSE;
485 #endif
486 }
487 
488 
489 
490 /*
491  * Configure external flash memory map size A
492  */
Qspi_Ip_SetMemMapSizeA(uint32 instance,QuadSPI_Type * BaseAddr,uint32 SizeA1,uint32 SizeA2)493 static inline void Qspi_Ip_SetMemMapSizeA(uint32 instance,
494                                           QuadSPI_Type *BaseAddr,
495                                           uint32 SizeA1,
496                                           uint32 SizeA2
497                                          )
498 {
499     BaseAddr->SFA1AD = Qspi_Ip_AhbAddress[instance] + SizeA1;
500     BaseAddr->SFA2AD = Qspi_Ip_AhbAddress[instance] + SizeA1 + SizeA2;
501 }
502 
503 
504 /*
505  * Set CS hold time in serial clock Cycles
506  */
Qspi_Ip_SetCsHoldTime(QuadSPI_Type * BaseAddr,uint8 Cycles)507 static inline void Qspi_Ip_SetCsHoldTime(QuadSPI_Type *BaseAddr,
508                                          uint8 Cycles
509                                         )
510 {
511     uint32 RegValue = (uint32)BaseAddr->FLSHCR;
512 
513     RegValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSH_MASK));
514     RegValue |= QuadSPI_FLSHCR_TCSH(Cycles);
515     BaseAddr->FLSHCR = (uint32)RegValue;
516 }
517 
518 
519 /*
520  * Set CS setup time
521  */
Qspi_Ip_SetCsSetupTime(QuadSPI_Type * BaseAddr,uint8 Cycles)522 static inline void Qspi_Ip_SetCsSetupTime(QuadSPI_Type *BaseAddr,
523                                           uint8 Cycles
524                                          )
525 {
526     uint32 RegValue = (uint32)BaseAddr->FLSHCR;
527 
528     RegValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSS_MASK));
529     RegValue |= QuadSPI_FLSHCR_TCSS(Cycles);
530     BaseAddr->FLSHCR = (uint32)RegValue;
531 }
532 
533 
534 #ifdef QuadSPI_FLSHCR_TDH_MASK
535 /*
536  * Set data in hold time
537  */
Qspi_Ip_SetDataInHoldTime(QuadSPI_Type * BaseAddr,Qspi_Ip_FlashDataAlignType Enable)538 static inline void Qspi_Ip_SetDataInHoldTime(QuadSPI_Type *BaseAddr,
539                                              Qspi_Ip_FlashDataAlignType Enable
540                                             )
541 {
542     uint32 RegValue = (uint32)BaseAddr->FLSHCR;
543 
544     RegValue &= (uint32)(~(QuadSPI_FLSHCR_TDH_MASK));
545     RegValue |= QuadSPI_FLSHCR_TDH(Enable);
546     BaseAddr->FLSHCR = (uint32)RegValue;
547 }
548 #endif /* QuadSPI_FLSHCR_TDH_MASK */
549 
550 
551 /*
552  * Sets AHB buffer 0 configuration
553  */
Qspi_Ip_SetAhbBuf0(QuadSPI_Type * BaseAddr,uint16 Size,uint8 Master)554 static inline void Qspi_Ip_SetAhbBuf0(QuadSPI_Type *BaseAddr,
555                                       uint16 Size,
556                                       uint8 Master
557                                      )
558 {
559     BaseAddr->BUF0CR =  QuadSPI_BUF0CR_ADATSZ((uint32)Size >> 3U)
560                       | QuadSPI_BUF0CR_MSTRID(Master);
561 }
562 
563 
564 /*
565  * Sets AHB buffer 1 configuration
566  */
Qspi_Ip_SetAhbBuf1(QuadSPI_Type * BaseAddr,uint16 Size,uint8 Master)567 static inline void Qspi_Ip_SetAhbBuf1(QuadSPI_Type *BaseAddr,
568                                       uint16 Size,
569                                       uint8 Master
570                                      )
571 {
572     BaseAddr->BUF1CR =  QuadSPI_BUF1CR_ADATSZ((uint32)Size >> 3U)
573                       | QuadSPI_BUF1CR_MSTRID(Master);
574 }
575 
576 
577 /*
578  * Sets AHB buffer 2 configuration
579  */
Qspi_Ip_SetAhbBuf2(QuadSPI_Type * BaseAddr,uint16 Size,uint8 Master)580 static inline void Qspi_Ip_SetAhbBuf2(QuadSPI_Type *BaseAddr,
581                                       uint16 Size,
582                                       uint8 Master
583                                      )
584 {
585     BaseAddr->BUF2CR =  QuadSPI_BUF2CR_ADATSZ((uint32)Size >> 3U)
586                       | QuadSPI_BUF2CR_MSTRID(Master);
587 }
588 
589 
590 /*
591  * Sets AHB buffer 3 configuration
592  */
Qspi_Ip_SetAhbBuf3(QuadSPI_Type * BaseAddr,uint16 Size,uint8 Master,boolean AllMasters)593 static inline void Qspi_Ip_SetAhbBuf3(QuadSPI_Type *BaseAddr,
594                                        uint16 Size,
595                                        uint8 Master,
596                                        boolean AllMasters
597                                      )
598 {
599     BaseAddr->BUF3CR =  QuadSPI_BUF3CR_ADATSZ((uint32)Size >> 3U)
600                       | QuadSPI_BUF3CR_MSTRID(Master)
601                       | QuadSPI_BUF3CR_ALLMST(AllMasters? 1U : 0U);
602 }
603 
604 
605 /*
606  * Sets AHB buffer 0 index. Parameter represents desired end index of the buffer.
607  */
Qspi_Ip_SetAhbBuf0Ind(QuadSPI_Type * BaseAddr,uint32 Index)608 static inline void Qspi_Ip_SetAhbBuf0Ind(QuadSPI_Type *BaseAddr,
609                                          uint32 Index
610                                         )
611 {
612     BaseAddr->BUF0IND =  Index;
613 }
614 
615 
616 /*
617  * Sets AHB buffer 1 index. Parameter represents desired end index of the buffer.
618  */
Qspi_Ip_SetAhbBuf1Ind(QuadSPI_Type * BaseAddr,uint32 Index)619 static inline void Qspi_Ip_SetAhbBuf1Ind(QuadSPI_Type *BaseAddr,
620                                          uint32 Index
621                                         )
622 {
623     BaseAddr->BUF1IND =  Index;
624 }
625 
626 
627 /*
628  * Sets AHB buffer 2 index. Parameter represents desired end index of the buffer.
629  */
Qspi_Ip_SetAhbBuf2Ind(QuadSPI_Type * BaseAddr,uint32 Index)630 static inline void Qspi_Ip_SetAhbBuf2Ind(QuadSPI_Type *BaseAddr,
631                                          uint32 Index
632                                         )
633 {
634     BaseAddr->BUF2IND =  Index;
635 }
636 
637 
638 /*
639  * Sets address for IP transactions
640  */
Qspi_Ip_SetIpAddr(QuadSPI_Type * BaseAddr,uint32 Addr)641 static inline void Qspi_Ip_SetIpAddr(QuadSPI_Type *BaseAddr,
642                                      uint32 Addr
643                                     )
644 {
645     BaseAddr->SFAR = Addr;
646 }
647 
648 
649 /*
650  * Sets flash address options
651  */
652 #ifdef QuadSPI_SFACR_CAS_MASK
Qspi_Ip_SetAddrOptions(QuadSPI_Type * BaseAddr,uint8 ColumnAddr,boolean WordAdressable)653 static inline void Qspi_Ip_SetAddrOptions(QuadSPI_Type *BaseAddr,
654                                           uint8 ColumnAddr,
655                                           boolean WordAdressable
656                                          )
657 {
658     /* Set Column address and Word addressable */
659     BaseAddr->SFACR = QuadSPI_SFACR_CAS(ColumnAddr)
660                     | QuadSPI_SFACR_WA(WordAdressable ? 1U : 0U);
661 }
662 #else
Qspi_Ip_SetAddrOptions(const QuadSPI_Type * BaseAddr,uint8 ColumnAddr,boolean WordAdressable)663 static inline void Qspi_Ip_SetAddrOptions(const QuadSPI_Type *BaseAddr,
664                                           uint8 ColumnAddr,
665                                           boolean WordAdressable
666                                          )
667 {
668     /* Unused variable */
669     (void)BaseAddr;
670     (void)ColumnAddr;
671     (void)WordAdressable;
672 }
673 #endif
674 
675 
676 /*
677  * Configures parameters related to sampling Rx data
678  */
Qspi_Ip_SetRxCfg(QuadSPI_Type * BaseAddr,Qspi_Ip_SampleDelayType Delay,Qspi_Ip_SamplePhaseType ClockPhase)679 static inline void Qspi_Ip_SetRxCfg(QuadSPI_Type *BaseAddr,
680                                     Qspi_Ip_SampleDelayType Delay,
681                                     Qspi_Ip_SamplePhaseType ClockPhase
682                                    )
683 {
684     BaseAddr->SMPR = QuadSPI_SMPR_FSPHS(ClockPhase)
685                    | QuadSPI_SMPR_FSDLY(Delay);
686 }
687 
688 
689 /*
690  * Configures parameters related to sampling Rx data
691  */
Qspi_Ip_SetRxDLLTapA(QuadSPI_Type * BaseAddr,uint8 Taps)692 static inline void Qspi_Ip_SetRxDLLTapA(QuadSPI_Type *BaseAddr,
693                                         uint8 Taps
694                                        )
695 {
696     uint32 RegValue = BaseAddr->SMPR;
697 
698     RegValue &= ~QuadSPI_SMPR_DLLFSMPFA_MASK;
699     RegValue |= QuadSPI_SMPR_DLLFSMPFA(Taps);
700     BaseAddr->SMPR = RegValue;
701 }
702 
703 
704 
705 
706 
707 /*
708  * Checks if module is busy with a transaction
709  */
Qspi_Ip_GetBusyStatus(const QuadSPI_Type * BaseAddr)710 static inline boolean Qspi_Ip_GetBusyStatus(const QuadSPI_Type *BaseAddr)
711 {
712     uint32 RegValue = (uint32)BaseAddr->SR;
713 
714     RegValue = (RegValue & QuadSPI_SR_BUSY_MASK) >> QuadSPI_SR_BUSY_SHIFT;
715     return (RegValue != 0U)? TRUE : FALSE;
716 }
717 
718 
719 /*
720  * Returns the current fill level of the Rx buffer
721  */
Qspi_Ip_GetRxBufFill(const QuadSPI_Type * BaseAddr)722 static inline uint32 Qspi_Ip_GetRxBufFill(const QuadSPI_Type *BaseAddr)
723 {
724     uint32 RegValue = (uint32)BaseAddr->RBSR;
725 
726     RegValue = (RegValue & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
727     return RegValue;
728 }
729 
730 
731 /*
732  * Checks if enough Rx data is available, according to the Watermark setting
733  */
Qspi_Ip_GetRxDataEvent(const QuadSPI_Type * BaseAddr)734 static inline boolean Qspi_Ip_GetRxDataEvent(const QuadSPI_Type *BaseAddr)
735 {
736     uint32 RegValue = (uint32)BaseAddr->SR;
737 
738     RegValue = (RegValue & QuadSPI_SR_RXWE_MASK) >> QuadSPI_SR_RXWE_SHIFT;
739     return (RegValue != 0U)? TRUE : FALSE;
740 }
741 
742 
743 /*
744  * Returns Tx buffer fill level expressed in 4-byte entries
745  */
Qspi_Ip_GetTxBufFill(const QuadSPI_Type * BaseAddr)746 static inline uint32 Qspi_Ip_GetTxBufFill(const QuadSPI_Type *BaseAddr)
747 {
748     uint32 RegValue = (uint32)BaseAddr->TBSR;
749 
750     RegValue = (RegValue & QuadSPI_TBSR_TRBFL_MASK) >> QuadSPI_TBSR_TRBFL_SHIFT;
751     return RegValue;
752 }
753 
754 
755 #ifdef QuadSPI_SR_TXWA_MASK
756 /*
757  * Checks the Tx buffer Watermark.
758  * Returns TRUE if number of buffer entries specified by the Watermark is available.
759  */
Qspi_Ip_GetTxWatermarkAvailable(const QuadSPI_Type * BaseAddr)760 static inline boolean Qspi_Ip_GetTxWatermarkAvailable(const QuadSPI_Type *BaseAddr)
761 {
762     uint32 RegValue = (uint32)BaseAddr->SR;
763 
764     RegValue = (RegValue & QuadSPI_SR_TXWA_MASK) >> QuadSPI_SR_TXWA_SHIFT;
765     return (RegValue != 0U)? TRUE : FALSE;
766 }
767 #endif
768 
769 
770 /*
771  * Writes data in the Tx buffer
772  */
Qspi_Ip_WriteTxData(QuadSPI_Type * BaseAddr,uint32 Data)773 static inline void Qspi_Ip_WriteTxData(QuadSPI_Type *BaseAddr, uint32 Data)
774 {
775     BaseAddr->TBDR = Data;
776 }
777 
778 
779 /*
780  * Returns the address of the Tx data register
781  */
Qspi_Ip_GetTxDataAddr(const QuadSPI_Type * BaseAddr)782 static inline uint32 Qspi_Ip_GetTxDataAddr(const QuadSPI_Type *BaseAddr)
783 {
784     return (Qspi_Ip_UintPtrType)&(BaseAddr->TBDR);
785 }
786 
787 
788 /*
789  * Returns the address of the first Rx data register
790  */
Qspi_Ip_GetRxDataAddr(const QuadSPI_Type * BaseAddr)791 static inline uint32 Qspi_Ip_GetRxDataAddr(const QuadSPI_Type *BaseAddr)
792 {
793     return (Qspi_Ip_UintPtrType)&(BaseAddr->RBDR[0U]);
794 }
795 
796 
797 /*
798  * Enables Tx DMA request (when Tx buffer has room for more data)
799  */
Qspi_Ip_EnableTxDmaReq(QuadSPI_Type * BaseAddr)800 static inline void Qspi_Ip_EnableTxDmaReq(QuadSPI_Type *BaseAddr)
801 {
802     BaseAddr->RSER |= QuadSPI_RSER_TBFDE_MASK;
803 }
804 
805 
806 /*
807  * Enables Rx DMA request (when Rx buffer has room for more data)
808  */
Qspi_Ip_EnableRxDmaReq(QuadSPI_Type * BaseAddr)809 static inline void Qspi_Ip_EnableRxDmaReq(QuadSPI_Type *BaseAddr)
810 {
811     BaseAddr->RSER |= QuadSPI_RSER_RBDDE_MASK;
812 }
813 
814 
815 /*
816  * Disables both Rx and Tx DMA requests
817  */
Qspi_Ip_DisableDmaReq(QuadSPI_Type * BaseAddr)818 static inline void Qspi_Ip_DisableDmaReq(QuadSPI_Type *BaseAddr)
819 {
820     BaseAddr->RSER &= ~(QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK);
821 }
822 
823 
824 /*
825  * Perform a POP operation on the Rx buffer, removing Rx_watermark entries
826  */
Qspi_Ip_RxPop(QuadSPI_Type * BaseAddr)827 static inline void Qspi_Ip_RxPop(QuadSPI_Type *BaseAddr)
828 {
829     BaseAddr->FR = QuadSPI_FR_RBDF_MASK;
830 }
831 
832 
833 /*
834  * Configures the Watermark for the Rx buffer, expressed in number of 4-byte entries
835  */
Qspi_Ip_SetRxWatermark(QuadSPI_Type * BaseAddr,uint8 Watermark)836 static inline void Qspi_Ip_SetRxWatermark(QuadSPI_Type *BaseAddr,
837                                           uint8 Watermark
838                                          )
839 {
840     uint32 RegValue = (uint32)BaseAddr->RBCT;
841 
842     RegValue &= (uint32)(~((uint32)QuadSPI_RBCT_WMRK_MASK));
843     RegValue |= QuadSPI_RBCT_WMRK((uint32)Watermark - 1U);
844     BaseAddr->RBCT = (uint32)RegValue;
845 }
846 
847 
848 #ifdef QuadSPI_RBCT_RXBRD_MASK
849 /*
850  * Configures the rx for the Rx buffer, expressed in number of 4-byte entries
851  */
Qspi_Ip_SetRxBufReadout(QuadSPI_Type * BaseAddr,uint8 Readout)852 static inline void Qspi_Ip_SetRxBufReadout(QuadSPI_Type *BaseAddr,
853                                            uint8 Readout
854                                           )
855 {
856     uint32 RegValue = (uint32)BaseAddr->RBCT;
857 
858     RegValue &= (uint32)(~((uint32)QuadSPI_RBCT_RXBRD_MASK));
859     RegValue |= QuadSPI_RBCT_RXBRD(Readout);
860     BaseAddr->RBCT = (uint32)RegValue;
861 }
862 #endif
863 
864 
865 /*
866  * Configures the Watermark for the Tx buffer, expressed in number of 4-byte entries
867  */
Qspi_Ip_SetTxWatermark(QuadSPI_Type * BaseAddr,uint8 Watermark)868 static inline void Qspi_Ip_SetTxWatermark(QuadSPI_Type *BaseAddr,
869                                           uint8 Watermark
870                                          )
871 {
872     uint32 RegValue = (uint32)BaseAddr->TBCT;
873 
874     RegValue &= (uint32)(~((uint32)QuadSPI_TBCT_WMRK_MASK));
875     RegValue |= QuadSPI_TBCT_WMRK(Watermark);
876     BaseAddr->TBCT = (uint32)RegValue;
877 }
878 
879 
880 /*
881  * Enables interrupts specified by the mask parameter
882  */
Qspi_Ip_EnableInt(QuadSPI_Type * BaseAddr,uint32 Mask)883 static inline void Qspi_Ip_EnableInt(QuadSPI_Type *BaseAddr,
884                                      uint32 Mask
885                                     )
886 {
887     BaseAddr->RSER |= Mask;
888 }
889 
890 
891 /*
892  * Disables interrupts specified by the mask parameter
893  */
Qspi_Ip_DisableInt(QuadSPI_Type * BaseAddr,uint32 Mask)894 static inline void Qspi_Ip_DisableInt(QuadSPI_Type *BaseAddr,
895                                       uint32 Mask
896                                      )
897 {
898     BaseAddr->RSER &= ~Mask;
899 }
900 
901 
902 /*
903  * Clears interrupt flags specified by the mask parameter
904  */
Qspi_Ip_ClearIntFlag(QuadSPI_Type * BaseAddr,uint32 Mask)905 static inline void Qspi_Ip_ClearIntFlag(QuadSPI_Type *BaseAddr,
906                                         uint32 Mask
907                                        )
908 {
909     BaseAddr->FR = Mask;
910 }
911 
912 
913 /*
914  * Configure DQS clock for sampling read data
915  */
Qspi_Ip_SetDQSSourceA(QuadSPI_Type * BaseAddr,Qspi_Ip_ReadModeType ReadModeA)916 static inline void Qspi_Ip_SetDQSSourceA(QuadSPI_Type *BaseAddr,
917                                          Qspi_Ip_ReadModeType ReadModeA)
918 {
919     /* get the value of MCR register */
920     uint32 RegValue = (uint32)BaseAddr->MCR;
921 
922     RegValue &= (uint32)(~QuadSPI_MCR_DQS_FA_SEL_MASK);
923     /* switch for modes */
924     switch (ReadModeA)
925     {
926 #if (FEATURE_QSPI_INTERNAL_DQS == 1)
927         case QSPI_IP_READ_MODE_INTERNAL_DQS:
928                 /* if it is DQS internal */
929                 RegValue |= QuadSPI_MCR_DQS_FA_SEL(0U);
930                 break;
931 #endif
932 #if (FEATURE_QSPI_LOOPBACK == 1)
933         case QSPI_IP_READ_MODE_LOOPBACK:
934                 /* if it is Pad loopback */
935                 RegValue |= QuadSPI_MCR_DQS_FA_SEL(1U);
936                 break;
937 #endif
938 #if (FEATURE_QSPI_LOOPBACK_DQS == 1)
939         case QSPI_IP_READ_MODE_LOOPBACK_DQS:
940                 /* if it is DQS pad loopback */
941                 RegValue |= QuadSPI_MCR_DQS_FA_SEL(2U);
942                 break;
943 #endif
944         case QSPI_IP_READ_MODE_EXTERNAL_DQS:
945                 /* if it is DQS external */
946                 RegValue |= QuadSPI_MCR_DQS_FA_SEL(3U);
947                 break;
948         default:
949                 ; /* Not possible */
950                 break;
951     }
952     BaseAddr->MCR = (uint32)RegValue;
953 }
954 
955 
956 
957 
958 
959 
960 
961 
962 #ifdef QuadSPI_SFACR_BYTE_SWAP_MASK
Qspi_Ip_SetByteSwap(QuadSPI_Type * BaseAddr,boolean ByteSwap)963 static inline void Qspi_Ip_SetByteSwap(QuadSPI_Type *BaseAddr,
964                                        boolean ByteSwap
965                                       )
966 {
967     /* Get the value of SFACR register */
968     uint32 RegValue = (uint32)BaseAddr->SFACR;
969 
970     /* Set mask */
971     RegValue &= (uint32)(~QuadSPI_SFACR_BYTE_SWAP_MASK);
972     RegValue |= QuadSPI_SFACR_BYTE_SWAP(ByteSwap? 1U : 0U);
973     /* Update again the SFACR register */
974     BaseAddr->SFACR = (uint32)RegValue;
975 }
976 #else
Qspi_Ip_SetByteSwap(const QuadSPI_Type * BaseAddr,boolean ByteSwap)977 static inline void Qspi_Ip_SetByteSwap(const QuadSPI_Type *BaseAddr,
978                                        boolean ByteSwap
979                                       )
980 {
981     /* Unused variable */
982     (void)BaseAddr;
983     (void)ByteSwap;
984 }
985 #endif
986 
987 #ifdef QuadSPI_MCR_SCLKCFG_MASK
988 /*
989  * Configure chip-specific clock options
990  */
Qspi_Ip_SetClockOptions(QuadSPI_Type * BaseAddr,uint8 Option)991 static inline void Qspi_Ip_SetClockOptions(QuadSPI_Type *BaseAddr,
992                                            uint8 Option
993                                           )
994 {
995     uint32 RegValue = (uint32)BaseAddr->MCR;
996 
997     RegValue &= (uint32)(~QuadSPI_MCR_SCLKCFG_MASK);
998     RegValue |= QuadSPI_MCR_SCLKCFG(Option);
999     BaseAddr->MCR = (uint32)RegValue;
1000 }
1001 #endif
1002 
1003 #ifdef QuadSPI_SOCCR_SOCCFG_MASK
1004 /*
1005  * Configure chip-specific options
1006  */
Qspi_Ip_SetChipOptions(QuadSPI_Type * BaseAddr,uint32 Option)1007 static inline void Qspi_Ip_SetChipOptions(QuadSPI_Type *BaseAddr,
1008                                           uint32 Option
1009                                          )
1010 {
1011     BaseAddr->SOCCR = Option;
1012 }
1013 #endif
1014 
1015 
1016 
1017 
1018 #if (FEATURE_QSPI_HAS_SFP == 1)
1019 
1020 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1021  * @brief Enable/disable all or just MDAD/FRAD access controls.
1022  *
1023  * Master Global Configuration (MGC):
1024  * - Global Valid access control (GVLD)
1025  * - Global Valid MDAD (GVLDMDAD)
1026  * - Global Valid FRAD (GVLDFRAD)
1027  *
1028  * @param[in] BaseAddr base address of the given QuadSPI instance
1029  * @param[in] AccessControl an enum selecting all or just MDAD/FRAD access controls
1030  * @param[in] Enabled the value of the selected field
1031  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetAccessControls(QuadSPI_Type * BaseAddr,Qspi_Ip_Sfp_AccessControlType AccessControl,sint8 Enabled)1032 static inline void Qspi_Ip_Sfp_SetAccessControls
1033 (
1034     QuadSPI_Type * BaseAddr,
1035     Qspi_Ip_Sfp_AccessControlType AccessControl,
1036     sint8 Enabled)
1037 {
1038     uint32 RegValue = BaseAddr->MGC;
1039 
1040     switch (AccessControl)
1041     {
1042         case QSPI_IP_SFP_ALL:
1043         {
1044             RegValue &= ~QuadSPI_MGC_GVLD_MASK;
1045             RegValue |= QuadSPI_MGC_GVLD(Enabled);
1046         }
1047         break;
1048 
1049         case QSPI_IP_SFP_MDAD:
1050         {
1051             RegValue &= ~QuadSPI_MGC_GVLDMDAD_MASK;
1052             RegValue |= QuadSPI_MGC_GVLDMDAD(Enabled);
1053         }
1054         break;
1055 
1056         case QSPI_IP_SFP_FRAD:
1057         {
1058             RegValue &= ~QuadSPI_MGC_GVLDFRAD_MASK;
1059             RegValue |= QuadSPI_MGC_GVLDFRAD(Enabled);
1060         }
1061         break;
1062 
1063         default:
1064             /* invalid selection */
1065         break;
1066     }
1067 
1068     BaseAddr->MGC = RegValue;
1069 }
1070 
1071 #if (QSPI_IP_SFP_ENABLE_GLOBAL == STD_ON)
1072 
1073 #if (QSPI_IP_SFP_ENABLE_MDAD == STD_ON)
1074 
1075 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1076  * @brief Program the VLD bit of a Target Group queue
1077  *
1078  * Target Group n Master Domain Access Descriptor (TG0MDAD - TG1MDAD):
1079  * - Valid (VLD)
1080  *
1081  * @param[in] BaseAddr base address of the given QuadSPI instance
1082  * @param[in] MdadInstance index of the target group to be configured
1083  * @param[in] Valid value to be written into the VLD bit
1084  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetTgValid(QuadSPI_Type * BaseAddr,uint8 MdadInstance,boolean Valid)1085 static inline void Qspi_Ip_Sfp_SetTgValid
1086 (
1087     QuadSPI_Type * BaseAddr,
1088     uint8 MdadInstance,
1089     boolean Valid)
1090 {
1091     if (MdadInstance < QuadSPI_MDAD_COUNT)
1092     {
1093         uint32 RegValue = BaseAddr->MDAD[MdadInstance].TGMDAD;
1094         RegValue &= ~QuadSPI_TGMDAD_VLD_MASK;
1095         RegValue |= QuadSPI_TGMDAD_VLD(Valid ? 1U : 0U);
1096         BaseAddr->MDAD[MdadInstance].TGMDAD = RegValue;
1097     }
1098 }
1099 
1100 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1101  * @brief Configure the Secure Attribute field of a Target Group queue
1102  *
1103  * Target Group n Master Domain Access Descriptor (TG0MDAD - TG1MDAD):
1104  * - Secure Attribute (SA)
1105  *
1106  * @param[in] BaseAddr base address of the given QuadSPI instance
1107  * @param[in] MdadInstance index of the target group to be configured
1108  * @param[in] SecureAttribute value of the SA field
1109  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetTgSecureAttribute(QuadSPI_Type * BaseAddr,uint8 MdadInstance,Qspi_Ip_SfpSaType SecureAttribute)1110 static inline void Qspi_Ip_Sfp_SetTgSecureAttribute
1111 (
1112     QuadSPI_Type * BaseAddr,
1113     uint8 MdadInstance,
1114     Qspi_Ip_SfpSaType SecureAttribute)
1115 {
1116     if (MdadInstance < QuadSPI_MDAD_COUNT)
1117     {
1118         uint32 RegValue = BaseAddr->MDAD[MdadInstance].TGMDAD;
1119         RegValue &= ~QuadSPI_TGMDAD_SA_MASK;
1120         RegValue |= QuadSPI_TGMDAD_SA(SecureAttribute);
1121         BaseAddr->MDAD[MdadInstance].TGMDAD = RegValue;
1122     }
1123 }
1124 
1125 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1126  * @brief Configure the MASKTYPE field of the given target group queue.
1127  *
1128  * Target Group n Master Domain Access Descriptor (TG0MDAD - TG1MDAD):
1129  * - Mask Type (MASKTYPE)
1130  *
1131  * @param[in] BaseAddr base address of the given QuadSPI instance
1132  * @param[in] MdadInstance index of the target group to be configured
1133  * @param[in] MaskType value to be written in the mask type field
1134  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetTgMaskType(QuadSPI_Type * BaseAddr,uint8 MdadInstance,Qspi_Ip_SfpMasktypeType MaskType)1135 static inline void Qspi_Ip_Sfp_SetTgMaskType
1136 (
1137     QuadSPI_Type * BaseAddr,
1138     uint8 MdadInstance,
1139     Qspi_Ip_SfpMasktypeType MaskType)
1140 {
1141     if (MdadInstance < QuadSPI_MDAD_COUNT)
1142     {
1143         uint32 RegValue = BaseAddr->MDAD[MdadInstance].TGMDAD;
1144         RegValue &= ~QuadSPI_TGMDAD_MASKTYPE_MASK;
1145         RegValue |= QuadSPI_TGMDAD_MASKTYPE(MaskType);
1146         BaseAddr->MDAD[MdadInstance].TGMDAD = RegValue;
1147     }
1148 }
1149 
1150 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1151  * @brief Configure the MASK field of the given target group queue.
1152  *
1153  * Target Group n Master Domain Access Descriptor (TG0MDAD - TG1MDAD):
1154  * - Mask (MASK)
1155  *
1156  * @param[in] BaseAddr base address of the given QuadSPI instance
1157  * @param[in] MdadInstance index of the target group to be configured
1158  * @param[in] Mask value that is written into the 6-bit mask
1159  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetTgMask(QuadSPI_Type * BaseAddr,uint8 MdadInstance,uint8 Mask)1160 static inline void Qspi_Ip_Sfp_SetTgMask
1161 (
1162     QuadSPI_Type * BaseAddr,
1163     uint8 MdadInstance,
1164     uint8 Mask)
1165 {
1166     if (MdadInstance < QuadSPI_MDAD_COUNT)
1167     {
1168         uint32 RegValue = BaseAddr->MDAD[MdadInstance].TGMDAD;
1169         RegValue &= ~QuadSPI_TGMDAD_MASK_MASK;
1170         RegValue |= QuadSPI_TGMDAD_MASK(Mask);
1171         BaseAddr->MDAD[MdadInstance].TGMDAD = RegValue;
1172     }
1173 }
1174 
1175 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1176  * @brief Configure the Domain ID reference of the given target group queue.
1177  *
1178  * Target Group n Master Domain Access Descriptor (TG0MDAD - TG1MDAD):
1179  * - Domain ID Reference (MIDMATCH)
1180  *
1181  * @param[in] BaseAddr base address of the given QuadSPI instance
1182  * @param[in] MdadInstance index of the target group to be configured
1183  * @param[in] DomainIdMatch value of MIDMATCH field
1184  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetTgDomainIdMatch(QuadSPI_Type * BaseAddr,uint8 MdadInstance,uint8 DomainIdMatch)1185 static inline void Qspi_Ip_Sfp_SetTgDomainIdMatch
1186 (
1187     QuadSPI_Type * BaseAddr,
1188     uint8 MdadInstance,
1189     uint8 DomainIdMatch)
1190 {
1191     if (MdadInstance < QuadSPI_MDAD_COUNT)
1192     {
1193         uint32 RegValue = BaseAddr->MDAD[MdadInstance].TGMDAD;
1194         RegValue &= ~QuadSPI_TGMDAD_MIDMATCH_MASK;
1195         RegValue |= QuadSPI_TGMDAD_MIDMATCH(DomainIdMatch);
1196         BaseAddr->MDAD[MdadInstance].TGMDAD = RegValue;
1197     }
1198 }
1199 
1200 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1201  * @brief Indicates whether the IPCR-IDATZ, IPCR-SEQID and PAR stored in this target group queue is
1202  * valid and queue is locked.
1203  *
1204  * Target Group n IPCR Status (TG0IPCRS - TG1IPCRS):
1205  * - Valid (VLD)
1206  *
1207  * @param[in] BaseAddr base address of the given QuadSPI instance
1208  * @param[in] MdadInstance index of the target group to be configured
1209  *
1210  * @retval TRUE: valid
1211  * @retval FALSE: invalid
1212  * @retval FALSE: the MdadInstance is invalid
1213  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_TgIpcrsValid(QuadSPI_Type const * BaseAddr,uint8 MdadInstance)1214 static inline boolean Qspi_Ip_Sfp_TgIpcrsValid
1215 (
1216     QuadSPI_Type const * BaseAddr,
1217     uint8 MdadInstance)
1218 {
1219     uint32 RegValue = 0U;
1220     if (MdadInstance < QuadSPI_MDAD_COUNT)
1221     {
1222         RegValue = (BaseAddr->MDAD[MdadInstance].TGIPCRS & QuadSPI_TGIPCRS_VLD_MASK) >> QuadSPI_TGIPCRS_VLD_SHIFT;
1223     }
1224     return (RegValue != 0U) ? TRUE : FALSE;
1225 }
1226 
1227 #endif /* QSPI_IP_SFP_ENABLE_MDAD */
1228 
1229 #if (QSPI_IP_SFP_ENABLE_FRAD == STD_ON)
1230 
1231 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1232  * @brief Specifies the specific flash memory region starting address (around 64 KB boundary).
1233  *
1234  * Flash Region Start Address (FRAD0_WORD0 - FRAD7_WORD0)
1235  *
1236  * @param[in] BaseAddr base address of the given QuadSPI instance
1237  * @param[in] FradInstance index of the FRAD descriptor to be configured
1238  * @param[in] StartAddress 64 KB aligned start address of the flash region
1239  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradStartAddress(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint32 StartAddress)1240 static inline void Qspi_Ip_Sfp_SetFradStartAddress
1241 (
1242     QuadSPI_Type * BaseAddr,
1243     uint8 FradInstance,
1244     uint32 StartAddress)
1245 {
1246     if (FradInstance < QuadSPI_FRAD_COUNT)
1247     {
1248         BaseAddr->FRAD[FradInstance].WORD0 = StartAddress;
1249     }
1250 }
1251 
1252 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1253  * @brief Specifies the specific flash memory region end address (around 64 KB boundary).
1254  *
1255  * Flash Region End Address (FRAD0_WORD1 - FRAD7_WORD1)
1256  *
1257  * @param[in] BaseAddr base address of the given QuadSPI instance
1258  * @param[in] FradInstance index of the FRAD descriptor to be configured
1259  * @param[in] EndAddress 64 KB aligned end address of the flash region
1260  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradEndAddress(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint32 EndAddress)1261 static inline void Qspi_Ip_Sfp_SetFradEndAddress
1262 (
1263     QuadSPI_Type * BaseAddr,
1264     uint8 FradInstance,
1265     uint32 EndAddress)
1266 {
1267     if (FradInstance < QuadSPI_FRAD_COUNT)
1268     {
1269         BaseAddr->FRAD[FradInstance].WORD1 = EndAddress;
1270     }
1271 }
1272 
1273 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1274  * @brief Configure the MD0ACP field in WORD2.
1275  *
1276  * Flash Region Privileges (FRAD0_WORD2 - FRAD7_WORD2):
1277  * - Master Domain Access Control Policy (MD0ACP)
1278  *
1279  * @param[in] BaseAddr base address of the given QuadSPI instance
1280  * @param[in] FradInstance index of the FRAD descriptor to be configured
1281  * @param[in] MdAcp value to be written in MD0ACP
1282  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradMd0Acp(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint8 MdAcp)1283 static inline void Qspi_Ip_Sfp_SetFradMd0Acp
1284 (
1285     QuadSPI_Type * BaseAddr,
1286     uint8 FradInstance,
1287     uint8 MdAcp)
1288 {
1289     if (FradInstance < QuadSPI_FRAD_COUNT)
1290     {
1291         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD2;
1292         RegValue &= ~QuadSPI_WORD2_MD0ACP_MASK;
1293         RegValue |= QuadSPI_WORD2_MD0ACP(MdAcp);
1294         BaseAddr->FRAD[FradInstance].WORD2 = RegValue;
1295     }
1296 }
1297 
1298 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1299  * @brief Configure the MD1ACP field in WORD2.
1300  *
1301  * Flash Region Privileges (FRAD0_WORD2 - FRAD7_WORD2):
1302  * - Master Domain Access Control Policy (MD1ACP)
1303  *
1304  * @param[in] BaseAddr base address of the given QuadSPI instance
1305  * @param[in] FradInstance index of the FRAD descriptor to be configured
1306  * @param[in] MdAcp value to be written in MD0ACP
1307  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradMd1Acp(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint8 MdAcp)1308 static inline void Qspi_Ip_Sfp_SetFradMd1Acp
1309 (
1310     QuadSPI_Type * BaseAddr,
1311     uint8 FradInstance,
1312     uint8 MdAcp)
1313 {
1314     if (FradInstance < QuadSPI_FRAD_COUNT)
1315     {
1316         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD2;
1317         RegValue &= ~QuadSPI_WORD2_MD1ACP_MASK;
1318         RegValue |= QuadSPI_WORD2_MD1ACP(MdAcp);
1319         BaseAddr->FRAD[FradInstance].WORD2 = RegValue;
1320     }
1321 }
1322 
1323 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1324  * @brief Program the VLD bit of a FRAD descriptor.
1325  *
1326  * Flash Region Lock Control (FRAD0_WORD3 - FRAD7_WORD3):
1327  * - Valid (VLD)
1328  *
1329  * @param[in] BaseAddr base address of the given QuadSPI instance
1330  * @param[in] FradInstance index of the FRAD descriptor to be configured
1331  * @param[in] Valid value to be written into VLD bit
1332  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradValid(QuadSPI_Type * BaseAddr,uint8 FradInstance,boolean Valid)1333 static inline void Qspi_Ip_Sfp_SetFradValid
1334 (
1335     QuadSPI_Type * BaseAddr,
1336     uint8 FradInstance,
1337     boolean Valid)
1338 {
1339     if (FradInstance < QuadSPI_FRAD_COUNT)
1340     {
1341         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD3;
1342         RegValue &= ~QuadSPI_WORD3_VLD_MASK;
1343         RegValue |= QuadSPI_WORD3_VLD(Valid ? 1U : 0U);
1344         BaseAddr->FRAD[FradInstance].WORD3 = RegValue;
1345     }
1346 }
1347 
1348 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1349  * @brief Program the LOCK field of a FRAD descriptor.
1350  *
1351  * Flash Region Lock Control (FRAD0_WORD3 - FRAD7_WORD3):
1352  * - Descriptor Lock (LOCK)
1353  *
1354  * @param[in] BaseAddr base address of the given QuadSPI instance
1355  * @param[in] FradInstance index of the FRAD descriptor to be configured
1356  * @param[in] Lock value to be written into LOCK field
1357  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradLock(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint8 Lock)1358 static inline void Qspi_Ip_Sfp_SetFradLock
1359 (
1360     QuadSPI_Type * BaseAddr,
1361     uint8 FradInstance,
1362     uint8 Lock)
1363 {
1364     if (FradInstance < QuadSPI_FRAD_COUNT)
1365     {
1366         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD3;
1367         RegValue &= ~QuadSPI_WORD3_LOCK_MASK;
1368         RegValue |= QuadSPI_WORD3_LOCK(Lock);
1369         BaseAddr->FRAD[FradInstance].WORD3 = RegValue;
1370     }
1371 }
1372 
1373 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1374  * @brief Program the EALO field of a FRAD descriptor.
1375  *
1376  * Flash Region Privileges (FRAD0_WORD2 - FRAD7_WORD2):
1377  * - Exclusive Access Lock Owner (EALO)
1378  *
1379  * @param[in] BaseAddr base address of the given QuadSPI instance
1380  * @param[in] FradInstance index of the FRAD descriptor to be configured
1381  * @param[in] EaOwner value to be written into EALO field
1382  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradEaOwner(QuadSPI_Type * BaseAddr,uint8 FradInstance,uint8 EaOwner)1383 static inline void Qspi_Ip_Sfp_SetFradEaOwner
1384 (
1385     QuadSPI_Type * BaseAddr,
1386     uint8 FradInstance,
1387     uint8 EaOwner)
1388 {
1389     if (FradInstance < QuadSPI_FRAD_COUNT)
1390     {
1391         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD2;
1392         RegValue &= ~QuadSPI_WORD2_EALO_MASK;
1393         RegValue |= QuadSPI_WORD2_EALO(EaOwner);
1394         BaseAddr->FRAD[FradInstance].WORD2 = RegValue;
1395     }
1396 }
1397 
1398 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1399  * @brief Program the EAL field of a FRAD descriptor.
1400  *
1401  * Flash Region Lock Control (FRAD0_WORD3 - FRAD7_WORD3):
1402  * - Exclusive Access Lock (EAL)
1403  *
1404  * @param[in] BaseAddr base address of the given QuadSPI instance
1405  * @param[in] FradInstance index of the FRAD descriptor to be configured
1406  * @param[in] EaLock value to be written into EAL field
1407  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetFradEaLock(QuadSPI_Type * BaseAddr,uint8 FradInstance,Qspi_Ip_SfpEalType EaLock)1408 static inline void Qspi_Ip_Sfp_SetFradEaLock
1409 (
1410     QuadSPI_Type * BaseAddr,
1411     uint8 FradInstance,
1412     Qspi_Ip_SfpEalType EaLock)
1413 {
1414     if (FradInstance < QuadSPI_FRAD_COUNT)
1415     {
1416         uint32 RegValue = BaseAddr->FRAD[FradInstance].WORD3;
1417         RegValue &= ~QuadSPI_WORD3_EAL_MASK;
1418         RegValue |= QuadSPI_WORD3_EAL(EaLock);
1419         BaseAddr->FRAD[FradInstance].WORD3 = RegValue;
1420     }
1421 }
1422 
1423 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1424  * @brief This field provides exclusive write lock over a FRAD region based on MDnACP.
1425  *
1426  * Flash Region Lock Control (FRAD0_WORD3 - FRAD7_WORD3):
1427  * - Exclusive Access Lock (EAL)
1428  *
1429  * @param[in] BaseAddr base address of the given QuadSPI instance
1430  * @param[in] FradInstance index of the FRAD descriptor to be configured
1431  *
1432  * @return the value read from the EAL field
1433  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_FradEaLock(QuadSPI_Type const * BaseAddr,uint8 FradInstance)1434 static inline uint8 Qspi_Ip_Sfp_FradEaLock
1435 (
1436     QuadSPI_Type const * BaseAddr,
1437     uint8 FradInstance)
1438 {
1439     uint32 RegValue = 0U;
1440     if (FradInstance < QuadSPI_FRAD_COUNT)
1441     {
1442         RegValue = (BaseAddr->FRAD[FradInstance].WORD3 & QuadSPI_WORD3_LOCK_MASK) >> QuadSPI_WORD3_LOCK_SHIFT;
1443     }
1444     return (uint8)RegValue;
1445 }
1446 
1447 #endif /* QSPI_IP_SFP_ENABLE_FRAD */
1448 
1449 /** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
1450  * @brief Configure the timeout to abort the ongoing write or read command.
1451  *
1452  * Master Timeout (MTO):
1453  * - Write Timeout (WRITE_TO)
1454  *
1455  * @param[in] BaseAddr base address of the given QuadSPI instance
1456  * @param[in] Timeout timeout value to be programmed into the register
1457  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Qspi_Ip_Sfp_SetMasterTimeout(QuadSPI_Type * BaseAddr,uint32 Timeout)1458 static inline void Qspi_Ip_Sfp_SetMasterTimeout
1459 (
1460     QuadSPI_Type * BaseAddr,
1461     uint32 Timeout)
1462 {
1463     BaseAddr->MTO = Timeout;
1464 }
1465 
1466 #endif /* QSPI_IP_SFP_ENABLE_GLOBAL */
1467 
1468 #endif /* FEATURE_QSPI_HAS_SFP */
1469 
1470 
1471 #endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
1472 
1473 #ifdef __cplusplus
1474 }
1475 #endif
1476 
1477 /** @} */
1478 
1479 #endif /* QUADSPI_HW_ACCESS_H */
1480