1 /*
2  * Copyright 2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SIUL2_PORT_IP_DEFINES
8 #define SIUL2_PORT_IP_DEFINES
9 
10 /**
11 *   @file    Siul2_Port_Ip_Defines.h
12 *
13 *   @addtogroup Port_CFG
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 /*==================================================================================================
22 *                                        INCLUDE FILES
23 * 1) system and project includes
24 * 2) needed interfaces from external units
25 * 3) internal and external interfaces from this unit
26 ==================================================================================================*/
27 #include "S32K344_SIUL2.h"
28 #include "S32K344_DCM_GPR.h"
29 /*==================================================================================================
30 *                              SOURCE FILE VERSION INFORMATION
31 ==================================================================================================*/
32 #define SIUL2_PORT_IP_DEFINES_VENDOR_ID_H                       43
33 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MAJOR_VERSION_H        4
34 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MINOR_VERSION_H        7
35 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_REVISION_VERSION_H     0
36 #define SIUL2_PORT_IP_DEFINES_SW_MAJOR_VERSION_H                3
37 #define SIUL2_PORT_IP_DEFINES_SW_MINOR_VERSION_H                0
38 #define SIUL2_PORT_IP_DEFINES_SW_PATCH_VERSION_H                0
39 
40 /*==================================================================================================
41 *                                     FILE VERSION CHECKS
42 ==================================================================================================*/
43 
44 /*==================================================================================================
45 *                                          CONSTANTS
46 ==================================================================================================*/
47 
48 /*==================================================================================================
49 *                                      DEFINES AND MACROS
50 ==================================================================================================*/
51 /**
52 * @brief Number of SIUL2 instances present on the subderivative
53 */
54 #define SIUL2_NUM_SIUL2_INSTANCES_U8 (1)
55 
56 /* S32K3XX */
57 #define SIUL2_PORT_IP_HAS_ONEBIT_SLEWRATE           (STD_ON)
58 #define SIUL2_PORT_IP_HAS_ADC_INTERLEAVE            (STD_ON)
59 #define SIUL2_PORT_IP_HAS_NO_RECEIVER_SELECT        (STD_ON)
60 
61 /*! @brief SIUL2 module has DSE bit */
62 #define FEATURE_SIUL2_PORT_IP_HAS_DRIVE_STRENGTH    (STD_ON)
63 
64 /*! @brief SIUL2 module has IFE bit */
65 #define FEATURE_SIUL2_PORT_IP_HAS_INPUT_FILTER      (STD_ON)
66 
67 /*! @brief SIUL2 module has PKE bit */
68 #define FEATURE_SIUL2_PORT_IP_HAS_PULL_KEEPER       (STD_ON)
69 
70 /*! @brief SIUL2 module has INV bit */
71 #define FEATURE_SIUL2_PORT_IP_HAS_INVERT_DATA       (STD_ON)
72 
73 #define FEATURE_SIUL2_PORT_IP_HAS_TOUCH_SENSING         (STD_ON)
74 /**
75 * @brief Macros defined for the SIUL2 IPV that are protected.
76 */
77 #define MCAL_SIUL2_REG_PROT_AVAILABLE   (STD_ON)
78 
79 /**
80 * @brief Macros defined for the protection size
81 */
82 #define SIUL2_PROT_MEM_U32    ((uint32)0x00000008UL)
83 
84 /**
85 * @brief Support for User mode.
86 * If this parameter has been configured to STD_ON, the PORT driver code can be executed from both supervisor and user mode.
87 */
88 #define PORT_ENABLE_USER_MODE_SUPPORT   (STD_OFF)
89 
90 #ifndef MCAL_ENABLE_USER_MODE_SUPPORT
91     #ifdef PORT_ENABLE_USER_MODE_SUPPORT
92         #if (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT)
93             #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Port in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
94         #endif /* (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT) */
95     #endif /* ifdef PORT_ENABLE_USER_MODE_SUPPORT*/
96 #endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */
97 
98 /* Pre-processor switch to enable/disable development error detection for Siul2 Ip API */
99 #define SIUL2_PORT_IP_DEV_ERROR_DETECT                         (STD_OFF)
100 
101 #define PORT_SIUL2_0_IMCRS_IDX_END_U16     ((uint16)378)
102 
103 /* Pre-processor switch to enable/disable VirtWrapper support */
104 #define PORT_VIRTWRAPPER_SUPPORT                      (STD_OFF)
105 
106 
107 #define SIUL2_MSCR_BASE                (IP_SIUL2->MSCR)
108 
109 /** SIUL2 */
110 /** Peripheral PORTA_L_HALF base pointer */
111 #define PORTA_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x00))
112 /** Peripheral PORTA_H_HALF base pointer */
113 #define PORTA_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x10))
114 /** Peripheral PORTB_L_HALF base pointer */
115 #define PORTB_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x20))
116 /** Peripheral PORTB_H_HALF base pointer */
117 #define PORTB_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x30))
118 /** Peripheral PORTC_L_HALF base pointer */
119 #define PORTC_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x40))
120 /** Peripheral PORTC_H_HALF base pointer */
121 #define PORTC_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x50))
122 /** Peripheral PORTD_L_HALF base pointer */
123 #define PORTD_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x60))
124 /** Peripheral PORTD_H_HALF base pointer */
125 #define PORTD_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x70))
126 /** Peripheral PORTE_L_HALF base pointer */
127 #define PORTE_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x80))
128 /** Peripheral PORTE_H_HALF base pointer */
129 #define PORTE_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0x90))
130 /** Peripheral PORTF_L_HALF base pointer */
131 #define PORTF_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xA0))
132 /** Peripheral PORTF_H_HALF base pointer */
133 #define PORTF_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xB0))
134 /** Peripheral PORTG_L_HALF base pointer */
135 #define PORTG_L_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xC0))
136 /** Peripheral PORTG_H_HALF base pointer */
137 #define PORTG_H_HALF                            ((Siul2_Port_Ip_PortType *)(SIUL2_MSCR_BASE + 0xD0))
138 
139 /*==================================================================================================
140 *                                             ENUMS
141 ==================================================================================================*/
142 
143 /*==================================================================================================
144 *                                STRUCTURES AND OTHER TYPEDEFS
145 ==================================================================================================*/
146 
147 
148 /*==================================================================================================
149 *                                GLOBAL VARIABLE DECLARATIONS
150 ==================================================================================================*/
151 
152 /*==================================================================================================
153 *                                    FUNCTION PROTOTYPES
154 ==================================================================================================*/
155 
156 
157 #ifdef __cplusplus
158 }
159 #endif
160 
161 /** @} */
162 
163 #endif /* SIUL2_PORT_IP_DEFINES */
164