1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_PLLDIG.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_PLLDIG 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_PLLDIG_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_PLLDIG_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PLLDIG Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PLLDIG_Peripheral_Access_Layer PLLDIG Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PLLDIG - Size of Registers Arrays */ 72 #define PLLDIG_PLLODIV_COUNT 7u 73 74 /** PLLDIG - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t PLLCR; /**< PLL Control, offset: 0x0 */ 77 __IO uint32_t PLLSR; /**< PLL Status, offset: 0x4 */ 78 __IO uint32_t PLLDV; /**< PLL Divider, offset: 0x8 */ 79 __IO uint32_t PLLFM; /**< PLL Frequency Modulation, offset: 0xC */ 80 __IO uint32_t PLLFD; /**< PLL Fractional Divider, offset: 0x10 */ 81 uint8_t RESERVED_0[12]; 82 __IO uint32_t PLLCLKMUX; /**< PLL Clock Multiplexer, offset: 0x20 */ 83 uint8_t RESERVED_1[92]; 84 __IO uint32_t PLLODIV[PLLDIG_PLLODIV_COUNT]; /**< PLL Output Divider, array offset: 0x80, array step: 0x4 */ 85 } PLLDIG_Type, *PLLDIG_MemMapPtr; 86 87 /** Number of instances of the PLLDIG module. */ 88 #define PLLDIG_INSTANCE_COUNT (3u) 89 90 /* PLLDIG - Peripheral instance base addresses */ 91 /** Peripheral CORE_PLL base address */ 92 #define IP_CORE_PLL_BASE (0x40210000u) 93 /** Peripheral CORE_PLL base pointer */ 94 #define IP_CORE_PLL ((PLLDIG_Type *)IP_CORE_PLL_BASE) 95 /** Peripheral DDR_PLL base address */ 96 #define IP_DDR_PLL_BASE (0x440A0000u) 97 /** Peripheral DDR_PLL base pointer */ 98 #define IP_DDR_PLL ((PLLDIG_Type *)IP_DDR_PLL_BASE) 99 /** Peripheral PERIPH_PLL base address */ 100 #define IP_PERIPH_PLL_BASE (0x40220000u) 101 /** Peripheral PERIPH_PLL base pointer */ 102 #define IP_PERIPH_PLL ((PLLDIG_Type *)IP_PERIPH_PLL_BASE) 103 /** Array initializer of PLLDIG peripheral base addresses */ 104 #define IP_PLLDIG_BASE_ADDRS { IP_CORE_PLL_BASE, IP_DDR_PLL_BASE, IP_PERIPH_PLL_BASE } 105 /** Array initializer of PLLDIG peripheral base pointers */ 106 #define IP_PLLDIG_BASE_PTRS { IP_CORE_PLL, IP_DDR_PLL, IP_PERIPH_PLL } 107 108 /* ---------------------------------------------------------------------------- 109 -- PLLDIG Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup PLLDIG_Register_Masks PLLDIG Register Masks 114 * @{ 115 */ 116 117 /*! @name PLLCR - PLL Control */ 118 /*! @{ */ 119 120 #define PLLDIG_PLLCR_PLLPD_MASK (0x80000000U) 121 #define PLLDIG_PLLCR_PLLPD_SHIFT (31U) 122 #define PLLDIG_PLLCR_PLLPD_WIDTH (1U) 123 #define PLLDIG_PLLCR_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLCR_PLLPD_SHIFT)) & PLLDIG_PLLCR_PLLPD_MASK) 124 /*! @} */ 125 126 /*! @name PLLSR - PLL Status */ 127 /*! @{ */ 128 129 #define PLLDIG_PLLSR_LOCK_MASK (0x4U) 130 #define PLLDIG_PLLSR_LOCK_SHIFT (2U) 131 #define PLLDIG_PLLSR_LOCK_WIDTH (1U) 132 #define PLLDIG_PLLSR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLSR_LOCK_SHIFT)) & PLLDIG_PLLSR_LOCK_MASK) 133 134 #define PLLDIG_PLLSR_LOL_MASK (0x8U) 135 #define PLLDIG_PLLSR_LOL_SHIFT (3U) 136 #define PLLDIG_PLLSR_LOL_WIDTH (1U) 137 #define PLLDIG_PLLSR_LOL(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLSR_LOL_SHIFT)) & PLLDIG_PLLSR_LOL_MASK) 138 /*! @} */ 139 140 /*! @name PLLDV - PLL Divider */ 141 /*! @{ */ 142 143 #define PLLDIG_PLLDV_MFI_MASK (0xFFU) 144 #define PLLDIG_PLLDV_MFI_SHIFT (0U) 145 #define PLLDIG_PLLDV_MFI_WIDTH (8U) 146 #define PLLDIG_PLLDV_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLDV_MFI_SHIFT)) & PLLDIG_PLLDV_MFI_MASK) 147 148 #define PLLDIG_PLLDV_RDIV_MASK (0x7000U) 149 #define PLLDIG_PLLDV_RDIV_SHIFT (12U) 150 #define PLLDIG_PLLDV_RDIV_WIDTH (3U) 151 #define PLLDIG_PLLDV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLDV_RDIV_SHIFT)) & PLLDIG_PLLDV_RDIV_MASK) 152 /*! @} */ 153 154 /*! @name PLLFM - PLL Frequency Modulation */ 155 /*! @{ */ 156 157 #define PLLDIG_PLLFM_STEPNO_MASK (0x7FFU) 158 #define PLLDIG_PLLFM_STEPNO_SHIFT (0U) 159 #define PLLDIG_PLLFM_STEPNO_WIDTH (11U) 160 #define PLLDIG_PLLFM_STEPNO(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFM_STEPNO_SHIFT)) & PLLDIG_PLLFM_STEPNO_MASK) 161 162 #define PLLDIG_PLLFM_STEPSIZE_MASK (0x3FF0000U) 163 #define PLLDIG_PLLFM_STEPSIZE_SHIFT (16U) 164 #define PLLDIG_PLLFM_STEPSIZE_WIDTH (10U) 165 #define PLLDIG_PLLFM_STEPSIZE(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFM_STEPSIZE_SHIFT)) & PLLDIG_PLLFM_STEPSIZE_MASK) 166 167 #define PLLDIG_PLLFM_SPREADCTL_MASK (0x20000000U) 168 #define PLLDIG_PLLFM_SPREADCTL_SHIFT (29U) 169 #define PLLDIG_PLLFM_SPREADCTL_WIDTH (1U) 170 #define PLLDIG_PLLFM_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFM_SPREADCTL_SHIFT)) & PLLDIG_PLLFM_SPREADCTL_MASK) 171 172 #define PLLDIG_PLLFM_SSCGBYP_MASK (0x40000000U) 173 #define PLLDIG_PLLFM_SSCGBYP_SHIFT (30U) 174 #define PLLDIG_PLLFM_SSCGBYP_WIDTH (1U) 175 #define PLLDIG_PLLFM_SSCGBYP(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFM_SSCGBYP_SHIFT)) & PLLDIG_PLLFM_SSCGBYP_MASK) 176 /*! @} */ 177 178 /*! @name PLLFD - PLL Fractional Divider */ 179 /*! @{ */ 180 181 #define PLLDIG_PLLFD_MFN_MASK (0x7FFFU) 182 #define PLLDIG_PLLFD_MFN_SHIFT (0U) 183 #define PLLDIG_PLLFD_MFN_WIDTH (15U) 184 #define PLLDIG_PLLFD_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFD_MFN_SHIFT)) & PLLDIG_PLLFD_MFN_MASK) 185 186 #define PLLDIG_PLLFD_SDMEN_MASK (0x40000000U) 187 #define PLLDIG_PLLFD_SDMEN_SHIFT (30U) 188 #define PLLDIG_PLLFD_SDMEN_WIDTH (1U) 189 #define PLLDIG_PLLFD_SDMEN(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLFD_SDMEN_SHIFT)) & PLLDIG_PLLFD_SDMEN_MASK) 190 /*! @} */ 191 192 /*! @name PLLCLKMUX - PLL Clock Multiplexer */ 193 /*! @{ */ 194 195 #define PLLDIG_PLLCLKMUX_REFCLKSEL_MASK (0x1U) 196 #define PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT (0U) 197 #define PLLDIG_PLLCLKMUX_REFCLKSEL_WIDTH (1U) 198 #define PLLDIG_PLLCLKMUX_REFCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT)) & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) 199 /*! @} */ 200 201 /*! @name PLLODIV - PLL Output Divider */ 202 /*! @{ */ 203 204 #define PLLDIG_PLLODIV_DIV_MASK (0xFF0000U) 205 #define PLLDIG_PLLODIV_DIV_SHIFT (16U) 206 #define PLLDIG_PLLODIV_DIV_WIDTH (8U) 207 #define PLLDIG_PLLODIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLODIV_DIV_SHIFT)) & PLLDIG_PLLODIV_DIV_MASK) 208 209 #define PLLDIG_PLLODIV_DE_MASK (0x80000000U) 210 #define PLLDIG_PLLODIV_DE_SHIFT (31U) 211 #define PLLDIG_PLLODIV_DE_WIDTH (1U) 212 #define PLLDIG_PLLODIV_DE(x) (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLODIV_DE_SHIFT)) & PLLDIG_PLLODIV_DE_MASK) 213 /*! @} */ 214 215 /*! 216 * @} 217 */ /* end of group PLLDIG_Register_Masks */ 218 219 /*! 220 * @} 221 */ /* end of group PLLDIG_Peripheral_Access_Layer */ 222 223 #endif /* #if !defined(S32Z2_PLLDIG_H_) */ 224
