1 /* This device file has been adapted from ARM CMSIS-Core sources*/ 2 /* by NXP Semiconductors (2018)*/ 3 /* Copyright(C) NXP B.V. 2018*/ 4 /* All rights are reserved. Reproduction in whole or in part is prohibited*/ 5 /* without the prior written consent of the copy-right owner.*/ 6 /* This source code and any compilation or derivative thereof is the sole*/ 7 /* property of NXP B.V. and is provided pursuant to a Software License*/ 8 /* Agreement. This code is the proprietary information of NXP B.V. and*/ 9 /* is confidential in nature. Its use and dissemination by any party other*/ 10 /* than NXP B.V. is strictly limited by the confidential information*/ 11 /* provisions of the agreement referenced above.*/ 12 /* NXP makes no warranty, expressed, implied or statutory, including but*/ 13 /* not limited to any implied warranty of merchantability or fitness for any*/ 14 /* particular purpose, or that the use will not infringe any third party patent,*/ 15 /* copyright or trademark.*/ 16 /* NXP must not be liable for any loss or damage arising from its use.*/ 17 /******************************************************************************************************** 18 * @file CoSimPKC.h 19 * 20 * @brief CMSIS Peripheral Access Layer Header File for CoSimPKC. 21 * 22 * @version $Revision: 25425 $ 23 * @date 26. November 2019 24 * 25 * @note Generated with csv2a_create_cmsis_cheader V1.41 26 *******************************************************************************************************/ 27 /* Copyright (c) 2012 ARM LIMITED 28 29 All rights reserved. 30 Redistribution and use in source and binary forms, with or without 31 modification, are permitted provided that the following conditions are met: 32 - Redistributions of source code must retain the above copyright 33 notice, this list of conditions and the following disclaimer. 34 - Redistributions in binary form must reproduce the above copyright 35 notice, this list of conditions and the following disclaimer in the 36 documentation and/or other materials provided with the distribution. 37 - Neither the name of ARM nor the names of its contributors may be used 38 to endorse or promote products derived from this software without 39 specific prior written permission. 40 * 41 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 42 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 45 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 46 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 47 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 48 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 49 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 50 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 51 POSSIBILITY OF SUCH DAMAGE. 52 ---------------------------------------------------------------------------*/ 53 54 55 56 /** @addtogroup (null) 57 * @{ 58 */ 59 60 /** @addtogroup CoSimPKC 61 * @{ 62 */ 63 64 #ifndef CoSimPKC_H 65 #define CoSimPKC_H 66 67 #ifdef __cplusplus 68 extern "C" { 69 #endif 70 71 72 #ifndef __IM /*!< Fallback for older CMSIS versions */ 73 #define __IM __I 74 #endif 75 #ifndef __OM /*!< Fallback for older CMSIS versions */ 76 #define __OM __O 77 #endif 78 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 79 #define __IOM __IO 80 #endif 81 82 83 /* ================================================================================ */ 84 /* ================ Device Specific Peripheral Section ================ */ 85 /* ================================================================================ */ 86 87 88 /** @addtogroup Device_Peripheral_Registers 89 * @{ 90 */ 91 92 93 /* =================== Start of section using anonymous unions ================== */ 94 #if defined(__CC_ARM) 95 #pragma push 96 #pragma anon_unions 97 #elif defined (__ICCARM__) 98 #pragma language=extended 99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 100 #pragma clang diagnostic push 101 #pragma clang diagnostic ignored "-Wc11-extensions" 102 #pragma clang diagnostic ignored "-Wreserved-id-macro" 103 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 104 #pragma clang diagnostic ignored "-Wnested-anon-types" 105 #elif defined(__GNUC__) 106 /* anonymous unions are enabled by default */ 107 #elif defined(__TMS470__) 108 /* anonymous unions are enabled by default */ 109 #elif defined(__TASKING__) 110 #pragma warning 586 111 #elif defined(__CSMC__) 112 /* anonymous unions are enabled by default */ 113 #else 114 #warning Not supported compiler type 115 #endif 116 117 118 119 /* ================================================================================ */ 120 /* ================ PKC ================ */ 121 /* ================================================================================ */ 122 123 124 /** 125 * @brief SFRs of block PKC (PKC) 126 */ 127 128 typedef struct { /*!< PKC Structure */ 129 130 union { 131 __IM uint32_t STATUS; /*!< Status register */ 132 133 struct { 134 __IM uint32_t ACTIV : 1; /*!< PKC active: ACTIV=1 signals that a calculation is in progress or 135 about to start. At the end of a calculation ACTIV is 136 automatically reset to logic 0 in case no further GO bit is set. 137 If the next PKC operation has been started by setting a GO bit 138 during a calculation, ACTIV remains high. ACTIV is always '1' in 139 case PKC_STATUS.GOANY is set. ACTIV is always '0' in case 140 PKC_CTRL_RESET is set.; While ACTIV is '1' the PKC is active also 141 in using the PKC RAM. Concurrent accesses to PKC RAM via the CPU 142 is still possible, but may reduce the performance of the PKC 143 calculation. Write accesses to the operand and result area 144 defined by the PKC pointer and length registers is prohibited 145 during a running calculation and may result in wrong calcuation 146 results. */ 147 __IM uint32_t CARRY : 1; /*!< Carry overflow flag: CARRY is set by the PKC at the end of a 148 calculation in case; - an addition or multiplication with 149 addition operation has been executed and an overflow in the most 150 significant bit has occured.; - a subtraction or multiplication 151 with subtraction operation has been executed with negative result 152 in twos complement notation.; - a shift or rotate operation has 153 been executed (most/least significant shifted/rotated bit is 154 stored in CARRY flag).; - a LSB0s or MSB0s operation has been 155 executed (CARRY indicates zero least/most-significant zero 156 bits).; - a compare operation habe been executed with Z>Y.; 157 CARRY is updated for each PKC calculation mode, except for MUL1 158 (opcode 0x20) and MUL1_GF2 (opcode 0x24). This holds also for 159 operation modes where CARRY is always zero, e.g. logical 160 operations (AND, OR, ...).; If PKC is in reset 161 (PKC_CTRL.RESET=1), CARRY is set to logic 0 (default). */ 162 __IM uint32_t ZERO : 1; /*!< Zero result flag: ZERO is set by the PKC at the end of a 163 calculation in case the result of the calculation is equal zero. 164 ZERO is updated for each PKC calculation mode, except for MUL1 165 (opcode 0x20) and MUL1_GF2 (opcode 0x24).; NOTE: A set ZERO flag 166 only indicates that the result written to PKC RAM is zero, but 167 does not imply that there is no overflow (i.e., CARRY flag set).; 168 If PKC is in reset (PKC_CTRL.RESET=1), ZERO is set to logic 0 169 (default). */ 170 __IM uint32_t GOANY : 1; /*!< Combined GO status flag: GOANY is set in case either 171 PKC_CTRL.GOD1, GOD2, GOM1, GOM2 or GOU is set. The 1-to-0 172 transition of GOANY indicates that a calculation has been started 173 and that a new GO bit can be set. If GOANY is cleared also all 174 PKC_STATUS.LOCKED bits are cleared to indicate that the parameter 175 set can be updated. GOANY is always '0' in case PKC_CTRL.RESET is 176 set. */ 177 uint32_t : 1; /*!< reserved */ 178 __IM uint32_t LOCKED : 2; /*!< Parameter set locked: Indicates if parameter set is locked due to 179 a pending calculation start or can be overwritten.; x1b- 180 parameter set 1 is locked; 1xb- parameter set 2 is locked; 181 LOCKED[0] is set in case a PKC calculation is started with 182 parameter set 1 via PKC_CTRL.GOD1 or PKC_CTRL.GOM1.; In case one 183 of the parameter set 1 SFRs PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, 184 PKC_LEN1 is updated while LOCKED[0] is set a PKC security alarm 185 will be triggered (PKC_ACCESS_ERR.CTRL is set).; LOCKED[1] is set 186 in case a PKC calculation is started with parameter set 2 via 187 PKC_CTRL.GOD2 or PKC_CTRL.GOM2.; In case one of the parameter set 188 2 SFRs PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2 is updated 189 while LOCKED[1] is set a PKC security alarm will be triggered 190 (PKC_ACCESS_ERR.CTRL is set).; LOCKED[1:0] is not set for a 191 universal pointer fetch (layer2) PKC calculation started via 192 PKC_CTRL.GOU. All parameter set SFRs can be updated during a 193 universal pointer fetch operation, except PKC_LEN1 and PKC_LEN2. 194 Updating PKC_LEN1 or PKC_LEN2 during a layer2 calculation 195 indicated by PKC_STATUS.GOANY will trigger a PKC security alarm 196 (PKC_ACCESS_ERR.CTRL is set).; LOCKED[1:0] is cleared with the 197 start of the calculation in parallel with the 1-to-0 transition 198 of PKC_STATUS.GOANY and in case PKC_CTRL.RESET is set. */ 199 uint32_t : 25; /*!< reserved */ 200 } STATUS_b; /*!< BitSize */ 201 }; 202 203 union { 204 __IOM uint32_t CTRL; /*!< Control register */ 205 206 struct { 207 __IOM uint32_t RESET : 1; /*!< PKC reset control bit: RESET=1 enforces the PKC's reset state 208 during which a calculation cannot be started and by which any 209 ongoing calculation process is stopped. RESET can be set/cleared 210 by the CPU in order to switch between PKC reset and calculation 211 enable. RESET=1 is the default state after a chip reset.; RESET=1 212 disables PKC activity and accordingly also provides its 213 power-saving state. When PKC reset is released (RESET=0) and idle 214 operation is activiated (PKC_CFG.IDLEOP=1) the power consumption 215 is increased even before a calculation is started by setting a GO 216 bit.; When RESET is set to '1' the read-only status flags 217 PKC_STATUS.CARRY and PKC_STATUS.ZERO are cleared. If required 218 these flags have to be evaluated before RESET is set. The status 219 bits PKC_STATUS.GOANY and PKC_STATUS.LOCKED are reset as well in 220 case RESET is set. RESET does not have an impact on the content 221 of any other PKC SFRs. The parameter set and universal pointer 222 SFRs can be read and written also while RESET is set.; Software 223 must clear bit RESET to enable the PKC before it can start a 224 calculation via one of the GO bits in PKC_CTRL. Any attempt to 225 start a calculation via a GO bit while RESET=1 will trigger a PKC 226 security alarm (PKC_ACCESS_ERR.CTRL is set).; The PKC 227 configuration setting in PKC_CFG can only be updated while 228 RESET=1. A write access to PKC_CFG while RESET=0 will trigger a 229 PKC security alarm (PKC_ACCESS_ERR.CTRL is set). */ 230 __IOM uint32_t STOP : 1; /*!< Freeze PKC calculation: STOP=1 freezes all PKC activity incl. RAM 231 accesses and reduces the PKC power consumption to its minimum. 232 The difference compared to the reset of the PKC is that a stopped 233 calculation can be continued when STOP is released (reset to '0') 234 again. The status flags are not affected by the STOP control bit. */ 235 __IOM uint32_t GOD1 : 1; /*!< Control bit to start direct operation using parameter set 1: If 236 GOD1 is set PKC will start a direct / layer0 operation using 237 parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1).; 238 Section 'Operating the PKC via the Parameter Set interface (layer 239 0)' describes how to start layer0 operations.; GOD1 is a 240 write-only bit and always read '0'. It is only allowed to set 241 GOD1 when PKC_STATUS.GOANY and PKC_CTRL.RESET are cleared. 242 Otherwise a security alarm is triggered (PKC_ACCESS_ERR.CTRL is 243 set). An alarm is also triggered in case more than one GO bit is 244 set for the PKC_CTRL SFR write access (PKC_ACCESS_ERR.CTRL is 245 set). */ 246 __IOM uint32_t GOD2 : 1; /*!< Control bit to start direct operation using parameter set 2: If 247 GOD2 is set PKC will start a direct / layer0 operation using 248 parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2).; 249 Section 'Operating the PKC via the Parameter Set interface (layer 250 0)' describes how to start layer0 operations.; GOD2 is a 251 write-only bit and always read '0'. It is only allowed to set 252 GOD2 when PKC_STATUS.GOANY and PKC_CTRL.RESET are cleared. 253 Otherwise a security alarm is triggered(PKC_ACCESS_ERR.CTRL is 254 set). An alarm is also triggered in case more than one GO bit is 255 set for the PKC_CTRL SFR write access (PKC_ACCESS_ERR.CTRL is 256 set). */ 257 __IOM uint32_t GOM1 : 1; /*!< Control bit to start MC pattern using parameter set 1: If GOM1 is 258 set PKC will start a MC pattern / layer1 operation using 259 parameter set 1 (PKC_MODE1, PKC_XYPTR1, PKC_ZRPTR1, PKC_LEN1).; 260 Section 'Operating the PKC via the Micro Code interface (layer 261 1)' describes how to start layer1 operations.; GOM1 is a 262 write-only bit and always read '0'. It is only allowed to set 263 GOM1 when PKC_STATUS.GOANY and PKC_CTRL.RESET are cleared. 264 Otherwise a security alarm is triggered (PKC_ACCESS_ERR.CTRL is 265 set). An alarm is also triggered in case more than one GO bit is 266 set for the PKC_CTRL SFR write access (PKC_ACCESS_ERR.CTRL is 267 set). */ 268 __IOM uint32_t GOM2 : 1; /*!< Control bit to start MC pattern using parameter set 2: If GOM2 is 269 set PKC will start a MC pattern / layer1 operation using 270 parameter set 2 (PKC_MODE2, PKC_XYPTR2, PKC_ZRPTR2, PKC_LEN2).; 271 Section 'Operating the PKC via the Micro Code interface (layer 272 1)' describes how to start layer1 operations.; GOM2 is a 273 write-only bit and always read '0'. It is only allowed to set 274 GOM2 when PKC_STATUS.GOANY and PKC_CTRL.RESET are cleared. 275 Otherwise a security alarm is triggered (PKC_ACCESS_ERR.CTRL is 276 set). An alarm is also triggered in case more than one GO bit is 277 set for the PKC_CTRL SFR write access (PKC_ACCESS_ERR.CTRL is 278 set). */ 279 __IOM uint32_t GOU : 1; /*!< Control bit to start pipe operation: If GOU is set PKC will start 280 the pipe / layer2 operation (parameter fetch & calculation) 281 described in section 'PKC Universal Pointer Fetch Operation'.; 282 Section 'Operating the PKC via the Universal Pointer Fetch Unit 283 (layer 2)' describes how to start layer2 operations.; GOU is a 284 write-only bit and always read '0'. It is only allowed to set GOU 285 when PKC_STATUS.GOANY and PKC_CTRL.RESET are cleared, 286 PKC_ULEN>0 and PKC_UPTR(T) point to valid addresses (defined 287 by MMU). Otherwise a security alarm is triggered 288 (PKC_ACCESS_ERR.CTRL or PKC_ACCESS_ERR.AHB is set). An alarm is 289 also triggered in case more than one GO bit is set for the 290 PKC_CTRL SFR write access (PKC_ACCESS_ERR.CTRL is set). */ 291 __IOM uint32_t GF2CONV : 1; /*!< Convert to GF2 calculation modes: If GF2CONV is set operations 292 are mapped to their GF(2) equivalent operation modes.; GF2CONV 293 influences all PKC operation modes layer0/1/2.; GF2CONV can be 294 updated at any point in time, even during a running calculation. 295 However the change is only applied when a new calculation is 296 started via PKC_CTRL.GO*. */ 297 __IOM uint32_t CLRCACHE : 1; /*!< Clear universal pointer cache: Invalidates the cache such that 298 all previously fetched parameters are withdrawn and have to be 299 fetched again via DMA accesses.; CLRCACHE can be triggered at any 300 point in time, even during a running universal pointer fetch 301 calculation. CLRCACHE is write-only and always read '0'. CLRCACHE 302 has no impact in case the cache is disabled via 303 PKC_CTRL.CACHE_EN=0 or in case no layer2 calculations are 304 executed.; Beside CLRCACHE the cache is also invalidated when it 305 is disabled (PKC_CTRL.CACHE_EN=0) or in case of any write access 306 to PKC_UPTRT. */ 307 __IOM uint32_t CACHE_EN : 1; /*!< Enable universal pointer cache: If CACHE_EN=1 the cache for the 308 universal pointer parameters is enabled. In case a parameter 309 value is found in the cache (from a previous fetch) no DMA access 310 is triggered. As such the amount of DMA accesses for the 311 parameter fetch vary between 0 and 4. To further optimize the 312 cache utilization not used parameters, e.g. XPTR for a plain 313 addition (opcode 0x0A), could be defined equal to a used one 314 (e.g. equal YPTR or RPTR) or a previously fetched parameter.; The 315 univeral pointer cache can store up to 6 16-bit parameter values. 316 In case the cache is full the entry that has not been used 317 longest is overwritten by the newly fetched parameter.; The cache 318 can be enabled and disabled at any point in time, even during a 319 running universal pointer fetch calculation. */ 320 __IOM uint32_t REDMUL : 2; /*!< Reduced multiplier mode: REDMUL defines the operand width 321 processed by the PKC coprocessor. The operand width can be 322 reduced to; - perform calculations on short operands, e.g. 323 32-bit.; - reduce power consumption and power peaks.; - add 324 additional noise in combination with PKC_CFG.REDMULNOISE = 1.; 325 PKC calculation performance is reduced when operating in reduced 326 multiplier mode because the operand length in PKC-words (64/32 327 bit) is increased.; For hard coded layer1 calculation modular 328 multiplication and modular reduction the pre-computed inverse of 329 the modul depends on the PKC-word size setting and as such is not 330 the same for different REDMUL configurations.; The operand 331 pointers and length definitions are independant from the REDMUL 332 setting as long as they are 64-bit aligned. The amount of ignored 333 least significiant bits of the pointer and length SFRs depends on 334 REDMUL. As a consequence also the minimum supported operand 335 length defined via PKC_LEN[1,2].LEN and PKC_LEN[1,2].MCLEN are 336 affected by REDMUL.; REDMUL must not be updated during a running 337 calculation while PKC_STATUS.ACTIV is set.; Changing REDMUL 338 during a running calculation may result in wrong calculation 339 results and/or a PKC security alarm (PKC_ACCESS_ERR.PKCC). */ 340 uint32_t : 20; /*!< reserved */ 341 } CTRL_b; /*!< BitSize */ 342 }; 343 344 union { 345 __IOM uint32_t CFG; /*!< Configuration register */ 346 347 struct { 348 __IOM uint32_t IDLEOP : 1; /*!< Idle operation configuration: If IDLEOP is set idle / dummy 349 operations are executed as soon as PKC_CTRL.RESET is cleared. The 350 idle / dummy operations cycles are inserted also in case of gaps 351 between two real calculation, e.g. between two layer0 352 calculations. The idle / dummy operation is aborted when a real 353 calculation is triggered, e.g., via a set GO bit in PKC_CTRL SFR. 354 In case RNDDLY is unequal 0x0 additional clock cycles with idle / 355 dummy calculation are introduced after setting the GO bit before 356 and after the real calculation.; Due to the idle / dummy activity 357 the average power consumption of the PKC is increased when IDLEOP 358 is set. Beside that the idle / dummy operations have no impact on 359 the calculation time.; IDLEOP can only be updated while the PKC 360 is disabled (PKC_CTRL.RESET=1). Any attempt to update the 361 configuration while RESET=0 will trigger a PKC security alarm 362 (PKC_ACCESS_ERR.CTRL is set). */ 363 __IOM uint32_t RFU1 : 1; /*!< RFU */ 364 __IOM uint32_t RFU2 : 1; /*!< RFU */ 365 __IOM uint32_t CLKRND : 1; /*!< Clock randomization configuration: CLKRND=1 activates the PKC 366 clock randomization. The performance decreases by approx. 8%. 367 Impact on power consumption is negligible.; CLKRND can only be 368 updated while the PKC is disabled (PKC_CTRL.RESET=1). Any attempt 369 to update the configuration while RESET=0 will trigger a PKC 370 security alarm (PKC_ACCESS_ERR.CTRL is set). */ 371 __IOM uint32_t REDMULNOISE: 1; /*!< Noise in reduced multiplier mode configuration: In reduced 372 multiplier mode only parts of the arithmetic PKC logic is 373 utilized. When REDMULNOISE=1 the not used circuitry is loaded 374 with random data to increase the noise level.; REDMULNOISE has no 375 impact in case PKC_CTRL.REDMUL is set to 0x0 or 0x2 (the max. 376 multiplier width). When REDMULNOISE is set for REDMUL equal 0x1 377 the power consumption is increased to the level of REDMUL equal 378 0x0 or 0x2 (full size resp. 64-bit mode).; REDMULNOISE can only 379 be updated while the PKC is disabled (PKC_CTRL.RESET=1). Any 380 attempt to update the configuration while RESET=0 will trigger a 381 PKC security alarm (PKC_ACCESS_ERR.CTRL is set). */ 382 __IOM uint32_t RNDDLY : 3; /*!< Random delay configuration: Define random delay cycles introduced 383 randomly before and after real calculation. The sum of the idle / 384 dummy cycles before and after the real calculation and as such 385 the total calculation time is constant per RNDDLY setting.; The 386 random delay is introduced for each single direct calculation, 387 e.g., for a layer1 MC calculation the delay is inserted for each 388 single Execute opcode.; In case RNDDLY is unequal 0x0 389 PKC_STATUS.ACTIV is cleared and the interrupt is triggered after 390 the real calculation and all delay cycles have finalized. In case 391 PKC_CFG.IDLEOP is set idle / dummy calculations are executed 392 during the delay cycles. Otherwise only the start of the real 393 calculation and the end of calculation signalling is delayed 394 without any activity during the delay cycles.; RNDDLY can only be 395 updated while the PKC is disabled (PKC_CTRL.RESET=1). Any attempt 396 to update the configuration while RESET=0 will trigger a PKC 397 security alarm (PKC_ACCESS_ERR.CTRL is set). */ 398 __IOM uint32_t SBXNOISE : 1; /*!< Noise feature not available in this version. */ 399 __IOM uint32_t ALPNOISE : 1; /*!< Noise feature not available in this version. */ 400 __IOM uint32_t FMULNOISE : 1; /*!< Noise feature not available in this version. */ 401 uint32_t : 21; /*!< reserved */ 402 } CFG_b; /*!< BitSize */ 403 }; 404 __IM uint32_t RESERVED0; 405 406 union { 407 __IOM uint32_t MODE1; /*!< Mode register, parameter set 1 */ 408 409 struct { 410 __IOM uint32_t MODE : 8; /*!< Calculation Mode / MC Start address:; Calculation mode of direct 411 calculation (layer0) are listed in a table in Section 'PKC 412 arithmetic unit (layer 0)'. In case of a not supported 413 calculation mode for layer0 calculation a PKC security alarm is 414 triggered (PKC_ACCESS_ERR.PKCC is set).; MC start addresses for 415 hard coded MC pattern are listed in a table in Section 'Fixed 416 Layer 1 MC Patterns'. The start address for the flexible MC 417 pattern depends on the customized MC code previously stored using 418 SFR PKC_MCDATA (data) and PKC_MODE1 (address).; PKC_MODE1 is 419 additionally used as pointer for the flexible MC initialization. 420 As PKC_MCDATA can only be accessed in chunks of 32-bit the least 421 significant two bits PKC_MODE1[1:0] are ignored. PKC_MODE1 is 422 automatically incremented by 4 for each read/write to PKC_MCDATA. 423 In case PKC_MCDATA is read/written while PKC_CTRL.RESET=0 a 424 security alarm is triggered (PKC_ACCESS_ERR.CTRL is set). */ 425 uint32_t : 24; /*!< reserved */ 426 } MODE1_b; /*!< BitSize */ 427 }; 428 429 union { 430 __IOM uint32_t XYPTR1; /*!< X+Y pointer register, parameter set 1 */ 431 432 struct { 433 __IOM uint32_t XPTR : 16; /*!< Start address of X operand in PKCRAM with byte granularity: Least 434 significant bits are ignored depending on PKC_CTRL.REDMUL 435 setting. Most significant bits are ignored depending on available 436 PKCRAM size. */ 437 __IOM uint32_t YPTR : 16; /*!< Start address of Y operand in PKCRAM with byte granularity: Least 438 significant bits are ignored depending on PKC_CTRL.REDMUL 439 setting. Most significant bits are ignored depending on available 440 PKCRAM size. */ 441 } XYPTR1_b; /*!< BitSize */ 442 }; 443 444 union { 445 __IOM uint32_t ZRPTR1; /*!< Z+R pointer register, parameter set 1 */ 446 447 struct { 448 __IOM uint32_t ZPTR : 16; /*!< Start address of Z operand in PKCRAM with byte granularity or 449 constant for calculation modes using CONST:; If ZPTR is used as 450 address pointer the least significant bits are ignored depending 451 on PKC_CTRL.REDMUL setting. Most significant bits are ignored 452 depending on available PKCRAM size.; If ZPTR is used as CONST 453 operand the high byte is ignored and only ZPTR[7:0] is used for 454 the calculation. For shift/rotate operation further most 455 signficant bits are ignored depending on PKC_CTRL.REDMUL. */ 456 __IOM uint32_t RPTR : 16; /*!< Start address of R result in PKCRAM with byte granularity: Least 457 significant bits are ignored depending on PKC_CTRL.REDMUL 458 setting. Most significant bits are ignored depending on available 459 PKCRAM size. */ 460 } ZRPTR1_b; /*!< BitSize */ 461 }; 462 463 union { 464 __IOM uint32_t LEN1; /*!< Length register, parameter set 1 */ 465 466 struct { 467 __IOM uint32_t LEN : 16; /*!< Operand length: LEN defines the length of the operands and the 468 result in bytes. The length of Y, Z and R depend furthermore on 469 the selected calculation mode.; The least significant bits are 470 ignored depending on PKC_CTRL.REDMUL setting. Most significant 471 bits are ignored depending on available PKCRAM size. In case LEN 472 is too short such that the resulting length depending on 473 PKC_CTRL.REDMUL is zero a PKC security alarm is triggered 474 (PKC_ACCESS_ERR.PKCC is set). */ 475 __IOM uint32_t MCLEN : 16; /*!< Loop counter for microcode pattern: MCLEN defines the length of 476 the loop counter that can be used in layer1 calculation mode, 477 e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns Modular 478 Multiplication (MC start address 0x00), Plain Multiplication 479 (0x13), Plain Multiplication with Addition (0x1D) and Modular 480 Reduction (0x33) MCLEN defines the length of the X operand in 481 bytes.; The least significant bits are ignored depending on 482 PKC_CTRL.REDMUL setting. Most significant bits are ignored 483 depending on available PKCRAM size. In case MCLEN is too short 484 such that a DecrTBNZ MC opcode is executed on a zero loop counter 485 value a PKC security alarm is triggered (PKC_ACCESS_ERR.PKCC is 486 set). */ 487 } LEN1_b; /*!< BitSize */ 488 }; 489 490 union { 491 __IOM uint32_t MODE2; /*!< Mode register, parameter set 2 */ 492 493 struct { 494 __IOM uint32_t MODE : 8; /*!< Calculation Mode / MC Start address:; Calculation mode of direct 495 calculation (layer0) are listed in a table in Section 'PKC 496 arithmetic unit (layer 0)'. In case of a not supported 497 calculation mode for layer0 calculation a PKC security alarm is 498 triggered (PKC_ACCESS_ERR.PKCC is set).; MC start addresses for 499 hard coded MC pattern are listed in a table in Section 'Fixed 500 Layer 1 MC Patterns'. The start address for the flexible MC 501 pattern depends on the customized MC code previously stored using 502 SFR PKC_MCDATA (data) and PKC_MODE1 (address). */ 503 uint32_t : 24; /*!< reserved */ 504 } MODE2_b; /*!< BitSize */ 505 }; 506 507 union { 508 __IOM uint32_t XYPTR2; /*!< X+Y pointer register, parameter set 2 */ 509 510 struct { 511 __IOM uint32_t XPTR : 16; /*!< Start address of X operand in PKCRAM with byte granularity: Least 512 significant bits are ignored depending on PKC_CTRL.REDMUL 513 setting. Most significant bits are ignored depending on available 514 PKCRAM size. */ 515 __IOM uint32_t YPTR : 16; /*!< Start address of Y operand in PKCRAM with byte granularity: Least 516 significant bits are ignored depending on PKC_CTRL.REDMUL 517 setting. Most significant bits are ignored depending on available 518 PKCRAM size. */ 519 } XYPTR2_b; /*!< BitSize */ 520 }; 521 522 union { 523 __IOM uint32_t ZRPTR2; /*!< Z+R pointer register, parameter set 2 */ 524 525 struct { 526 __IOM uint32_t ZPTR : 16; /*!< Start address of Z operand in PKCRAM with byte granularity or 527 constant for calculation modes using CONST:; If ZPTR is used as 528 address pointer the least significant bits are ignored depending 529 on PKC_CTRL.REDMUL setting. Most significant bits are ignored 530 depending on available PKCRAM size.; If ZPTR is used as CONST 531 operand the high byte is ignored and only ZPTR[7:0] is used for 532 the calculation. For shift/rotate operation further most 533 signficant bits are ignored depending on PKC_CTRL.REDMUL. */ 534 __IOM uint32_t RPTR : 16; /*!< Start address of R result in PKCRAM with byte granularity: Least 535 significant bits are ignored depending on PKC_CTRL.REDMUL 536 setting. Most significant bits are ignored depending on available 537 PKCRAM size. */ 538 } ZRPTR2_b; /*!< BitSize */ 539 }; 540 541 union { 542 __IOM uint32_t LEN2; /*!< Length register, parameter set 2 */ 543 544 struct { 545 __IOM uint32_t LEN : 16; /*!< Operand length: LEN defines the length of the operands and the 546 result in bytes. The length of Y, Z and R depend furthermore on 547 the selected calculation mode.; The least significant bits are 548 ignored depending on PKC_CTRL.REDMUL setting. Most significant 549 bits are ignored depending on available PKCRAM size. In case LEN 550 is too short such that the resulting length depending on 551 PKC_CTRL.REDMUL is zero a PKC security alarm is triggered 552 (PKC_ACCESS_ERR.PKCC is set). */ 553 __IOM uint32_t MCLEN : 16; /*!< Loop counter for microcode pattern: MCLEN defines the length of 554 the loop counter that can be used in layer1 calculation mode, 555 e.g. in MC opcode DecrTBNZ. For the hardcoded MC patterns Modular 556 Multiplication (MC start address 0x00); The least significant 557 bits are ignored depending on PKC_CTRL.REDMUL setting. Most 558 significant bits are ignored depending on available PKCRAM size. 559 In case MCLEN is too short such that a DecrTBNZ MC opcode is 560 executed on a zero loop counter value a PKC security alarm is 561 triggered (PKC_ACCESS_ERR.PKCC is set). */ 562 } LEN2_b; /*!< BitSize */ 563 }; 564 __IM uint32_t RESERVED1[4]; 565 566 union { 567 __IOM uint32_t UPTR; /*!< Universal pointer FUP program */ 568 569 struct { 570 __IOM uint32_t PTR : 32; /*!< Pointer to start address of PKC FUP program: PKC_UPTR needs to be 571 defined before starting a universal pointer PKC calculation 572 (layer2) via PKC_CTRL.GOU. The pointer address needs to be valid 573 and the memory space the pointer addresses needs to be enabled 574 for PKC access by the system. Otherwise a security alarm is 575 triggered (PKC_ACCESS_ERR.AHB is set).; PKC_UPTR must not be 576 updated during a running layer2 calculation while 577 PKC_STATUS.GOANY is set. Update of this SFR during a universal 578 pointer fetch calculation may result in wrong calculation results 579 and/or security alarms.; PKC_UPTR is updated by HW during a 580 layer2 calculation, resp. incremented by 6 for each processed FUP 581 program entry. The least signficant bit of PKC_UPTR is ignored as 582 the FUP program has to be stored at even addresses. */ 583 } UPTR_b; /*!< BitSize */ 584 }; 585 586 union { 587 __IOM uint32_t UPTRT; /*!< Universal pointer FUP table */ 588 589 struct { 590 __IOM uint32_t PTR : 32; /*!< Pointer to start address of PKC FUP table: PKC_UPTRT needs to be 591 defined before starting a universal pointer PKC calculation 592 (layer2) via PKC_CTRL.GOU. The pointer address needs to be valid 593 and the memory space the pointer addresses needs to be enabled 594 for PKC access by the system. Otherwise a security alarm is 595 triggered (PKC_ACCESS_ERR.AHB is set).; PKC_UPTRT must not be 596 updated during a running layer2 calculation while 597 PKC_STATUS.GOANY is set. Update of this SFR during a universal 598 pointer fetch calculation may result in wrong calculation results 599 and/or security alarms.; PKC_UPTRT is not updated by HW during a 600 layer2 calculation. The least signficant bit of PKC_UPTRT is 601 ignored as the FUP table has to be stored at even addresses.; Any 602 SFR write access to PKC_UPTRT triggers the invalidation of the 603 universal pointer cache, similar to PKC_CTRL.CLRCACHE. */ 604 } UPTRT_b; /*!< BitSize */ 605 }; 606 607 union { 608 __IOM uint32_t ULEN; /*!< Universal pointer length */ 609 610 struct { 611 __IOM uint32_t LEN : 8; /*!< Length of universal pointer calculation: PKC_ULEN defines how 612 many FUP program entries shall be processed for one layer2 613 calculation started via PKC_CTRL.GOU. The FUP program entries 614 include layer0 calculations, layer1 calculations and CRC entries 615 for FUP program integrity protection.; PKC_ULEN must not be 616 updated during a running layer2 calculation while 617 PKC_STATUS.GOANY is set. Update of this SFR during a universal 618 pointer fetch calculation may result in wrong calculation results 619 and/or security alarms.; Starting a univesal pointer fetch 620 calculation via PKC_CTRL.GOU while PKC_ULEN is zero triggers a 621 security alarm (PKC_ACCESS_ERR.CTRL is set).; PKC_ULEN is updated 622 by HW during a layer2 calculation, resp. decremented for each 623 processed FUP program entry. When PKC_ULEN has been decremented 624 to zero PKC_STATUS.GOANY is cleared to indicate the start of the 625 last calculation. When the PKC has finalized its last pipe 626 calculation PKC_STATUS.ACTIV is cleared and the interrupt status 627 bit PKC_INT_STATUS.INT_PDONE is set. */ 628 uint32_t : 24; /*!< reserved */ 629 } ULEN_b; /*!< BitSize */ 630 }; 631 __IM uint32_t RESERVED2; 632 633 union { 634 __IOM uint32_t MCDATA; /*!< MC pattern data interface */ 635 636 struct { 637 __IOM uint32_t MCDATA : 32; /*!< Microcode read/write data: Read access to PKC_MCDATA returns the 638 32-bit MC pattern addressed by PKC_MODE1. Default value of all 639 flexible MC bytes after reset is 0xFF (invalid MC instruction). 640 Read to PKC_MCDATA while PKC_CTRL.RESET=0 or PKC_MODE1<0x80 641 (fixed MC pattern) triggers a security alarm (PKC_ACCESS_ERR.CTRL 642 is set).; NOTE: When trying to read flexible MC bytes not 643 existing (e.g., fixed MC bytes) a data value of 0 is returned.; A 644 SFR write to PKC_MCDATA initializes the MC pattern PKC_MODE1 645 points to. Write to PKC_MCDATA while PKC_CTRL.RESET=0 or 646 PKC_MODE1<0x80 (fixed MC pattern) triggers a security alarm 647 (PKC_ACCESS_ERR.CTRL is set).; Any SFR access to PKC_MCDATA 648 increments the PKC_MODE1 SFR by 4. As PKC_MCDATA is always 649 accessed with 32-bit width the least signficant bits 650 PKC_MODE1[1:0] are ignored for the MC flexible data addressing. */ 651 } MCDATA_b; /*!< BitSize */ 652 }; 653 __IM uint32_t RESERVED3[3]; 654 655 union { 656 __IM uint32_t VERSION; /*!< PKC version register */ 657 658 struct { 659 __IM uint32_t MULSIZE : 2; /*!< native multiplier size and operand granularity */ 660 __IM uint32_t MCAVAIL : 1; /*!< MC feature (layer1 calculation) is available */ 661 __IM uint32_t UPAVAIL : 1; /*!< UP feature (layer2 calculation) is available */ 662 __IM uint32_t UPCACHEAVAIL: 1; /*!< UP cache is available */ 663 __IM uint32_t GF2AVAIL : 1; /*!< GF2 calculation modes are available */ 664 __IM uint32_t PARAMNUM : 2; /*!< Number of parameter sets for real calculation */ 665 __IM uint32_t SBX0AVAIL : 1; /*!< SBX0 operation is available */ 666 __IM uint32_t SBX1AVAIL : 1; /*!< SBX1 operation is available */ 667 __IM uint32_t SBX2AVAIL : 1; /*!< SBX2 operation is available */ 668 __IM uint32_t SBX3AVAIL : 1; /*!< SBX3 operation is available */ 669 __IM uint32_t MCRECONF_SIZE: 8; /*!< Size of reconfigurable MC table in bytes */ 670 uint32_t : 12; /*!< reserved */ 671 } VERSION_b; /*!< BitSize */ 672 }; 673 __IM uint32_t RESERVED4[979]; 674 675 union { 676 __IOM uint32_t SOFT_RST; /*!< Software reset */ 677 678 struct { 679 __IOM uint32_t SOFT_RST : 1; /*!< Write 1 to reset module (0 has no effect). All running and 680 pending PKC calculation are stopped. All PKC SFRs are reset 681 except PKC_ACCESS_ERR. */ 682 uint32_t : 31; /*!< reserved */ 683 } SOFT_RST_b; /*!< BitSize */ 684 }; 685 __IM uint32_t RESERVED5[3]; 686 687 union { 688 __IM uint32_t ACCESS_ERR; /*!< Access Error */ 689 690 struct { 691 __IM uint32_t APB_NOTAV : 1; /*!< APB Error: address not available */ 692 __IM uint32_t APB_WRGMD : 1; /*!< APB Error: Wrong access mode */ 693 uint32_t : 2; /*!< reserved for future erors on SPB I/F */ 694 __IM uint32_t APB_MASTER : 4; /*!< APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV */ 695 uint32_t : 2; /*!< reserved for future erors on AHB I/F Layer2 Only */ 696 __IM uint32_t AHB : 1; /*!< AHB Error: invalid AHB access Layer2 Only */ 697 uint32_t : 5; /*!< reserved for future erors on AHB I/F Layer2 Only */ 698 __IM uint32_t PKCC : 1; /*!< Error in PKC coprocessor kernel */ 699 __IM uint32_t FDET : 1; /*!< Error due to error detection circuitry */ 700 __IM uint32_t CTRL : 1; /*!< Error in PKC software control */ 701 __IM uint32_t UCRC : 1; /*!< Error in layer2 CRC check */ 702 uint32_t : 1; /*!< reserved */ 703 uint32_t : 11; /*!< reserved for more block errors */ 704 } ACCESS_ERR_b; /*!< BitSize */ 705 }; 706 707 union { 708 __IOM uint32_t ACCESS_ERR_CLR; /*!< Clear Access Error */ 709 710 struct { 711 __IOM uint32_t ERR_CLR : 1; /*!< Write 1 to reset PKC_ACCESS_ERR SFR. */ 712 uint32_t : 31; /*!< reserved */ 713 } ACCESS_ERR_CLR_b; /*!< BitSize */ 714 }; 715 __IM uint32_t RESERVED6[4]; 716 717 union { 718 __IOM uint32_t INT_CLR_ENABLE; /*!< Interrupt enable clear */ 719 720 struct { 721 __IOM uint32_t EN_PDONE : 1; /*!< Write to clear PDONE interrupt enable flag 722 (PKC_INT_ENABLE.EN_PDONE=0). */ 723 uint32_t : 1; /*!< reserved */ 724 uint32_t : 30; /*!< reserved */ 725 } INT_CLR_ENABLE_b; /*!< BitSize */ 726 }; 727 728 union { 729 __IOM uint32_t INT_SET_ENABLE; /*!< Interrupt enable set */ 730 731 struct { 732 __IOM uint32_t EN_PDONE : 1; /*!< Write to set PDONE interrupt enable flag 733 (PKC_INT_ENABLE.EN_PDONE=1). */ 734 uint32_t : 1; /*!< reserved */ 735 uint32_t : 30; /*!< reserved */ 736 } INT_SET_ENABLE_b; /*!< BitSize */ 737 }; 738 739 union { 740 __IM uint32_t INT_STATUS; /*!< Interrupt status */ 741 742 struct { 743 __IM uint32_t INT_PDONE : 1; /*!< End-of-computation status flag: INT_PDONE is set after EACH 744 single PKC layer0 or layer1 calculation. In case of a universal 745 pointer calculation (layer2) INT_PDONE is set at the end of the 746 pipe calculation when PKC_ULEN has been decremented to zero and 747 the final PKC calculation has completed.; INT_PDONE is set 748 independent from the interrupt enable PKC_INT_ENABLE.EN_PDONE. In 749 case PKC_INT_ENABLE.EN_PDONE=1 an interrupt towards the CPU is 750 triggered when INT_PDONE is set (level triggered).; INT_PDONE is 751 not cleared by PKC hardware but has to be cleared by software, 752 except in case of a reset (chip/block reset, PKC_SOFT_RST, PKC 753 security alarm). */ 754 uint32_t : 1; /*!< reserved */ 755 uint32_t : 30; /*!< reserved */ 756 } INT_STATUS_b; /*!< BitSize */ 757 }; 758 759 union { 760 __IM uint32_t INT_ENABLE; /*!< Interrupt enable */ 761 762 struct { 763 __IM uint32_t EN_PDONE : 1; /*!< PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is 764 triggered every time PKC_INT_STATUS.INT_PDONE is set. Otherwise 765 the interrupt generation is suppressed. */ 766 uint32_t : 1; /*!< reserved */ 767 uint32_t : 30; /*!< reserved */ 768 } INT_ENABLE_b; /*!< BitSize */ 769 }; 770 771 union { 772 __IOM uint32_t INT_CLR_STATUS; /*!< Interrupt status clear */ 773 774 struct { 775 __IOM uint32_t INT_PDONE : 1; /*!< Write to clear End-of-computation status flag 776 (PKC_INT_STATUS.INT_PDONE=0). */ 777 uint32_t : 1; /*!< reserved */ 778 uint32_t : 30; /*!< reserved */ 779 } INT_CLR_STATUS_b; /*!< BitSize */ 780 }; 781 782 union { 783 __IOM uint32_t INT_SET_STATUS; /*!< Interrupt status set */ 784 785 struct { 786 __IOM uint32_t INT_PDONE : 1; /*!< Write to set End-of-computation status flag 787 (PKC_INT_STATUS.INT_PDONE=1) to trigger a PKC interrupt via 788 software, e.g. for debug purposes. */ 789 uint32_t : 1; /*!< reserved */ 790 uint32_t : 30; /*!< reserved */ 791 } INT_SET_STATUS_b; /*!< BitSize */ 792 }; 793 __IM uint32_t RESERVED7[3]; 794 795 union { 796 __IM uint32_t MODULE_ID; /*!< Module ID */ 797 798 struct { 799 __IM uint32_t SIZE : 8; /*!< Address space of the IP */ 800 __IM uint32_t MINOR_REV : 4; /*!< Minor revision */ 801 __IM uint32_t MAJOR_REV : 4; /*!< Major revision */ 802 __IM uint32_t ID : 16; /*!< Module ID */ 803 } MODULE_ID_b; /*!< BitSize */ 804 }; 805 } ip_pkc_Type; 806 807 808 /* ================================================================================ */ 809 /* ================ Detailed bit description ================ */ 810 /* ================================================================================ */ 811 812 /* ================ Bit field only ================ */ 813 #define PKC_CTRL_b_REDMUL_FULLSZ 0x0 /*!< full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008*/ 814 #define PKC_CTRL_b_REDMUL_32BIT 0x1 /*!< RFU Error Generated if selected */ 815 #define PKC_CTRL_b_REDMUL_64BIT 0x2 /*!< 64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008*/ 816 #define PKC_CTRL_b_REDMUL_128BIT 0x3 /*!< RFU Error Generated if selected */ 817 818 #define PKC_CFG_b_RNDDLY_NODLY 0x0 /*!< no random delay */ 819 #define PKC_CFG_b_RNDDLY_1DLY 0x1 /*!< 1x4 clocks delay */ 820 #define PKC_CFG_b_RNDDLY_3DLY 0x2 /*!< 3x4 clocks delay */ 821 #define PKC_CFG_b_RNDDLY_7DLY 0x3 /*!< 7x4 clocks delay */ 822 #define PKC_CFG_b_RNDDLY_15DLY 0x4 /*!< 15x4 clocks delay */ 823 #define PKC_CFG_b_RNDDLY_31DLY 0x5 /*!< 31x4 clocks delay */ 824 #define PKC_CFG_b_RNDDLY_63DLY 0x6 /*!< 63x4 clocks delay */ 825 #define PKC_CFG_b_RNDDLY_127DLY 0x7 /*!< 127x4 clocks delay */ 826 827 #define PKC_VERSION_b_MULSIZE_32B 0x1 /*!< 32-bit multiplier */ 828 #define PKC_VERSION_b_MULSIZE_64B 0x2 /*!< 64-bit multiplier */ 829 #define PKC_VERSION_b_MULSIZE_128B 0x3 /*!< 128-bit multiplier */ 830 831 /* ================ Complete SFR ================ */ 832 #define PKC_CTRL_REDMUL_FULLSZ 0x00000000 /*!< full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008*/ 833 #define PKC_CTRL_REDMUL_32BIT 0x00000400 /*!< RFU Error Generated if selected */ 834 #define PKC_CTRL_REDMUL_64BIT 0x00000800 /*!< 64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008*/ 835 #define PKC_CTRL_REDMUL_128BIT 0x00000C00 /*!< RFU Error Generated if selected */ 836 837 #define PKC_CFG_RNDDLY_NODLY 0x00000000 /*!< no random delay */ 838 #define PKC_CFG_RNDDLY_1DLY 0x00000020 /*!< 1x4 clocks delay */ 839 #define PKC_CFG_RNDDLY_3DLY 0x00000040 /*!< 3x4 clocks delay */ 840 #define PKC_CFG_RNDDLY_7DLY 0x00000060 /*!< 7x4 clocks delay */ 841 #define PKC_CFG_RNDDLY_15DLY 0x00000080 /*!< 15x4 clocks delay */ 842 #define PKC_CFG_RNDDLY_31DLY 0x000000A0 /*!< 31x4 clocks delay */ 843 #define PKC_CFG_RNDDLY_63DLY 0x000000C0 /*!< 63x4 clocks delay */ 844 #define PKC_CFG_RNDDLY_127DLY 0x000000E0 /*!< 127x4 clocks delay */ 845 846 #define PKC_VERSION_MULSIZE_32B 0x00000001 /*!< 32-bit multiplier */ 847 #define PKC_VERSION_MULSIZE_64B 0x00000002 /*!< 64-bit multiplier */ 848 #define PKC_VERSION_MULSIZE_128B 0x00000003 /*!< 128-bit multiplier */ 849 850 851 852 /* ==================== End of section using anonymous unions =================== */ 853 #if defined(__CC_ARM) 854 #pragma pop 855 #elif defined(__ICCARM__) 856 /* leave anonymous unions enabled */ 857 #elif (__ARMCC_VERSION >= 6010050) 858 #pragma clang diagnostic pop 859 #elif defined(__GNUC__) 860 /* anonymous unions are enabled by default */ 861 #elif defined(__TMS470__) 862 /* anonymous unions are enabled by default */ 863 #elif defined(__TASKING__) 864 #pragma warning restore 865 #elif defined(__CSMC__) 866 /* anonymous unions are enabled by default */ 867 #else 868 #warning Not supported compiler type 869 #endif 870 871 872 873 /* ================================================================================ */ 874 /* ================ struct 'PKC' Position & Mask ================ */ 875 /* ================================================================================ */ 876 877 878 /* =============================== PKC_STATUS ============================== */ 879 #define PKC_STATUS_ACTIV_Pos 0 /*!< PKC_STATUS: ACTIV Position */ 880 #define PKC_STATUS_ACTIV_Msk (0x01UL << PKC_STATUS_ACTIV_Pos) /*!< PKC_STATUS: ACTIV Mask */ 881 #define PKC_STATUS_CARRY_Pos 1 /*!< PKC_STATUS: CARRY Position */ 882 #define PKC_STATUS_CARRY_Msk (0x01UL << PKC_STATUS_CARRY_Pos) /*!< PKC_STATUS: CARRY Mask */ 883 #define PKC_STATUS_ZERO_Pos 2 /*!< PKC_STATUS: ZERO Position */ 884 #define PKC_STATUS_ZERO_Msk (0x01UL << PKC_STATUS_ZERO_Pos) /*!< PKC_STATUS: ZERO Mask */ 885 #define PKC_STATUS_GOANY_Pos 3 /*!< PKC_STATUS: GOANY Position */ 886 #define PKC_STATUS_GOANY_Msk (0x01UL << PKC_STATUS_GOANY_Pos) /*!< PKC_STATUS: GOANY Mask */ 887 #define PKC_STATUS_RESERVED0_Pos 4 /*!< PKC_STATUS: RESERVED0 Position */ 888 #define PKC_STATUS_RESERVED0_Msk (0x01UL << PKC_STATUS_RESERVED0_Pos) /*!< PKC_STATUS: RESERVED0 Mask */ 889 #define PKC_STATUS_LOCKED_Pos 5 /*!< PKC_STATUS: LOCKED Position */ 890 #define PKC_STATUS_LOCKED_Msk (0x03UL << PKC_STATUS_LOCKED_Pos) /*!< PKC_STATUS: LOCKED Mask */ 891 #define PKC_STATUS_RESERVED1_Pos 7 /*!< PKC_STATUS: RESERVED1 Position */ 892 #define PKC_STATUS_RESERVED1_Msk (0x01ffffffUL << PKC_STATUS_RESERVED1_Pos) /*!< PKC_STATUS: RESERVED1 Mask */ 893 894 /* =============================== PKC_CTRL ============================== */ 895 #define PKC_CTRL_RESET_Pos 0 /*!< PKC_CTRL: RESET Position */ 896 #define PKC_CTRL_RESET_Msk (0x01UL << PKC_CTRL_RESET_Pos) /*!< PKC_CTRL: RESET Mask */ 897 #define PKC_CTRL_STOP_Pos 1 /*!< PKC_CTRL: STOP Position */ 898 #define PKC_CTRL_STOP_Msk (0x01UL << PKC_CTRL_STOP_Pos) /*!< PKC_CTRL: STOP Mask */ 899 #define PKC_CTRL_GOD1_Pos 2 /*!< PKC_CTRL: GOD1 Position */ 900 #define PKC_CTRL_GOD1_Msk (0x01UL << PKC_CTRL_GOD1_Pos) /*!< PKC_CTRL: GOD1 Mask */ 901 #define PKC_CTRL_GOD2_Pos 3 /*!< PKC_CTRL: GOD2 Position */ 902 #define PKC_CTRL_GOD2_Msk (0x01UL << PKC_CTRL_GOD2_Pos) /*!< PKC_CTRL: GOD2 Mask */ 903 #define PKC_CTRL_GOM1_Pos 4 /*!< PKC_CTRL: GOM1 Position */ 904 #define PKC_CTRL_GOM1_Msk (0x01UL << PKC_CTRL_GOM1_Pos) /*!< PKC_CTRL: GOM1 Mask */ 905 #define PKC_CTRL_GOM2_Pos 5 /*!< PKC_CTRL: GOM2 Position */ 906 #define PKC_CTRL_GOM2_Msk (0x01UL << PKC_CTRL_GOM2_Pos) /*!< PKC_CTRL: GOM2 Mask */ 907 #define PKC_CTRL_GOU_Pos 6 /*!< PKC_CTRL: GOU Position */ 908 #define PKC_CTRL_GOU_Msk (0x01UL << PKC_CTRL_GOU_Pos) /*!< PKC_CTRL: GOU Mask */ 909 #define PKC_CTRL_GF2CONV_Pos 7 /*!< PKC_CTRL: GF2CONV Position */ 910 #define PKC_CTRL_GF2CONV_Msk (0x01UL << PKC_CTRL_GF2CONV_Pos) /*!< PKC_CTRL: GF2CONV Mask */ 911 #define PKC_CTRL_CLRCACHE_Pos 8 /*!< PKC_CTRL: CLRCACHE Position */ 912 #define PKC_CTRL_CLRCACHE_Msk (0x01UL << PKC_CTRL_CLRCACHE_Pos) /*!< PKC_CTRL: CLRCACHE Mask */ 913 #define PKC_CTRL_CACHE_EN_Pos 9 /*!< PKC_CTRL: CACHE_EN Position */ 914 #define PKC_CTRL_CACHE_EN_Msk (0x01UL << PKC_CTRL_CACHE_EN_Pos) /*!< PKC_CTRL: CACHE_EN Mask */ 915 #define PKC_CTRL_REDMUL_Pos 10 /*!< PKC_CTRL: REDMUL Position */ 916 #define PKC_CTRL_REDMUL_Msk (0x03UL << PKC_CTRL_REDMUL_Pos) /*!< PKC_CTRL: REDMUL Mask */ 917 #define PKC_CTRL_RESERVED_Pos 12 /*!< PKC_CTRL: RESERVED Position */ 918 #define PKC_CTRL_RESERVED_Msk (0x000fffffUL << PKC_CTRL_RESERVED_Pos) /*!< PKC_CTRL: RESERVED Mask */ 919 920 /* =============================== PKC_CFG ============================== */ 921 #define PKC_CFG_IDLEOP_Pos 0 /*!< PKC_CFG: IDLEOP Position */ 922 #define PKC_CFG_IDLEOP_Msk (0x01UL << PKC_CFG_IDLEOP_Pos) /*!< PKC_CFG: IDLEOP Mask */ 923 #define PKC_CFG_RFU1_Pos 1 /*!< PKC_CFG: RFU1 Position */ 924 #define PKC_CFG_RFU1_Msk (0x01UL << PKC_CFG_RFU1_Pos) /*!< PKC_CFG: RFU1 Mask */ 925 #define PKC_CFG_RFU2_Pos 2 /*!< PKC_CFG: RFU2 Position */ 926 #define PKC_CFG_RFU2_Msk (0x01UL << PKC_CFG_RFU2_Pos) /*!< PKC_CFG: RFU2 Mask */ 927 #define PKC_CFG_CLKRND_Pos 3 /*!< PKC_CFG: CLKRND Position */ 928 #define PKC_CFG_CLKRND_Msk (0x01UL << PKC_CFG_CLKRND_Pos) /*!< PKC_CFG: CLKRND Mask */ 929 #define PKC_CFG_REDMULNOISE_Pos 4 /*!< PKC_CFG: REDMULNOISE Position */ 930 #define PKC_CFG_REDMULNOISE_Msk (0x01UL << PKC_CFG_REDMULNOISE_Pos) /*!< PKC_CFG: REDMULNOISE Mask */ 931 #define PKC_CFG_RNDDLY_Pos 5 /*!< PKC_CFG: RNDDLY Position */ 932 #define PKC_CFG_RNDDLY_Msk (0x07UL << PKC_CFG_RNDDLY_Pos) /*!< PKC_CFG: RNDDLY Mask */ 933 #define PKC_CFG_SBXNOISE_Pos 8 /*!< PKC_CFG: SBXNOISE Position */ 934 #define PKC_CFG_SBXNOISE_Msk (0x01UL << PKC_CFG_SBXNOISE_Pos) /*!< PKC_CFG: SBXNOISE Mask */ 935 #define PKC_CFG_ALPNOISE_Pos 9 /*!< PKC_CFG: ALPNOISE Position */ 936 #define PKC_CFG_ALPNOISE_Msk (0x01UL << PKC_CFG_ALPNOISE_Pos) /*!< PKC_CFG: ALPNOISE Mask */ 937 #define PKC_CFG_FMULNOISE_Pos 10 /*!< PKC_CFG: FMULNOISE Position */ 938 #define PKC_CFG_FMULNOISE_Msk (0x01UL << PKC_CFG_FMULNOISE_Pos) /*!< PKC_CFG: FMULNOISE Mask */ 939 #define PKC_CFG_RESERVED_Pos 11 /*!< PKC_CFG: RESERVED Position */ 940 #define PKC_CFG_RESERVED_Msk (0x001fffffUL << PKC_CFG_RESERVED_Pos) /*!< PKC_CFG: RESERVED Mask */ 941 942 /* =============================== PKC_MODE1 ============================== */ 943 #define PKC_MODE1_MODE_Pos 0 /*!< PKC_MODE1: MODE Position */ 944 #define PKC_MODE1_MODE_Msk (0x000000ffUL << PKC_MODE1_MODE_Pos) /*!< PKC_MODE1: MODE Mask */ 945 #define PKC_MODE1_RESERVED_Pos 8 /*!< PKC_MODE1: RESERVED Position */ 946 #define PKC_MODE1_RESERVED_Msk (0x00ffffffUL << PKC_MODE1_RESERVED_Pos) /*!< PKC_MODE1: RESERVED Mask */ 947 948 /* =============================== PKC_XYPTR1 ============================== */ 949 #define PKC_XYPTR1_XPTR_Pos 0 /*!< PKC_XYPTR1: XPTR Position */ 950 #define PKC_XYPTR1_XPTR_Msk (0x0000ffffUL << PKC_XYPTR1_XPTR_Pos) /*!< PKC_XYPTR1: XPTR Mask */ 951 #define PKC_XYPTR1_YPTR_Pos 16 /*!< PKC_XYPTR1: YPTR Position */ 952 #define PKC_XYPTR1_YPTR_Msk (0x0000ffffUL << PKC_XYPTR1_YPTR_Pos) /*!< PKC_XYPTR1: YPTR Mask */ 953 954 /* =============================== PKC_ZRPTR1 ============================== */ 955 #define PKC_ZRPTR1_ZPTR_Pos 0 /*!< PKC_ZRPTR1: ZPTR Position */ 956 #define PKC_ZRPTR1_ZPTR_Msk (0x0000ffffUL << PKC_ZRPTR1_ZPTR_Pos) /*!< PKC_ZRPTR1: ZPTR Mask */ 957 #define PKC_ZRPTR1_RPTR_Pos 16 /*!< PKC_ZRPTR1: RPTR Position */ 958 #define PKC_ZRPTR1_RPTR_Msk (0x0000ffffUL << PKC_ZRPTR1_RPTR_Pos) /*!< PKC_ZRPTR1: RPTR Mask */ 959 960 /* =============================== PKC_LEN1 ============================== */ 961 #define PKC_LEN1_LEN_Pos 0 /*!< PKC_LEN1: LEN Position */ 962 #define PKC_LEN1_LEN_Msk (0x0000ffffUL << PKC_LEN1_LEN_Pos) /*!< PKC_LEN1: LEN Mask */ 963 #define PKC_LEN1_MCLEN_Pos 16 /*!< PKC_LEN1: MCLEN Position */ 964 #define PKC_LEN1_MCLEN_Msk (0x0000ffffUL << PKC_LEN1_MCLEN_Pos) /*!< PKC_LEN1: MCLEN Mask */ 965 966 /* =============================== PKC_MODE2 ============================== */ 967 #define PKC_MODE2_MODE_Pos 0 /*!< PKC_MODE2: MODE Position */ 968 #define PKC_MODE2_MODE_Msk (0x000000ffUL << PKC_MODE2_MODE_Pos) /*!< PKC_MODE2: MODE Mask */ 969 #define PKC_MODE2_RESERVED_Pos 8 /*!< PKC_MODE2: RESERVED Position */ 970 #define PKC_MODE2_RESERVED_Msk (0x00ffffffUL << PKC_MODE2_RESERVED_Pos) /*!< PKC_MODE2: RESERVED Mask */ 971 972 /* =============================== PKC_XYPTR2 ============================== */ 973 #define PKC_XYPTR2_XPTR_Pos 0 /*!< PKC_XYPTR2: XPTR Position */ 974 #define PKC_XYPTR2_XPTR_Msk (0x0000ffffUL << PKC_XYPTR2_XPTR_Pos) /*!< PKC_XYPTR2: XPTR Mask */ 975 #define PKC_XYPTR2_YPTR_Pos 16 /*!< PKC_XYPTR2: YPTR Position */ 976 #define PKC_XYPTR2_YPTR_Msk (0x0000ffffUL << PKC_XYPTR2_YPTR_Pos) /*!< PKC_XYPTR2: YPTR Mask */ 977 978 /* =============================== PKC_ZRPTR2 ============================== */ 979 #define PKC_ZRPTR2_ZPTR_Pos 0 /*!< PKC_ZRPTR2: ZPTR Position */ 980 #define PKC_ZRPTR2_ZPTR_Msk (0x0000ffffUL << PKC_ZRPTR2_ZPTR_Pos) /*!< PKC_ZRPTR2: ZPTR Mask */ 981 #define PKC_ZRPTR2_RPTR_Pos 16 /*!< PKC_ZRPTR2: RPTR Position */ 982 #define PKC_ZRPTR2_RPTR_Msk (0x0000ffffUL << PKC_ZRPTR2_RPTR_Pos) /*!< PKC_ZRPTR2: RPTR Mask */ 983 984 /* =============================== PKC_LEN2 ============================== */ 985 #define PKC_LEN2_LEN_Pos 0 /*!< PKC_LEN2: LEN Position */ 986 #define PKC_LEN2_LEN_Msk (0x0000ffffUL << PKC_LEN2_LEN_Pos) /*!< PKC_LEN2: LEN Mask */ 987 #define PKC_LEN2_MCLEN_Pos 16 /*!< PKC_LEN2: MCLEN Position */ 988 #define PKC_LEN2_MCLEN_Msk (0x0000ffffUL << PKC_LEN2_MCLEN_Pos) /*!< PKC_LEN2: MCLEN Mask */ 989 990 /* =============================== PKC_UPTR ============================== */ 991 #define PKC_UPTR_PTR_Pos 0 /*!< PKC_UPTR: PTR Position */ 992 #define PKC_UPTR_PTR_Msk (0xffffffffUL << PKC_UPTR_PTR_Pos) /*!< PKC_UPTR: PTR Mask */ 993 994 /* =============================== PKC_UPTRT ============================== */ 995 #define PKC_UPTRT_PTR_Pos 0 /*!< PKC_UPTRT: PTR Position */ 996 #define PKC_UPTRT_PTR_Msk (0xffffffffUL << PKC_UPTRT_PTR_Pos) /*!< PKC_UPTRT: PTR Mask */ 997 998 /* =============================== PKC_ULEN ============================== */ 999 #define PKC_ULEN_LEN_Pos 0 /*!< PKC_ULEN: LEN Position */ 1000 #define PKC_ULEN_LEN_Msk (0x000000ffUL << PKC_ULEN_LEN_Pos) /*!< PKC_ULEN: LEN Mask */ 1001 #define PKC_ULEN_RESERVED_Pos 8 /*!< PKC_ULEN: RESERVED Position */ 1002 #define PKC_ULEN_RESERVED_Msk (0x00ffffffUL << PKC_ULEN_RESERVED_Pos) /*!< PKC_ULEN: RESERVED Mask */ 1003 1004 /* =============================== PKC_MCDATA ============================== */ 1005 #define PKC_MCDATA_MCDATA_Pos 0 /*!< PKC_MCDATA: MCDATA Position */ 1006 #define PKC_MCDATA_MCDATA_Msk (0xffffffffUL << PKC_MCDATA_MCDATA_Pos) /*!< PKC_MCDATA: MCDATA Mask */ 1007 1008 /* =============================== PKC_VERSION ============================== */ 1009 #define PKC_VERSION_MULSIZE_Pos 0 /*!< PKC_VERSION: MULSIZE Position */ 1010 #define PKC_VERSION_MULSIZE_Msk (0x03UL << PKC_VERSION_MULSIZE_Pos) /*!< PKC_VERSION: MULSIZE Mask */ 1011 #define PKC_VERSION_MCAVAIL_Pos 2 /*!< PKC_VERSION: MCAVAIL Position */ 1012 #define PKC_VERSION_MCAVAIL_Msk (0x01UL << PKC_VERSION_MCAVAIL_Pos) /*!< PKC_VERSION: MCAVAIL Mask */ 1013 #define PKC_VERSION_UPAVAIL_Pos 3 /*!< PKC_VERSION: UPAVAIL Position */ 1014 #define PKC_VERSION_UPAVAIL_Msk (0x01UL << PKC_VERSION_UPAVAIL_Pos) /*!< PKC_VERSION: UPAVAIL Mask */ 1015 #define PKC_VERSION_UPCACHEAVAIL_Pos 4 /*!< PKC_VERSION: UPCACHEAVAIL Position */ 1016 #define PKC_VERSION_UPCACHEAVAIL_Msk (0x01UL << PKC_VERSION_UPCACHEAVAIL_Pos) /*!< PKC_VERSION: UPCACHEAVAIL Mask */ 1017 #define PKC_VERSION_GF2AVAIL_Pos 5 /*!< PKC_VERSION: GF2AVAIL Position */ 1018 #define PKC_VERSION_GF2AVAIL_Msk (0x01UL << PKC_VERSION_GF2AVAIL_Pos) /*!< PKC_VERSION: GF2AVAIL Mask */ 1019 #define PKC_VERSION_PARAMNUM_Pos 6 /*!< PKC_VERSION: PARAMNUM Position */ 1020 #define PKC_VERSION_PARAMNUM_Msk (0x03UL << PKC_VERSION_PARAMNUM_Pos) /*!< PKC_VERSION: PARAMNUM Mask */ 1021 #define PKC_VERSION_SBX0AVAIL_Pos 8 /*!< PKC_VERSION: SBX0AVAIL Position */ 1022 #define PKC_VERSION_SBX0AVAIL_Msk (0x01UL << PKC_VERSION_SBX0AVAIL_Pos) /*!< PKC_VERSION: SBX0AVAIL Mask */ 1023 #define PKC_VERSION_SBX1AVAIL_Pos 9 /*!< PKC_VERSION: SBX1AVAIL Position */ 1024 #define PKC_VERSION_SBX1AVAIL_Msk (0x01UL << PKC_VERSION_SBX1AVAIL_Pos) /*!< PKC_VERSION: SBX1AVAIL Mask */ 1025 #define PKC_VERSION_SBX2AVAIL_Pos 10 /*!< PKC_VERSION: SBX2AVAIL Position */ 1026 #define PKC_VERSION_SBX2AVAIL_Msk (0x01UL << PKC_VERSION_SBX2AVAIL_Pos) /*!< PKC_VERSION: SBX2AVAIL Mask */ 1027 #define PKC_VERSION_SBX3AVAIL_Pos 11 /*!< PKC_VERSION: SBX3AVAIL Position */ 1028 #define PKC_VERSION_SBX3AVAIL_Msk (0x01UL << PKC_VERSION_SBX3AVAIL_Pos) /*!< PKC_VERSION: SBX3AVAIL Mask */ 1029 #define PKC_VERSION_MCRECONF_SIZE_Pos 12 /*!< PKC_VERSION: MCRECONF_SIZE Position */ 1030 #define PKC_VERSION_MCRECONF_SIZE_Msk (0x000000ffUL << PKC_VERSION_MCRECONF_SIZE_Pos) /*!< PKC_VERSION: MCRECONF_SIZE Mask */ 1031 #define PKC_VERSION_RESERVED_Pos 20 /*!< PKC_VERSION: RESERVED Position */ 1032 #define PKC_VERSION_RESERVED_Msk (0x00000fffUL << PKC_VERSION_RESERVED_Pos) /*!< PKC_VERSION: RESERVED Mask */ 1033 1034 /* =============================== PKC_SOFT_RST ============================== */ 1035 #define PKC_SOFT_RST_SOFT_RST_Pos 0 /*!< PKC_SOFT_RST: SOFT_RST Position */ 1036 #define PKC_SOFT_RST_SOFT_RST_Msk (0x01UL << PKC_SOFT_RST_SOFT_RST_Pos) /*!< PKC_SOFT_RST: SOFT_RST Mask */ 1037 #define PKC_SOFT_RST_RESERVED_Pos 1 /*!< PKC_SOFT_RST: RESERVED Position */ 1038 #define PKC_SOFT_RST_RESERVED_Msk (0x7fffffffUL << PKC_SOFT_RST_RESERVED_Pos) /*!< PKC_SOFT_RST: RESERVED Mask */ 1039 1040 /* =============================== PKC_ACCESS_ERR ============================== */ 1041 #define PKC_ACCESS_ERR_APB_NOTAV_Pos 0 /*!< PKC_ACCESS_ERR: APB_NOTAV Position */ 1042 #define PKC_ACCESS_ERR_APB_NOTAV_Msk (0x01UL << PKC_ACCESS_ERR_APB_NOTAV_Pos) /*!< PKC_ACCESS_ERR: APB_NOTAV Mask */ 1043 #define PKC_ACCESS_ERR_APB_WRGMD_Pos 1 /*!< PKC_ACCESS_ERR: APB_WRGMD Position */ 1044 #define PKC_ACCESS_ERR_APB_WRGMD_Msk (0x01UL << PKC_ACCESS_ERR_APB_WRGMD_Pos) /*!< PKC_ACCESS_ERR: APB_WRGMD Mask */ 1045 #define PKC_ACCESS_ERR_RESERVED0_Pos 2 /*!< PKC_ACCESS_ERR: RESERVED0 Position */ 1046 #define PKC_ACCESS_ERR_RESERVED0_Msk (0x03UL << PKC_ACCESS_ERR_RESERVED0_Pos) /*!< PKC_ACCESS_ERR: RESERVED0 Mask */ 1047 #define PKC_ACCESS_ERR_APB_MASTER_Pos 4 /*!< PKC_ACCESS_ERR: APB_MASTER Position */ 1048 #define PKC_ACCESS_ERR_APB_MASTER_Msk (0x0fUL << PKC_ACCESS_ERR_APB_MASTER_Pos) /*!< PKC_ACCESS_ERR: APB_MASTER Mask */ 1049 #define PKC_ACCESS_ERR_RESERVED1_Pos 8 /*!< PKC_ACCESS_ERR: RESERVED1 Position */ 1050 #define PKC_ACCESS_ERR_RESERVED1_Msk (0x03UL << PKC_ACCESS_ERR_RESERVED1_Pos) /*!< PKC_ACCESS_ERR: RESERVED1 Mask */ 1051 #define PKC_ACCESS_ERR_AHB_Pos 10 /*!< PKC_ACCESS_ERR: AHB Position */ 1052 #define PKC_ACCESS_ERR_AHB_Msk (0x01UL << PKC_ACCESS_ERR_AHB_Pos) /*!< PKC_ACCESS_ERR: AHB Mask */ 1053 #define PKC_ACCESS_ERR_RESERVED2_Pos 11 /*!< PKC_ACCESS_ERR: RESERVED2 Position */ 1054 #define PKC_ACCESS_ERR_RESERVED2_Msk (0x1fUL << PKC_ACCESS_ERR_RESERVED2_Pos) /*!< PKC_ACCESS_ERR: RESERVED2 Mask */ 1055 #define PKC_ACCESS_ERR_PKCC_Pos 16 /*!< PKC_ACCESS_ERR: PKCC Position */ 1056 #define PKC_ACCESS_ERR_PKCC_Msk (0x01UL << PKC_ACCESS_ERR_PKCC_Pos) /*!< PKC_ACCESS_ERR: PKCC Mask */ 1057 #define PKC_ACCESS_ERR_FDET_Pos 17 /*!< PKC_ACCESS_ERR: FDET Position */ 1058 #define PKC_ACCESS_ERR_FDET_Msk (0x01UL << PKC_ACCESS_ERR_FDET_Pos) /*!< PKC_ACCESS_ERR: FDET Mask */ 1059 #define PKC_ACCESS_ERR_CTRL_Pos 18 /*!< PKC_ACCESS_ERR: CTRL Position */ 1060 #define PKC_ACCESS_ERR_CTRL_Msk (0x01UL << PKC_ACCESS_ERR_CTRL_Pos) /*!< PKC_ACCESS_ERR: CTRL Mask */ 1061 #define PKC_ACCESS_ERR_UCRC_Pos 19 /*!< PKC_ACCESS_ERR: UCRC Position */ 1062 #define PKC_ACCESS_ERR_UCRC_Msk (0x01UL << PKC_ACCESS_ERR_UCRC_Pos) /*!< PKC_ACCESS_ERR: UCRC Mask */ 1063 #define PKC_ACCESS_ERR_RESERVED3_Pos 20 /*!< PKC_ACCESS_ERR: RESERVED3 Position */ 1064 #define PKC_ACCESS_ERR_RESERVED3_Msk (0x01UL << PKC_ACCESS_ERR_RESERVED3_Pos) /*!< PKC_ACCESS_ERR: RESERVED3 Mask */ 1065 #define PKC_ACCESS_ERR_RESERVED4_Pos 21 /*!< PKC_ACCESS_ERR: RESERVED4 Position */ 1066 #define PKC_ACCESS_ERR_RESERVED4_Msk (0x000007ffUL << PKC_ACCESS_ERR_RESERVED4_Pos) /*!< PKC_ACCESS_ERR: RESERVED4 Mask */ 1067 1068 /* =============================== PKC_ACCESS_ERR_CLR ============================== */ 1069 #define PKC_ACCESS_ERR_CLR_ERR_CLR_Pos 0 /*!< PKC_ACCESS_ERR_CLR: ERR_CLR Position */ 1070 #define PKC_ACCESS_ERR_CLR_ERR_CLR_Msk (0x01UL << PKC_ACCESS_ERR_CLR_ERR_CLR_Pos) /*!< PKC_ACCESS_ERR_CLR: ERR_CLR Mask */ 1071 #define PKC_ACCESS_ERR_CLR_RESERVED_Pos 1 /*!< PKC_ACCESS_ERR_CLR: RESERVED Position */ 1072 #define PKC_ACCESS_ERR_CLR_RESERVED_Msk (0x7fffffffUL << PKC_ACCESS_ERR_CLR_RESERVED_Pos) /*!< PKC_ACCESS_ERR_CLR: RESERVED Mask */ 1073 1074 /* =============================== PKC_INT_CLR_ENABLE ============================== */ 1075 #define PKC_INT_CLR_ENABLE_EN_PDONE_Pos 0 /*!< PKC_INT_CLR_ENABLE: EN_PDONE Position */ 1076 #define PKC_INT_CLR_ENABLE_EN_PDONE_Msk (0x01UL << PKC_INT_CLR_ENABLE_EN_PDONE_Pos) /*!< PKC_INT_CLR_ENABLE: EN_PDONE Mask */ 1077 #define PKC_INT_CLR_ENABLE_RESERVED0_Pos 1 /*!< PKC_INT_CLR_ENABLE: RESERVED0 Position */ 1078 #define PKC_INT_CLR_ENABLE_RESERVED0_Msk (0x01UL << PKC_INT_CLR_ENABLE_RESERVED0_Pos) /*!< PKC_INT_CLR_ENABLE: RESERVED0 Mask */ 1079 #define PKC_INT_CLR_ENABLE_RESERVED1_Pos 2 /*!< PKC_INT_CLR_ENABLE: RESERVED1 Position */ 1080 #define PKC_INT_CLR_ENABLE_RESERVED1_Msk (0x3fffffffUL << PKC_INT_CLR_ENABLE_RESERVED1_Pos) /*!< PKC_INT_CLR_ENABLE: RESERVED1 Mask */ 1081 1082 /* =============================== PKC_INT_SET_ENABLE ============================== */ 1083 #define PKC_INT_SET_ENABLE_EN_PDONE_Pos 0 /*!< PKC_INT_SET_ENABLE: EN_PDONE Position */ 1084 #define PKC_INT_SET_ENABLE_EN_PDONE_Msk (0x01UL << PKC_INT_SET_ENABLE_EN_PDONE_Pos) /*!< PKC_INT_SET_ENABLE: EN_PDONE Mask */ 1085 #define PKC_INT_SET_ENABLE_RESERVED0_Pos 1 /*!< PKC_INT_SET_ENABLE: RESERVED0 Position */ 1086 #define PKC_INT_SET_ENABLE_RESERVED0_Msk (0x01UL << PKC_INT_SET_ENABLE_RESERVED0_Pos) /*!< PKC_INT_SET_ENABLE: RESERVED0 Mask */ 1087 #define PKC_INT_SET_ENABLE_RESERVED1_Pos 2 /*!< PKC_INT_SET_ENABLE: RESERVED1 Position */ 1088 #define PKC_INT_SET_ENABLE_RESERVED1_Msk (0x3fffffffUL << PKC_INT_SET_ENABLE_RESERVED1_Pos) /*!< PKC_INT_SET_ENABLE: RESERVED1 Mask */ 1089 1090 /* =============================== PKC_INT_STATUS ============================== */ 1091 #define PKC_INT_STATUS_INT_PDONE_Pos 0 /*!< PKC_INT_STATUS: INT_PDONE Position */ 1092 #define PKC_INT_STATUS_INT_PDONE_Msk (0x01UL << PKC_INT_STATUS_INT_PDONE_Pos) /*!< PKC_INT_STATUS: INT_PDONE Mask */ 1093 #define PKC_INT_STATUS_RESERVED0_Pos 1 /*!< PKC_INT_STATUS: RESERVED0 Position */ 1094 #define PKC_INT_STATUS_RESERVED0_Msk (0x01UL << PKC_INT_STATUS_RESERVED0_Pos) /*!< PKC_INT_STATUS: RESERVED0 Mask */ 1095 #define PKC_INT_STATUS_RESERVED1_Pos 2 /*!< PKC_INT_STATUS: RESERVED1 Position */ 1096 #define PKC_INT_STATUS_RESERVED1_Msk (0x3fffffffUL << PKC_INT_STATUS_RESERVED1_Pos) /*!< PKC_INT_STATUS: RESERVED1 Mask */ 1097 1098 /* =============================== PKC_INT_ENABLE ============================== */ 1099 #define PKC_INT_ENABLE_EN_PDONE_Pos 0 /*!< PKC_INT_ENABLE: EN_PDONE Position */ 1100 #define PKC_INT_ENABLE_EN_PDONE_Msk (0x01UL << PKC_INT_ENABLE_EN_PDONE_Pos) /*!< PKC_INT_ENABLE: EN_PDONE Mask */ 1101 #define PKC_INT_ENABLE_RESERVED0_Pos 1 /*!< PKC_INT_ENABLE: RESERVED0 Position */ 1102 #define PKC_INT_ENABLE_RESERVED0_Msk (0x01UL << PKC_INT_ENABLE_RESERVED0_Pos) /*!< PKC_INT_ENABLE: RESERVED0 Mask */ 1103 #define PKC_INT_ENABLE_RESERVED1_Pos 2 /*!< PKC_INT_ENABLE: RESERVED1 Position */ 1104 #define PKC_INT_ENABLE_RESERVED1_Msk (0x3fffffffUL << PKC_INT_ENABLE_RESERVED1_Pos) /*!< PKC_INT_ENABLE: RESERVED1 Mask */ 1105 1106 /* =============================== PKC_INT_CLR_STATUS ============================== */ 1107 #define PKC_INT_CLR_STATUS_INT_PDONE_Pos 0 /*!< PKC_INT_CLR_STATUS: INT_PDONE Position */ 1108 #define PKC_INT_CLR_STATUS_INT_PDONE_Msk (0x01UL << PKC_INT_CLR_STATUS_INT_PDONE_Pos) /*!< PKC_INT_CLR_STATUS: INT_PDONE Mask */ 1109 #define PKC_INT_CLR_STATUS_RESERVED0_Pos 1 /*!< PKC_INT_CLR_STATUS: RESERVED0 Position */ 1110 #define PKC_INT_CLR_STATUS_RESERVED0_Msk (0x01UL << PKC_INT_CLR_STATUS_RESERVED0_Pos) /*!< PKC_INT_CLR_STATUS: RESERVED0 Mask */ 1111 #define PKC_INT_CLR_STATUS_RESERVED1_Pos 2 /*!< PKC_INT_CLR_STATUS: RESERVED1 Position */ 1112 #define PKC_INT_CLR_STATUS_RESERVED1_Msk (0x3fffffffUL << PKC_INT_CLR_STATUS_RESERVED1_Pos) /*!< PKC_INT_CLR_STATUS: RESERVED1 Mask */ 1113 1114 /* =============================== PKC_INT_SET_STATUS ============================== */ 1115 #define PKC_INT_SET_STATUS_INT_PDONE_Pos 0 /*!< PKC_INT_SET_STATUS: INT_PDONE Position */ 1116 #define PKC_INT_SET_STATUS_INT_PDONE_Msk (0x01UL << PKC_INT_SET_STATUS_INT_PDONE_Pos) /*!< PKC_INT_SET_STATUS: INT_PDONE Mask */ 1117 #define PKC_INT_SET_STATUS_RESERVED0_Pos 1 /*!< PKC_INT_SET_STATUS: RESERVED0 Position */ 1118 #define PKC_INT_SET_STATUS_RESERVED0_Msk (0x01UL << PKC_INT_SET_STATUS_RESERVED0_Pos) /*!< PKC_INT_SET_STATUS: RESERVED0 Mask */ 1119 #define PKC_INT_SET_STATUS_RESERVED1_Pos 2 /*!< PKC_INT_SET_STATUS: RESERVED1 Position */ 1120 #define PKC_INT_SET_STATUS_RESERVED1_Msk (0x3fffffffUL << PKC_INT_SET_STATUS_RESERVED1_Pos) /*!< PKC_INT_SET_STATUS: RESERVED1 Mask */ 1121 1122 /* =============================== PKC_MODULE_ID ============================== */ 1123 #define PKC_MODULE_ID_SIZE_Pos 0 /*!< PKC_MODULE_ID: SIZE Position */ 1124 #define PKC_MODULE_ID_SIZE_Msk (0x000000ffUL << PKC_MODULE_ID_SIZE_Pos) /*!< PKC_MODULE_ID: SIZE Mask */ 1125 #define PKC_MODULE_ID_MINOR_REV_Pos 8 /*!< PKC_MODULE_ID: MINOR_REV Position */ 1126 #define PKC_MODULE_ID_MINOR_REV_Msk (0x0fUL << PKC_MODULE_ID_MINOR_REV_Pos) /*!< PKC_MODULE_ID: MINOR_REV Mask */ 1127 #define PKC_MODULE_ID_MAJOR_REV_Pos 12 /*!< PKC_MODULE_ID: MAJOR_REV Position */ 1128 #define PKC_MODULE_ID_MAJOR_REV_Msk (0x0fUL << PKC_MODULE_ID_MAJOR_REV_Pos) /*!< PKC_MODULE_ID: MAJOR_REV Mask */ 1129 #define PKC_MODULE_ID_ID_Pos 16 /*!< PKC_MODULE_ID: ID Position */ 1130 #define PKC_MODULE_ID_ID_Msk (0x0000ffffUL << PKC_MODULE_ID_ID_Pos) /*!< PKC_MODULE_ID: ID Mask */ 1131 1132 1133 1134 /* ================================================================================ */ 1135 /* ================ Peripheral memory map ================ */ 1136 /* ================================================================================ */ 1137 1138 //#define PKC_BASE 0x50031000UL 1139 1140 1141 /* ================================================================================ */ 1142 /* ================ Peripheral declaration ================ */ 1143 /* ================================================================================ */ 1144 1145 //#define PKC ((PKC_Type *) PKC_BASE) 1146 1147 1148 /** @} */ /* End of group Device_Peripheral_Registers */ 1149 /** @} */ /* End of group CoSimPKC */ 1150 /** @} */ /* End of group (null) */ 1151 1152 #ifdef __cplusplus 1153 } 1154 #endif 1155 1156 1157 #endif /* CoSimPKC_H */ 1158
