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Searched refs:PHY_CTL1_SPEEDUPLX_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/components/phy/device/phyksz8081/
Dfsl_phyksz8081.c33 #define PHY_CTL1_SPEEDUPLX_MASK ((uint16_t)0x0007U) /*!< The PHY speed and duplex mask. */ macro
227 flag = regValue & PHY_CTL1_SPEEDUPLX_MASK; in PHY_KSZ8081_GetLinkSpeedDuplex()
240 flag = regValue & PHY_CTL1_SPEEDUPLX_MASK; in PHY_KSZ8081_GetLinkSpeedDuplex()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/phyksz8081/
Dfsl_phy.c276 data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; in PHY_GetLinkSpeedDuplex()
288 data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; in PHY_GetLinkSpeedDuplex()
Dfsl_phy.h52 #define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ macro