MUX_DIV_TRIG_CTRL (reference) in projects: hal_nxp-3.5.0

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Searched refs:MUX_DIV_TRIG_CTRL (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_DividerTrigger.c	`133 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 137 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()`
D	Clock_Ip_Divider.c	`231 …if ((Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_M… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_DividerTrigger.c	`138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() 142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()`
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
D	Clock_Ip_Specific.h	`212 uint32 MUX_DIV_TRIG_CTRL; /*< Clock Divider trigger Control Register / member`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
D	Clock_Ip_Specific.h	`366 …uint32 MUX_DIV_TRIG_CTRL; /**< Clock Mux 0 Divider Trigger Control Register, offset:… member`

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TraceRecorderSource-3.4.0
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