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Searched refs:MSTATUS (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.h812 return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK); in I3C_MasterGetStatusFlags()
835 base->MSTATUS = statusMask; in I3C_MasterClearStatusFlags()
1057 …return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); in I3C_MasterGetBusIdleState()
1255 return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT); in I3C_GetIBIAddress()
Dfsl_i3c.c719 … uint32_t ibiValue = (base->MSTATUS & I3C_MSTATUS_IBITYPE_MASK) >> I3C_MSTATUS_IBITYPE_SHIFT; in I3C_GetIBIType()
958 uint32_t masterState = (base->MSTATUS & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; in I3C_MasterGetState()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h107 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10494 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
DMIMXRT685S_cm33.h17378 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h17378 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h20823 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19794 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
DMIMXRT595S_cm33.h26753 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h20823 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26749 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h25624 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h26752 __IO uint32_t MSTATUS; /**< Master Status Register, offset: 0x88 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h40891 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member
DMIMX9352_ca55.h36181 __IO uint32_t MSTATUS; /**< Master Status, offset: 0x88 */ member