1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MSCM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MSCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MSCM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MSCM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MSCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MSCM - Size of Registers Arrays */ 72 #define MSCM_IRSPRC_COUNT 240u 73 74 /** MSCM - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t CPXTYPE; /**< Processor X Type, offset: 0x0 */ 77 __I uint32_t CPXNUM; /**< Processor X Number, offset: 0x4 */ 78 __I uint32_t CPXREV; /**< Processor X Revision, offset: 0x8 */ 79 __I uint32_t CPXCFG0; /**< Processor X Configuration 0, offset: 0xC */ 80 __I uint32_t CPXCFG1; /**< Processor X Configuration 1, offset: 0x10 */ 81 __I uint32_t CPXCFG2; /**< Processor X Configuration 2, offset: 0x14 */ 82 __I uint32_t CPXCFG3; /**< Processor x Configuration 3, offset: 0x18 */ 83 uint8_t RESERVED_0[4]; 84 __I uint32_t CP0TYPE; /**< Processor 0 Type, offset: 0x20 */ 85 __I uint32_t CP0NUM; /**< Processor 0 Number, offset: 0x24 */ 86 __I uint32_t CP0REV; /**< Processor 0 Count, offset: 0x28 */ 87 __I uint32_t CP0CFG0; /**< Processor 0 Configuration 0, offset: 0x2C */ 88 __I uint32_t CP0CFG1; /**< Processor 0 Configuration 1, offset: 0x30 */ 89 __I uint32_t CP0CFG2; /**< Processor 0 Configuration 2, offset: 0x34 */ 90 __I uint32_t CP0CFG3; /**< Processor 0 Configuration 3, offset: 0x38 */ 91 uint8_t RESERVED_1[452]; 92 __IO uint32_t IRCP0ISR0; /**< Interrupt Router CP0 Interrupt Status, offset: 0x200 */ 93 __O uint32_t IRCP0IGR0; /**< Interrupt Router CP0 Interrupt Generation, offset: 0x204 */ 94 __IO uint32_t IRCP0ISR1; /**< Interrupt Router CP0 Interrupt Status, offset: 0x208 */ 95 __O uint32_t IRCP0IGR1; /**< Interrupt Router CP0 Interrupt Generation, offset: 0x20C */ 96 __IO uint32_t IRCP0ISR2; /**< Interrupt Router CP0 Interrupt Status, offset: 0x210 */ 97 __O uint32_t IRCP0IGR2; /**< Interrupt Router CP0 Interrupt Generation, offset: 0x214 */ 98 __IO uint32_t IRCP0ISR3; /**< Interrupt Router CP0 Interrupt Status, offset: 0x218 */ 99 __O uint32_t IRCP0IGR3; /**< Interrupt Router CP0 Interrupt Generation, offset: 0x21C */ 100 __IO uint32_t IRCP1ISR0; /**< Interrupt Router CP1 Interrupt Status, offset: 0x220 */ 101 __O uint32_t IRCP1IGR0; /**< Interrupt Router CP1 Interrupt Generation, offset: 0x224 */ 102 __IO uint32_t IRCP1ISR1; /**< Interrupt Router CP1 Interrupt Status, offset: 0x228 */ 103 __O uint32_t IRCP1IGR1; /**< Interrupt Router CP1 Interrupt Generation, offset: 0x22C */ 104 __IO uint32_t IRCP1ISR2; /**< Interrupt Router CP1 Interrupt Status, offset: 0x230 */ 105 __O uint32_t IRCP1IGR2; /**< Interrupt Router CP1 Interrupt Generation, offset: 0x234 */ 106 __IO uint32_t IRCP1ISR3; /**< Interrupt Router CP1 Interrupt Status, offset: 0x238 */ 107 __O uint32_t IRCP1IGR3; /**< Interrupt Router CP1 Interrupt Generation, offset: 0x23C */ 108 uint8_t RESERVED_2[448]; 109 __IO uint32_t IRCPCFG; /**< Interrupt Router Configuration, offset: 0x400 */ 110 uint8_t RESERVED_3[508]; 111 __IO uint32_t ENEDC; /**< Enable Interconnect Error Detection, offset: 0x600 */ 112 uint8_t RESERVED_4[252]; 113 __IO uint32_t IAHBCFGREG; /**< AHB Gasket Configuration, offset: 0x700 */ 114 uint8_t RESERVED_5[380]; 115 __IO uint16_t IRSPRC[MSCM_IRSPRC_COUNT]; /**< Interrupt Router Shared Peripheral Routing Control, array offset: 0x880, array step: 0x2 */ 116 } MSCM_Type, *MSCM_MemMapPtr; 117 118 /** Number of instances of the MSCM module. */ 119 #define MSCM_INSTANCE_COUNT (1u) 120 121 /* MSCM - Peripheral instance base addresses */ 122 /** Peripheral MSCM base address */ 123 #define IP_MSCM_BASE (0x40260000u) 124 /** Peripheral MSCM base pointer */ 125 #define IP_MSCM ((MSCM_Type *)IP_MSCM_BASE) 126 /** Array initializer of MSCM peripheral base addresses */ 127 #define IP_MSCM_BASE_ADDRS { IP_MSCM_BASE } 128 /** Array initializer of MSCM peripheral base pointers */ 129 #define IP_MSCM_BASE_PTRS { IP_MSCM } 130 131 /* ---------------------------------------------------------------------------- 132 -- MSCM Register Masks 133 ---------------------------------------------------------------------------- */ 134 135 /*! 136 * @addtogroup MSCM_Register_Masks MSCM Register Masks 137 * @{ 138 */ 139 140 /*! @name CPXTYPE - Processor X Type */ 141 /*! @{ */ 142 143 #define MSCM_CPXTYPE_PERSONALITY_MASK (0xFFFFFFFFU) 144 #define MSCM_CPXTYPE_PERSONALITY_SHIFT (0U) 145 #define MSCM_CPXTYPE_PERSONALITY_WIDTH (32U) 146 #define MSCM_CPXTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK) 147 /*! @} */ 148 149 /*! @name CPXNUM - Processor X Number */ 150 /*! @{ */ 151 152 #define MSCM_CPXNUM_CPN_MASK (0x3U) 153 #define MSCM_CPXNUM_CPN_SHIFT (0U) 154 #define MSCM_CPXNUM_CPN_WIDTH (2U) 155 #define MSCM_CPXNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK) 156 /*! @} */ 157 158 /*! @name CPXREV - Processor X Revision */ 159 /*! @{ */ 160 161 #define MSCM_CPXREV_RYPZ_MASK (0xFFU) 162 #define MSCM_CPXREV_RYPZ_SHIFT (0U) 163 #define MSCM_CPXREV_RYPZ_WIDTH (8U) 164 #define MSCM_CPXREV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXREV_RYPZ_SHIFT)) & MSCM_CPXREV_RYPZ_MASK) 165 /*! @} */ 166 167 /*! @name CPXCFG0 - Processor X Configuration 0 */ 168 /*! @{ */ 169 170 #define MSCM_CPXCFG0_DCWY_MASK (0xFFU) 171 #define MSCM_CPXCFG0_DCWY_SHIFT (0U) 172 #define MSCM_CPXCFG0_DCWY_WIDTH (8U) 173 #define MSCM_CPXCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK) 174 175 #define MSCM_CPXCFG0_DCSZ_MASK (0xFF00U) 176 #define MSCM_CPXCFG0_DCSZ_SHIFT (8U) 177 #define MSCM_CPXCFG0_DCSZ_WIDTH (8U) 178 #define MSCM_CPXCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK) 179 180 #define MSCM_CPXCFG0_ICWY_MASK (0xFF0000U) 181 #define MSCM_CPXCFG0_ICWY_SHIFT (16U) 182 #define MSCM_CPXCFG0_ICWY_WIDTH (8U) 183 #define MSCM_CPXCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK) 184 185 #define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) 186 #define MSCM_CPXCFG0_ICSZ_SHIFT (24U) 187 #define MSCM_CPXCFG0_ICSZ_WIDTH (8U) 188 #define MSCM_CPXCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK) 189 /*! @} */ 190 191 /*! @name CPXCFG1 - Processor X Configuration 1 */ 192 /*! @{ */ 193 194 #define MSCM_CPXCFG1_L2WY_MASK (0xFF0000U) 195 #define MSCM_CPXCFG1_L2WY_SHIFT (16U) 196 #define MSCM_CPXCFG1_L2WY_WIDTH (8U) 197 #define MSCM_CPXCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK) 198 199 #define MSCM_CPXCFG1_L2SZ_MASK (0xFF000000U) 200 #define MSCM_CPXCFG1_L2SZ_SHIFT (24U) 201 #define MSCM_CPXCFG1_L2SZ_WIDTH (8U) 202 #define MSCM_CPXCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK) 203 /*! @} */ 204 205 /*! @name CPXCFG2 - Processor X Configuration 2 */ 206 /*! @{ */ 207 208 #define MSCM_CPXCFG2_ITCMSZ_MASK (0xFF0000U) 209 #define MSCM_CPXCFG2_ITCMSZ_SHIFT (16U) 210 #define MSCM_CPXCFG2_ITCMSZ_WIDTH (8U) 211 #define MSCM_CPXCFG2_ITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_ITCMSZ_SHIFT)) & MSCM_CPXCFG2_ITCMSZ_MASK) 212 213 #define MSCM_CPXCFG2_DTCMSZ_MASK (0xFF000000U) 214 #define MSCM_CPXCFG2_DTCMSZ_SHIFT (24U) 215 #define MSCM_CPXCFG2_DTCMSZ_WIDTH (8U) 216 #define MSCM_CPXCFG2_DTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_DTCMSZ_SHIFT)) & MSCM_CPXCFG2_DTCMSZ_MASK) 217 /*! @} */ 218 219 /*! @name CPXCFG3 - Processor x Configuration 3 */ 220 /*! @{ */ 221 222 #define MSCM_CPXCFG3_FPU_MASK (0x1U) 223 #define MSCM_CPXCFG3_FPU_SHIFT (0U) 224 #define MSCM_CPXCFG3_FPU_WIDTH (1U) 225 #define MSCM_CPXCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK) 226 227 #define MSCM_CPXCFG3_SIMD_MASK (0x2U) 228 #define MSCM_CPXCFG3_SIMD_SHIFT (1U) 229 #define MSCM_CPXCFG3_SIMD_WIDTH (1U) 230 #define MSCM_CPXCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK) 231 232 #define MSCM_CPXCFG3_MMU_MASK (0x4U) 233 #define MSCM_CPXCFG3_MMU_SHIFT (2U) 234 #define MSCM_CPXCFG3_MMU_WIDTH (1U) 235 #define MSCM_CPXCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK) 236 237 #define MSCM_CPXCFG3_CMP_MASK (0x8U) 238 #define MSCM_CPXCFG3_CMP_SHIFT (3U) 239 #define MSCM_CPXCFG3_CMP_WIDTH (1U) 240 #define MSCM_CPXCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK) 241 242 #define MSCM_CPXCFG3_CPY_MASK (0x10U) 243 #define MSCM_CPXCFG3_CPY_SHIFT (4U) 244 #define MSCM_CPXCFG3_CPY_WIDTH (1U) 245 #define MSCM_CPXCFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CPY_SHIFT)) & MSCM_CPXCFG3_CPY_MASK) 246 /*! @} */ 247 248 /*! @name CP0TYPE - Processor 0 Type */ 249 /*! @{ */ 250 251 #define MSCM_CP0TYPE_PERSONALITY_MASK (0xFFFFFFFFU) 252 #define MSCM_CP0TYPE_PERSONALITY_SHIFT (0U) 253 #define MSCM_CP0TYPE_PERSONALITY_WIDTH (32U) 254 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_PERSONALITY_SHIFT)) & MSCM_CP0TYPE_PERSONALITY_MASK) 255 /*! @} */ 256 257 /*! @name CP0NUM - Processor 0 Number */ 258 /*! @{ */ 259 260 #define MSCM_CP0NUM_CPN_MASK (0x3U) 261 #define MSCM_CP0NUM_CPN_SHIFT (0U) 262 #define MSCM_CP0NUM_CPN_WIDTH (2U) 263 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0NUM_CPN_SHIFT)) & MSCM_CP0NUM_CPN_MASK) 264 /*! @} */ 265 266 /*! @name CP0REV - Processor 0 Count */ 267 /*! @{ */ 268 269 #define MSCM_CP0REV_RYPZ_MASK (0xFFU) 270 #define MSCM_CP0REV_RYPZ_SHIFT (0U) 271 #define MSCM_CP0REV_RYPZ_WIDTH (8U) 272 #define MSCM_CP0REV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0REV_RYPZ_SHIFT)) & MSCM_CP0REV_RYPZ_MASK) 273 /*! @} */ 274 275 /*! @name CP0CFG0 - Processor 0 Configuration 0 */ 276 /*! @{ */ 277 278 #define MSCM_CP0CFG0_DCWY_MASK (0xFFU) 279 #define MSCM_CP0CFG0_DCWY_SHIFT (0U) 280 #define MSCM_CP0CFG0_DCWY_WIDTH (8U) 281 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCWY_SHIFT)) & MSCM_CP0CFG0_DCWY_MASK) 282 283 #define MSCM_CP0CFG0_DCSZ_MASK (0xFF00U) 284 #define MSCM_CP0CFG0_DCSZ_SHIFT (8U) 285 #define MSCM_CP0CFG0_DCSZ_WIDTH (8U) 286 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCSZ_SHIFT)) & MSCM_CP0CFG0_DCSZ_MASK) 287 288 #define MSCM_CP0CFG0_ICWY_MASK (0xFF0000U) 289 #define MSCM_CP0CFG0_ICWY_SHIFT (16U) 290 #define MSCM_CP0CFG0_ICWY_WIDTH (8U) 291 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICWY_SHIFT)) & MSCM_CP0CFG0_ICWY_MASK) 292 293 #define MSCM_CP0CFG0_ICSZ_MASK (0xFF000000U) 294 #define MSCM_CP0CFG0_ICSZ_SHIFT (24U) 295 #define MSCM_CP0CFG0_ICSZ_WIDTH (8U) 296 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICSZ_SHIFT)) & MSCM_CP0CFG0_ICSZ_MASK) 297 /*! @} */ 298 299 /*! @name CP0CFG1 - Processor 0 Configuration 1 */ 300 /*! @{ */ 301 302 #define MSCM_CP0CFG1_L2WY_MASK (0xFF0000U) 303 #define MSCM_CP0CFG1_L2WY_SHIFT (16U) 304 #define MSCM_CP0CFG1_L2WY_WIDTH (8U) 305 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2WY_SHIFT)) & MSCM_CP0CFG1_L2WY_MASK) 306 307 #define MSCM_CP0CFG1_L2SZ_MASK (0xFF000000U) 308 #define MSCM_CP0CFG1_L2SZ_SHIFT (24U) 309 #define MSCM_CP0CFG1_L2SZ_WIDTH (8U) 310 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2SZ_SHIFT)) & MSCM_CP0CFG1_L2SZ_MASK) 311 /*! @} */ 312 313 /*! @name CP0CFG2 - Processor 0 Configuration 2 */ 314 /*! @{ */ 315 316 #define MSCM_CP0CFG2_ITCMSZ_MASK (0xFF0000U) 317 #define MSCM_CP0CFG2_ITCMSZ_SHIFT (16U) 318 #define MSCM_CP0CFG2_ITCMSZ_WIDTH (8U) 319 #define MSCM_CP0CFG2_ITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_ITCMSZ_SHIFT)) & MSCM_CP0CFG2_ITCMSZ_MASK) 320 321 #define MSCM_CP0CFG2_DTCMSZ_MASK (0xFF000000U) 322 #define MSCM_CP0CFG2_DTCMSZ_SHIFT (24U) 323 #define MSCM_CP0CFG2_DTCMSZ_WIDTH (8U) 324 #define MSCM_CP0CFG2_DTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_DTCMSZ_SHIFT)) & MSCM_CP0CFG2_DTCMSZ_MASK) 325 /*! @} */ 326 327 /*! @name CP0CFG3 - Processor 0 Configuration 3 */ 328 /*! @{ */ 329 330 #define MSCM_CP0CFG3_FPU_MASK (0x1U) 331 #define MSCM_CP0CFG3_FPU_SHIFT (0U) 332 #define MSCM_CP0CFG3_FPU_WIDTH (1U) 333 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_FPU_SHIFT)) & MSCM_CP0CFG3_FPU_MASK) 334 335 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) 336 #define MSCM_CP0CFG3_SIMD_SHIFT (1U) 337 #define MSCM_CP0CFG3_SIMD_WIDTH (1U) 338 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK) 339 340 #define MSCM_CP0CFG3_MMU_MASK (0x4U) 341 #define MSCM_CP0CFG3_MMU_SHIFT (2U) 342 #define MSCM_CP0CFG3_MMU_WIDTH (1U) 343 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_MMU_SHIFT)) & MSCM_CP0CFG3_MMU_MASK) 344 345 #define MSCM_CP0CFG3_CMP_MASK (0x8U) 346 #define MSCM_CP0CFG3_CMP_SHIFT (3U) 347 #define MSCM_CP0CFG3_CMP_WIDTH (1U) 348 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CMP_SHIFT)) & MSCM_CP0CFG3_CMP_MASK) 349 350 #define MSCM_CP0CFG3_CPY_MASK (0x10U) 351 #define MSCM_CP0CFG3_CPY_SHIFT (4U) 352 #define MSCM_CP0CFG3_CPY_WIDTH (1U) 353 #define MSCM_CP0CFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CPY_SHIFT)) & MSCM_CP0CFG3_CPY_MASK) 354 /*! @} */ 355 356 /*! @name IRCP0ISR0 - Interrupt Router CP0 Interrupt Status */ 357 /*! @{ */ 358 359 #define MSCM_IRCP0ISR0_CP0_INT_MASK (0x1U) 360 #define MSCM_IRCP0ISR0_CP0_INT_SHIFT (0U) 361 #define MSCM_IRCP0ISR0_CP0_INT_WIDTH (1U) 362 #define MSCM_IRCP0ISR0_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0ISR0_CP0_INT_SHIFT)) & MSCM_IRCP0ISR0_CP0_INT_MASK) 363 /*! @} */ 364 365 /*! @name IRCP0IGR0 - Interrupt Router CP0 Interrupt Generation */ 366 /*! @{ */ 367 368 #define MSCM_IRCP0IGR0_INT_EN_MASK (0x1U) 369 #define MSCM_IRCP0IGR0_INT_EN_SHIFT (0U) 370 #define MSCM_IRCP0IGR0_INT_EN_WIDTH (1U) 371 #define MSCM_IRCP0IGR0_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0IGR0_INT_EN_SHIFT)) & MSCM_IRCP0IGR0_INT_EN_MASK) 372 /*! @} */ 373 374 /*! @name IRCP0ISR1 - Interrupt Router CP0 Interrupt Status */ 375 /*! @{ */ 376 377 #define MSCM_IRCP0ISR1_CP0_INT_MASK (0x1U) 378 #define MSCM_IRCP0ISR1_CP0_INT_SHIFT (0U) 379 #define MSCM_IRCP0ISR1_CP0_INT_WIDTH (1U) 380 #define MSCM_IRCP0ISR1_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0ISR1_CP0_INT_SHIFT)) & MSCM_IRCP0ISR1_CP0_INT_MASK) 381 /*! @} */ 382 383 /*! @name IRCP0IGR1 - Interrupt Router CP0 Interrupt Generation */ 384 /*! @{ */ 385 386 #define MSCM_IRCP0IGR1_INT_EN_MASK (0x1U) 387 #define MSCM_IRCP0IGR1_INT_EN_SHIFT (0U) 388 #define MSCM_IRCP0IGR1_INT_EN_WIDTH (1U) 389 #define MSCM_IRCP0IGR1_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0IGR1_INT_EN_SHIFT)) & MSCM_IRCP0IGR1_INT_EN_MASK) 390 /*! @} */ 391 392 /*! @name IRCP0ISR2 - Interrupt Router CP0 Interrupt Status */ 393 /*! @{ */ 394 395 #define MSCM_IRCP0ISR2_CP0_INT_MASK (0x1U) 396 #define MSCM_IRCP0ISR2_CP0_INT_SHIFT (0U) 397 #define MSCM_IRCP0ISR2_CP0_INT_WIDTH (1U) 398 #define MSCM_IRCP0ISR2_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0ISR2_CP0_INT_SHIFT)) & MSCM_IRCP0ISR2_CP0_INT_MASK) 399 /*! @} */ 400 401 /*! @name IRCP0IGR2 - Interrupt Router CP0 Interrupt Generation */ 402 /*! @{ */ 403 404 #define MSCM_IRCP0IGR2_INT_EN_MASK (0x1U) 405 #define MSCM_IRCP0IGR2_INT_EN_SHIFT (0U) 406 #define MSCM_IRCP0IGR2_INT_EN_WIDTH (1U) 407 #define MSCM_IRCP0IGR2_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0IGR2_INT_EN_SHIFT)) & MSCM_IRCP0IGR2_INT_EN_MASK) 408 /*! @} */ 409 410 /*! @name IRCP0ISR3 - Interrupt Router CP0 Interrupt Status */ 411 /*! @{ */ 412 413 #define MSCM_IRCP0ISR3_CP0_INT_MASK (0x1U) 414 #define MSCM_IRCP0ISR3_CP0_INT_SHIFT (0U) 415 #define MSCM_IRCP0ISR3_CP0_INT_WIDTH (1U) 416 #define MSCM_IRCP0ISR3_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0ISR3_CP0_INT_SHIFT)) & MSCM_IRCP0ISR3_CP0_INT_MASK) 417 /*! @} */ 418 419 /*! @name IRCP0IGR3 - Interrupt Router CP0 Interrupt Generation */ 420 /*! @{ */ 421 422 #define MSCM_IRCP0IGR3_INT_EN_MASK (0x1U) 423 #define MSCM_IRCP0IGR3_INT_EN_SHIFT (0U) 424 #define MSCM_IRCP0IGR3_INT_EN_WIDTH (1U) 425 #define MSCM_IRCP0IGR3_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP0IGR3_INT_EN_SHIFT)) & MSCM_IRCP0IGR3_INT_EN_MASK) 426 /*! @} */ 427 428 /*! @name IRCP1ISR0 - Interrupt Router CP1 Interrupt Status */ 429 /*! @{ */ 430 431 #define MSCM_IRCP1ISR0_CP0_INT_MASK (0x1U) 432 #define MSCM_IRCP1ISR0_CP0_INT_SHIFT (0U) 433 #define MSCM_IRCP1ISR0_CP0_INT_WIDTH (1U) 434 #define MSCM_IRCP1ISR0_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1ISR0_CP0_INT_SHIFT)) & MSCM_IRCP1ISR0_CP0_INT_MASK) 435 /*! @} */ 436 437 /*! @name IRCP1IGR0 - Interrupt Router CP1 Interrupt Generation */ 438 /*! @{ */ 439 440 #define MSCM_IRCP1IGR0_INT_EN_MASK (0x1U) 441 #define MSCM_IRCP1IGR0_INT_EN_SHIFT (0U) 442 #define MSCM_IRCP1IGR0_INT_EN_WIDTH (1U) 443 #define MSCM_IRCP1IGR0_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1IGR0_INT_EN_SHIFT)) & MSCM_IRCP1IGR0_INT_EN_MASK) 444 /*! @} */ 445 446 /*! @name IRCP1ISR1 - Interrupt Router CP1 Interrupt Status */ 447 /*! @{ */ 448 449 #define MSCM_IRCP1ISR1_CP0_INT_MASK (0x1U) 450 #define MSCM_IRCP1ISR1_CP0_INT_SHIFT (0U) 451 #define MSCM_IRCP1ISR1_CP0_INT_WIDTH (1U) 452 #define MSCM_IRCP1ISR1_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1ISR1_CP0_INT_SHIFT)) & MSCM_IRCP1ISR1_CP0_INT_MASK) 453 /*! @} */ 454 455 /*! @name IRCP1IGR1 - Interrupt Router CP1 Interrupt Generation */ 456 /*! @{ */ 457 458 #define MSCM_IRCP1IGR1_INT_EN_MASK (0x1U) 459 #define MSCM_IRCP1IGR1_INT_EN_SHIFT (0U) 460 #define MSCM_IRCP1IGR1_INT_EN_WIDTH (1U) 461 #define MSCM_IRCP1IGR1_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1IGR1_INT_EN_SHIFT)) & MSCM_IRCP1IGR1_INT_EN_MASK) 462 /*! @} */ 463 464 /*! @name IRCP1ISR2 - Interrupt Router CP1 Interrupt Status */ 465 /*! @{ */ 466 467 #define MSCM_IRCP1ISR2_CP0_INT_MASK (0x1U) 468 #define MSCM_IRCP1ISR2_CP0_INT_SHIFT (0U) 469 #define MSCM_IRCP1ISR2_CP0_INT_WIDTH (1U) 470 #define MSCM_IRCP1ISR2_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1ISR2_CP0_INT_SHIFT)) & MSCM_IRCP1ISR2_CP0_INT_MASK) 471 /*! @} */ 472 473 /*! @name IRCP1IGR2 - Interrupt Router CP1 Interrupt Generation */ 474 /*! @{ */ 475 476 #define MSCM_IRCP1IGR2_INT_EN_MASK (0x1U) 477 #define MSCM_IRCP1IGR2_INT_EN_SHIFT (0U) 478 #define MSCM_IRCP1IGR2_INT_EN_WIDTH (1U) 479 #define MSCM_IRCP1IGR2_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1IGR2_INT_EN_SHIFT)) & MSCM_IRCP1IGR2_INT_EN_MASK) 480 /*! @} */ 481 482 /*! @name IRCP1ISR3 - Interrupt Router CP1 Interrupt Status */ 483 /*! @{ */ 484 485 #define MSCM_IRCP1ISR3_CP0_INT_MASK (0x1U) 486 #define MSCM_IRCP1ISR3_CP0_INT_SHIFT (0U) 487 #define MSCM_IRCP1ISR3_CP0_INT_WIDTH (1U) 488 #define MSCM_IRCP1ISR3_CP0_INT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1ISR3_CP0_INT_SHIFT)) & MSCM_IRCP1ISR3_CP0_INT_MASK) 489 /*! @} */ 490 491 /*! @name IRCP1IGR3 - Interrupt Router CP1 Interrupt Generation */ 492 /*! @{ */ 493 494 #define MSCM_IRCP1IGR3_INT_EN_MASK (0x1U) 495 #define MSCM_IRCP1IGR3_INT_EN_SHIFT (0U) 496 #define MSCM_IRCP1IGR3_INT_EN_WIDTH (1U) 497 #define MSCM_IRCP1IGR3_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCP1IGR3_INT_EN_SHIFT)) & MSCM_IRCP1IGR3_INT_EN_MASK) 498 /*! @} */ 499 500 /*! @name IRCPCFG - Interrupt Router Configuration */ 501 /*! @{ */ 502 503 #define MSCM_IRCPCFG_CP0_TR_MASK (0x1U) 504 #define MSCM_IRCPCFG_CP0_TR_SHIFT (0U) 505 #define MSCM_IRCPCFG_CP0_TR_WIDTH (1U) 506 #define MSCM_IRCPCFG_CP0_TR(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCPCFG_CP0_TR_SHIFT)) & MSCM_IRCPCFG_CP0_TR_MASK) 507 508 #define MSCM_IRCPCFG_LOCK_MASK (0x80000000U) 509 #define MSCM_IRCPCFG_LOCK_SHIFT (31U) 510 #define MSCM_IRCPCFG_LOCK_WIDTH (1U) 511 #define MSCM_IRCPCFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IRCPCFG_LOCK_SHIFT)) & MSCM_IRCPCFG_LOCK_MASK) 512 /*! @} */ 513 514 /*! @name ENEDC - Enable Interconnect Error Detection */ 515 /*! @{ */ 516 517 #define MSCM_ENEDC_EN_RD_CM7_0_AHBM_MASK (0x1U) 518 #define MSCM_ENEDC_EN_RD_CM7_0_AHBM_SHIFT (0U) 519 #define MSCM_ENEDC_EN_RD_CM7_0_AHBM_WIDTH (1U) 520 #define MSCM_ENEDC_EN_RD_CM7_0_AHBM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_CM7_0_AHBM_SHIFT)) & MSCM_ENEDC_EN_RD_CM7_0_AHBM_MASK) 521 522 #define MSCM_ENEDC_EN_RD_CM7_0_AHBP_MASK (0x2U) 523 #define MSCM_ENEDC_EN_RD_CM7_0_AHBP_SHIFT (1U) 524 #define MSCM_ENEDC_EN_RD_CM7_0_AHBP_WIDTH (1U) 525 #define MSCM_ENEDC_EN_RD_CM7_0_AHBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_CM7_0_AHBP_SHIFT)) & MSCM_ENEDC_EN_RD_CM7_0_AHBP_MASK) 526 527 #define MSCM_ENEDC_EN_RD_EDMA_MASK (0x4U) 528 #define MSCM_ENEDC_EN_RD_EDMA_SHIFT (2U) 529 #define MSCM_ENEDC_EN_RD_EDMA_WIDTH (1U) 530 #define MSCM_ENEDC_EN_RD_EDMA(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_EDMA_SHIFT)) & MSCM_ENEDC_EN_RD_EDMA_MASK) 531 532 #define MSCM_ENEDC_EN_RD_HSE_MASK (0x10U) 533 #define MSCM_ENEDC_EN_RD_HSE_SHIFT (4U) 534 #define MSCM_ENEDC_EN_RD_HSE_WIDTH (1U) 535 #define MSCM_ENEDC_EN_RD_HSE(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_HSE_SHIFT)) & MSCM_ENEDC_EN_RD_HSE_MASK) 536 537 #define MSCM_ENEDC_EN_RD_EMAC_MASK (0x20U) 538 #define MSCM_ENEDC_EN_RD_EMAC_SHIFT (5U) 539 #define MSCM_ENEDC_EN_RD_EMAC_WIDTH (1U) 540 #define MSCM_ENEDC_EN_RD_EMAC(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_EMAC_SHIFT)) & MSCM_ENEDC_EN_RD_EMAC_MASK) 541 542 #define MSCM_ENEDC_EN_RD_CM7_1_AHBM_MASK (0x40U) 543 #define MSCM_ENEDC_EN_RD_CM7_1_AHBM_SHIFT (6U) 544 #define MSCM_ENEDC_EN_RD_CM7_1_AHBM_WIDTH (1U) 545 #define MSCM_ENEDC_EN_RD_CM7_1_AHBM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_CM7_1_AHBM_SHIFT)) & MSCM_ENEDC_EN_RD_CM7_1_AHBM_MASK) 546 547 #define MSCM_ENEDC_EN_RD_CM7_1_AHBP_MASK (0x80U) 548 #define MSCM_ENEDC_EN_RD_CM7_1_AHBP_SHIFT (7U) 549 #define MSCM_ENEDC_EN_RD_CM7_1_AHBP_WIDTH (1U) 550 #define MSCM_ENEDC_EN_RD_CM7_1_AHBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_CM7_1_AHBP_SHIFT)) & MSCM_ENEDC_EN_RD_CM7_1_AHBP_MASK) 551 552 #define MSCM_ENEDC_EN_RD_TCM_MASK (0x100U) 553 #define MSCM_ENEDC_EN_RD_TCM_SHIFT (8U) 554 #define MSCM_ENEDC_EN_RD_TCM_WIDTH (1U) 555 #define MSCM_ENEDC_EN_RD_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_RD_TCM_SHIFT)) & MSCM_ENEDC_EN_RD_TCM_MASK) 556 557 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT0_MASK (0x200U) 558 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT0_SHIFT (9U) 559 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT0_WIDTH (1U) 560 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_PFLASH_PORT0_SHIFT)) & MSCM_ENEDC_EN_ADD_PFLASH_PORT0_MASK) 561 562 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT1_MASK (0x400U) 563 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT1_SHIFT (10U) 564 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT1_WIDTH (1U) 565 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_PFLASH_PORT1_SHIFT)) & MSCM_ENEDC_EN_ADD_PFLASH_PORT1_MASK) 566 567 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT2_MASK (0x800U) 568 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT2_SHIFT (11U) 569 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT2_WIDTH (1U) 570 #define MSCM_ENEDC_EN_ADD_PFLASH_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_PFLASH_PORT2_SHIFT)) & MSCM_ENEDC_EN_ADD_PFLASH_PORT2_MASK) 571 572 #define MSCM_ENEDC_EN_WR_PRAM0_MASK (0x1000U) 573 #define MSCM_ENEDC_EN_WR_PRAM0_SHIFT (12U) 574 #define MSCM_ENEDC_EN_WR_PRAM0_WIDTH (1U) 575 #define MSCM_ENEDC_EN_WR_PRAM0(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_PRAM0_SHIFT)) & MSCM_ENEDC_EN_WR_PRAM0_MASK) 576 577 #define MSCM_ENEDC_EN_ADD_PRAM0_MASK (0x2000U) 578 #define MSCM_ENEDC_EN_ADD_PRAM0_SHIFT (13U) 579 #define MSCM_ENEDC_EN_ADD_PRAM0_WIDTH (1U) 580 #define MSCM_ENEDC_EN_ADD_PRAM0(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_PRAM0_SHIFT)) & MSCM_ENEDC_EN_ADD_PRAM0_MASK) 581 582 #define MSCM_ENEDC_EN_WR_PRAM1_MASK (0x4000U) 583 #define MSCM_ENEDC_EN_WR_PRAM1_SHIFT (14U) 584 #define MSCM_ENEDC_EN_WR_PRAM1_WIDTH (1U) 585 #define MSCM_ENEDC_EN_WR_PRAM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_PRAM1_SHIFT)) & MSCM_ENEDC_EN_WR_PRAM1_MASK) 586 587 #define MSCM_ENEDC_EN_ADD_PRAM1_MASK (0x8000U) 588 #define MSCM_ENEDC_EN_ADD_PRAM1_SHIFT (15U) 589 #define MSCM_ENEDC_EN_ADD_PRAM1_WIDTH (1U) 590 #define MSCM_ENEDC_EN_ADD_PRAM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_PRAM1_SHIFT)) & MSCM_ENEDC_EN_ADD_PRAM1_MASK) 591 592 #define MSCM_ENEDC_EN_WR_TCM_MASK (0x10000U) 593 #define MSCM_ENEDC_EN_WR_TCM_SHIFT (16U) 594 #define MSCM_ENEDC_EN_WR_TCM_WIDTH (1U) 595 #define MSCM_ENEDC_EN_WR_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_TCM_SHIFT)) & MSCM_ENEDC_EN_WR_TCM_MASK) 596 597 #define MSCM_ENEDC_EN_ADD_TCM_MASK (0x20000U) 598 #define MSCM_ENEDC_EN_ADD_TCM_SHIFT (17U) 599 #define MSCM_ENEDC_EN_ADD_TCM_WIDTH (1U) 600 #define MSCM_ENEDC_EN_ADD_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_TCM_SHIFT)) & MSCM_ENEDC_EN_ADD_TCM_MASK) 601 602 #define MSCM_ENEDC_EN_ADD_QSPI_MASK (0x80000U) 603 #define MSCM_ENEDC_EN_ADD_QSPI_SHIFT (19U) 604 #define MSCM_ENEDC_EN_ADD_QSPI_WIDTH (1U) 605 #define MSCM_ENEDC_EN_ADD_QSPI(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_QSPI_SHIFT)) & MSCM_ENEDC_EN_ADD_QSPI_MASK) 606 607 #define MSCM_ENEDC_EN_WR_AIPS0_MASK (0x100000U) 608 #define MSCM_ENEDC_EN_WR_AIPS0_SHIFT (20U) 609 #define MSCM_ENEDC_EN_WR_AIPS0_WIDTH (1U) 610 #define MSCM_ENEDC_EN_WR_AIPS0(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_AIPS0_SHIFT)) & MSCM_ENEDC_EN_WR_AIPS0_MASK) 611 612 #define MSCM_ENEDC_EN_ADD_AIPS0_MASK (0x200000U) 613 #define MSCM_ENEDC_EN_ADD_AIPS0_SHIFT (21U) 614 #define MSCM_ENEDC_EN_ADD_AIPS0_WIDTH (1U) 615 #define MSCM_ENEDC_EN_ADD_AIPS0(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_AIPS0_SHIFT)) & MSCM_ENEDC_EN_ADD_AIPS0_MASK) 616 617 #define MSCM_ENEDC_EN_WR_AIPS1_MASK (0x400000U) 618 #define MSCM_ENEDC_EN_WR_AIPS1_SHIFT (22U) 619 #define MSCM_ENEDC_EN_WR_AIPS1_WIDTH (1U) 620 #define MSCM_ENEDC_EN_WR_AIPS1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_AIPS1_SHIFT)) & MSCM_ENEDC_EN_WR_AIPS1_MASK) 621 622 #define MSCM_ENEDC_EN_ADD_AIPS1_MASK (0x800000U) 623 #define MSCM_ENEDC_EN_ADD_AIPS1_SHIFT (23U) 624 #define MSCM_ENEDC_EN_ADD_AIPS1_WIDTH (1U) 625 #define MSCM_ENEDC_EN_ADD_AIPS1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_AIPS1_SHIFT)) & MSCM_ENEDC_EN_ADD_AIPS1_MASK) 626 627 #define MSCM_ENEDC_EN_WR_AIPS2_MASK (0x1000000U) 628 #define MSCM_ENEDC_EN_WR_AIPS2_SHIFT (24U) 629 #define MSCM_ENEDC_EN_WR_AIPS2_WIDTH (1U) 630 #define MSCM_ENEDC_EN_WR_AIPS2(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_AIPS2_SHIFT)) & MSCM_ENEDC_EN_WR_AIPS2_MASK) 631 632 #define MSCM_ENEDC_EN_ADD_AIPS2_MASK (0x2000000U) 633 #define MSCM_ENEDC_EN_ADD_AIPS2_SHIFT (25U) 634 #define MSCM_ENEDC_EN_ADD_AIPS2_WIDTH (1U) 635 #define MSCM_ENEDC_EN_ADD_AIPS2(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_AIPS2_SHIFT)) & MSCM_ENEDC_EN_ADD_AIPS2_MASK) 636 637 #define MSCM_ENEDC_EN_WR_CM7_0_TCM_MASK (0x4000000U) 638 #define MSCM_ENEDC_EN_WR_CM7_0_TCM_SHIFT (26U) 639 #define MSCM_ENEDC_EN_WR_CM7_0_TCM_WIDTH (1U) 640 #define MSCM_ENEDC_EN_WR_CM7_0_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_CM7_0_TCM_SHIFT)) & MSCM_ENEDC_EN_WR_CM7_0_TCM_MASK) 641 642 #define MSCM_ENEDC_EN_ADD_CM7_0_TCM_MASK (0x8000000U) 643 #define MSCM_ENEDC_EN_ADD_CM7_0_TCM_SHIFT (27U) 644 #define MSCM_ENEDC_EN_ADD_CM7_0_TCM_WIDTH (1U) 645 #define MSCM_ENEDC_EN_ADD_CM7_0_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_CM7_0_TCM_SHIFT)) & MSCM_ENEDC_EN_ADD_CM7_0_TCM_MASK) 646 647 #define MSCM_ENEDC_EN_WR_CM7_1_TCM_MASK (0x10000000U) 648 #define MSCM_ENEDC_EN_WR_CM7_1_TCM_SHIFT (28U) 649 #define MSCM_ENEDC_EN_WR_CM7_1_TCM_WIDTH (1U) 650 #define MSCM_ENEDC_EN_WR_CM7_1_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_WR_CM7_1_TCM_SHIFT)) & MSCM_ENEDC_EN_WR_CM7_1_TCM_MASK) 651 652 #define MSCM_ENEDC_EN_ADD_CM7_1_TCM_MASK (0x20000000U) 653 #define MSCM_ENEDC_EN_ADD_CM7_1_TCM_SHIFT (29U) 654 #define MSCM_ENEDC_EN_ADD_CM7_1_TCM_WIDTH (1U) 655 #define MSCM_ENEDC_EN_ADD_CM7_1_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_ENEDC_EN_ADD_CM7_1_TCM_SHIFT)) & MSCM_ENEDC_EN_ADD_CM7_1_TCM_MASK) 656 /*! @} */ 657 658 /*! @name IAHBCFGREG - AHB Gasket Configuration */ 659 /*! @{ */ 660 661 #define MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT_MASK (0x1U) 662 #define MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT_SHIFT (0U) 663 #define MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT_WIDTH (1U) 664 #define MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_EMAC_DIS_WR_OPT_MASK) 665 666 #define MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT_MASK (0x10U) 667 #define MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT_SHIFT (4U) 668 #define MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT_WIDTH (1U) 669 #define MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_DMA_AXBS_S0_DIS_WR_OPT_MASK) 670 671 #define MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT_MASK (0x100U) 672 #define MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT_SHIFT (8U) 673 #define MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT_WIDTH (1U) 674 #define MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_DMA_AXBS_S1_DIS_WR_OPT_MASK) 675 676 #define MSCM_IAHBCFGREG_HSE_DIS_WR_OPT_MASK (0x1000U) 677 #define MSCM_IAHBCFGREG_HSE_DIS_WR_OPT_SHIFT (12U) 678 #define MSCM_IAHBCFGREG_HSE_DIS_WR_OPT_WIDTH (1U) 679 #define MSCM_IAHBCFGREG_HSE_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_HSE_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_HSE_DIS_WR_OPT_MASK) 680 681 #define MSCM_IAHBCFGREG_TCM_DIS_WR_OPT_MASK (0x10000U) 682 #define MSCM_IAHBCFGREG_TCM_DIS_WR_OPT_SHIFT (16U) 683 #define MSCM_IAHBCFGREG_TCM_DIS_WR_OPT_WIDTH (1U) 684 #define MSCM_IAHBCFGREG_TCM_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_TCM_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_TCM_DIS_WR_OPT_MASK) 685 686 #define MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT_MASK (0x100000U) 687 #define MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT_SHIFT (20U) 688 #define MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT_WIDTH (1U) 689 #define MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_QSPI_DIS_WR_OPT_MASK) 690 691 #define MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT_MASK (0x1000000U) 692 #define MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT_SHIFT (24U) 693 #define MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT_WIDTH (1U) 694 #define MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_AIPS1_DIS_WR_OPT_MASK) 695 696 #define MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT_MASK (0x10000000U) 697 #define MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT_SHIFT (28U) 698 #define MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT_WIDTH (1U) 699 #define MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT_SHIFT)) & MSCM_IAHBCFGREG_AIPS2_DIS_WR_OPT_MASK) 700 /*! @} */ 701 702 /*! @name IRSPRC - Interrupt Router Shared Peripheral Routing Control */ 703 /*! @{ */ 704 705 #define MSCM_IRSPRC_M7_0_MASK (0x1U) 706 #define MSCM_IRSPRC_M7_0_SHIFT (0U) 707 #define MSCM_IRSPRC_M7_0_WIDTH (1U) 708 #define MSCM_IRSPRC_M7_0(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_M7_0_SHIFT)) & MSCM_IRSPRC_M7_0_MASK) 709 710 #define MSCM_IRSPRC_LOCK_MASK (0x8000U) 711 #define MSCM_IRSPRC_LOCK_SHIFT (15U) 712 #define MSCM_IRSPRC_LOCK_WIDTH (1U) 713 #define MSCM_IRSPRC_LOCK(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_LOCK_SHIFT)) & MSCM_IRSPRC_LOCK_MASK) 714 /*! @} */ 715 716 /*! 717 * @} 718 */ /* end of group MSCM_Register_Masks */ 719 720 /*! 721 * @} 722 */ /* end of group MSCM_Peripheral_Access_Layer */ 723 724 #endif /* #if !defined(S32K344_MSCM_H_) */ 725
