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Searched refs:MDATACTRL (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.h1004 …base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(r… in I3C_MasterSetWatermarks()
1021 *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; in I3C_MasterGetFifoCounts()
1025 *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; in I3C_MasterGetFifoCounts()
Dfsl_i3c.c428 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterCheckAndClearError()
1408 if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) in I3C_MasterReceive()
1762 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferBlocking()
1936 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferCreateHandle()
2382 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferNonBlocking()
2476 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferAbort()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h116 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10502 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
DMIMXRT685S_cm33.h17386 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h17386 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h20831 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19802 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
DMIMXRT595S_cm33.h26761 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h20831 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26757 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h25632 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h26760 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h40899 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
DMIMX9352_ca55.h36189 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member