Searched refs:MDATACTRL (Results 1 – 15 of 15) sorted by relevance
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/i3c/ |
D | fsl_i3c.h | 1004 …base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(r… in I3C_MasterSetWatermarks() 1021 *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; in I3C_MasterGetFifoCounts() 1025 *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; in I3C_MasterGetFifoCounts()
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D | fsl_i3c.c | 428 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterCheckAndClearError() 1408 if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) in I3C_MasterReceive() 1762 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferBlocking() 1936 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferCreateHandle() 2382 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferNonBlocking() 2476 base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; in I3C_MasterTransferAbort()
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/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/ |
D | S32Z2_I3C.h | 116 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/ |
D | MIMXRT685S_dsp.h | 10502 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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D | MIMXRT685S_cm33.h | 17386 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/ |
D | MIMXRT633S.h | 17386 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/ |
D | LPC5536.h | 20831 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/ |
D | MIMXRT595S_dsp.h | 19802 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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D | MIMXRT595S_cm33.h | 26761 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/ |
D | LPC5534.h | 20831 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/ |
D | MIMXRT533S.h | 26757 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC55S36/ |
D | LPC55S36.h | 25632 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/ |
D | MIMXRT555S.h | 26760 …__IO uint32_t MDATACTRL; /**< Master Data Control Register, offset: 0xAC */ member
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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX9352/ |
D | MIMX9352_cm33.h | 40899 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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D | MIMX9352_ca55.h | 36189 __IO uint32_t MDATACTRL; /**< Master Data Control, offset: 0xAC */ member
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